aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/SystemZ/int-div-07.ll
blob: 9cee91f7b3c6326942792ada58ea50cf07b26bae (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit division and remainder in vector registers on z13 using libcalls
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s

; Divide signed.
define i128 @f1(i128 %a, i128 %b) {
; CHECK-LABEL: f1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
; CHECK-NEXT:    .cfi_offset %r13, -56
; CHECK-NEXT:    .cfi_offset %r14, -48
; CHECK-NEXT:    .cfi_offset %r15, -40
; CHECK-NEXT:    aghi %r15, -208
; CHECK-NEXT:    .cfi_def_cfa_offset 368
; CHECK-NEXT:    vl %v0, 0(%r3), 3
; CHECK-NEXT:    vl %v1, 0(%r4), 3
; CHECK-NEXT:    lgr %r13, %r2
; CHECK-NEXT:    la %r2, 192(%r15)
; CHECK-NEXT:    la %r3, 176(%r15)
; CHECK-NEXT:    la %r4, 160(%r15)
; CHECK-NEXT:    vst %v1, 160(%r15), 3
; CHECK-NEXT:    vst %v0, 176(%r15), 3
; CHECK-NEXT:    brasl %r14, __divti3@PLT
; CHECK-NEXT:    vl %v0, 192(%r15), 3
; CHECK-NEXT:    vst %v0, 0(%r13), 3
; CHECK-NEXT:    lmg %r13, %r15, 312(%r15)
; CHECK-NEXT:    br %r14
  %res = sdiv i128 %a, %b
  ret i128 %res
}

; Divide unsigned.
define i128 @f2(i128 %a, i128 %b) {
; CHECK-LABEL: f2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
; CHECK-NEXT:    .cfi_offset %r13, -56
; CHECK-NEXT:    .cfi_offset %r14, -48
; CHECK-NEXT:    .cfi_offset %r15, -40
; CHECK-NEXT:    aghi %r15, -208
; CHECK-NEXT:    .cfi_def_cfa_offset 368
; CHECK-NEXT:    vl %v0, 0(%r3), 3
; CHECK-NEXT:    vl %v1, 0(%r4), 3
; CHECK-NEXT:    lgr %r13, %r2
; CHECK-NEXT:    la %r2, 192(%r15)
; CHECK-NEXT:    la %r3, 176(%r15)
; CHECK-NEXT:    la %r4, 160(%r15)
; CHECK-NEXT:    vst %v1, 160(%r15), 3
; CHECK-NEXT:    vst %v0, 176(%r15), 3
; CHECK-NEXT:    brasl %r14, __udivti3@PLT
; CHECK-NEXT:    vl %v0, 192(%r15), 3
; CHECK-NEXT:    vst %v0, 0(%r13), 3
; CHECK-NEXT:    lmg %r13, %r15, 312(%r15)
; CHECK-NEXT:    br %r14
  %res = udiv i128 %a, %b
  ret i128 %res
}

; Remainder signed.
define i128 @f3(i128 %a, i128 %b) {
; CHECK-LABEL: f3:
; CHECK:       # %bb.0:
; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
; CHECK-NEXT:    .cfi_offset %r13, -56
; CHECK-NEXT:    .cfi_offset %r14, -48
; CHECK-NEXT:    .cfi_offset %r15, -40
; CHECK-NEXT:    aghi %r15, -208
; CHECK-NEXT:    .cfi_def_cfa_offset 368
; CHECK-NEXT:    vl %v0, 0(%r3), 3
; CHECK-NEXT:    vl %v1, 0(%r4), 3
; CHECK-NEXT:    lgr %r13, %r2
; CHECK-NEXT:    la %r2, 192(%r15)
; CHECK-NEXT:    la %r3, 176(%r15)
; CHECK-NEXT:    la %r4, 160(%r15)
; CHECK-NEXT:    vst %v1, 160(%r15), 3
; CHECK-NEXT:    vst %v0, 176(%r15), 3
; CHECK-NEXT:    brasl %r14, __modti3@PLT
; CHECK-NEXT:    vl %v0, 192(%r15), 3
; CHECK-NEXT:    vst %v0, 0(%r13), 3
; CHECK-NEXT:    lmg %r13, %r15, 312(%r15)
; CHECK-NEXT:    br %r14
  %res = srem i128 %a, %b
  ret i128 %res
}

; Remainder unsigned.
define i128 @f4(i128 %a, i128 %b) {
; CHECK-LABEL: f4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
; CHECK-NEXT:    .cfi_offset %r13, -56
; CHECK-NEXT:    .cfi_offset %r14, -48
; CHECK-NEXT:    .cfi_offset %r15, -40
; CHECK-NEXT:    aghi %r15, -208
; CHECK-NEXT:    .cfi_def_cfa_offset 368
; CHECK-NEXT:    vl %v0, 0(%r3), 3
; CHECK-NEXT:    vl %v1, 0(%r4), 3
; CHECK-NEXT:    lgr %r13, %r2
; CHECK-NEXT:    la %r2, 192(%r15)
; CHECK-NEXT:    la %r3, 176(%r15)
; CHECK-NEXT:    la %r4, 160(%r15)
; CHECK-NEXT:    vst %v1, 160(%r15), 3
; CHECK-NEXT:    vst %v0, 176(%r15), 3
; CHECK-NEXT:    brasl %r14, __umodti3@PLT
; CHECK-NEXT:    vl %v0, 192(%r15), 3
; CHECK-NEXT:    vst %v0, 0(%r13), 3
; CHECK-NEXT:    lmg %r13, %r15, 312(%r15)
; CHECK-NEXT:    br %r14
  %res = urem i128 %a, %b
  ret i128 %res
}