1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefix=RV32I
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefix=RV64I
define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
; RV32I-LABEL: ucmp.8.8:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.8.8:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
ret i8 %1
}
define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
; RV32I-LABEL: ucmp.8.16:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.8.16:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
ret i8 %1
}
define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: ucmp.8.32:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.8.32:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
ret i8 %1
}
define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: ucmp.8.64:
; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a4, a1, a3
; RV32I-NEXT: sltu a0, a3, a1
; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.8.64:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
ret i8 %1
}
define i8 @ucmp.8.128(i128 %x, i128 %y) nounwind {
; RV32I-LABEL: ucmp.8.128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a6, 12(a0)
; RV32I-NEXT: lw a7, 8(a0)
; RV32I-NEXT: beq a6, a5, .LBB4_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t2, a6, a5
; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: sltu t2, a7, a4
; RV32I-NEXT: .LBB4_3:
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: lw t0, 0(a0)
; RV32I-NEXT: beq a3, a2, .LBB4_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: sltu a0, a3, a2
; RV32I-NEXT: j .LBB4_6
; RV32I-NEXT: .LBB4_5:
; RV32I-NEXT: sltu a0, t0, a1
; RV32I-NEXT: .LBB4_6:
; RV32I-NEXT: xor t1, a6, a5
; RV32I-NEXT: xor t3, a7, a4
; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: beqz t1, .LBB4_8
; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: mv a0, t2
; RV32I-NEXT: .LBB4_8:
; RV32I-NEXT: beq a6, a5, .LBB4_11
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: sltu a4, a5, a6
; RV32I-NEXT: bne a3, a2, .LBB4_12
; RV32I-NEXT: .LBB4_10:
; RV32I-NEXT: sltu a1, a1, t0
; RV32I-NEXT: bnez t1, .LBB4_13
; RV32I-NEXT: j .LBB4_14
; RV32I-NEXT: .LBB4_11:
; RV32I-NEXT: sltu a4, a4, a7
; RV32I-NEXT: beq a3, a2, .LBB4_10
; RV32I-NEXT: .LBB4_12:
; RV32I-NEXT: sltu a1, a2, a3
; RV32I-NEXT: beqz t1, .LBB4_14
; RV32I-NEXT: .LBB4_13:
; RV32I-NEXT: mv a1, a4
; RV32I-NEXT: .LBB4_14:
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.8.128:
; RV64I: # %bb.0:
; RV64I-NEXT: beq a1, a3, .LBB4_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sltu a4, a1, a3
; RV64I-NEXT: sltu a0, a3, a1
; RV64I-NEXT: sub a0, a0, a4
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: sltu a4, a0, a2
; RV64I-NEXT: sltu a0, a2, a0
; RV64I-NEXT: sub a0, a0, a4
; RV64I-NEXT: ret
%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
ret i8 %1
}
define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: ucmp.32.32:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.32.32:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
ret i32 %1
}
define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
; RV32I-LABEL: ucmp.32.32_sext:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.32.32_sext:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
ret i32 %1
}
define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {
; RV32I-LABEL: ucmp.32.32_zext:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.32.32_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
ret i32 %1
}
define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: ucmp.32.64:
; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB8_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a4, a1, a3
; RV32I-NEXT: sltu a0, a3, a1
; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.32.64:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
ret i32 %1
}
define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: ucmp.64.64:
; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB9_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a4, a1, a3
; RV32I-NEXT: sltu a0, a3, a1
; RV32I-NEXT: j .LBB9_3
; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: .LBB9_3:
; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: ret
;
; RV64I-LABEL: ucmp.64.64:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a2, a0, a1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
ret i64 %1
}
|
