1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
;; `.insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is
;; the raw encoding for `fadd.s`
@gf = external global float
define float @constraint_f_modifier_N_float(float %a) nounwind {
; RV32F-LABEL: constraint_f_modifier_N_float:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw fa5, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x fa4, a0
; RV32F-NEXT: #APP
; RV32F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, fa5
; RV32F-NEXT: ret
;
; RV64F-LABEL: constraint_f_modifier_N_float:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw fa5, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x fa4, a0
; RV64F-NEXT: #APP
; RV64F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, fa5
; RV64F-NEXT: ret
%1 = load float, ptr @gf
%2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(float %a, float %1)
ret float %2
}
define float @constraint_cf_modifier_N_float(float %a) nounwind {
; RV32F-LABEL: constraint_cf_modifier_N_float:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw fa5, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x fa4, a0
; RV32F-NEXT: #APP
; RV32F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, fa5
; RV32F-NEXT: ret
;
; RV64F-LABEL: constraint_cf_modifier_N_float:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw fa5, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x fa4, a0
; RV64F-NEXT: #APP
; RV64F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, fa5
; RV64F-NEXT: ret
%1 = load float, ptr @gf
%2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(float %a, float %1)
ret float %2
}
define float @modifier_N_float_abi_name(float %a) nounwind {
; RV32F-LABEL: modifier_N_float_abi_name:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw fs0, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x fa0, a0
; RV32F-NEXT: #APP
; RV32F-NEXT: .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret
;
; RV64F-LABEL: modifier_N_float_abi_name:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw fs0, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x fa0, a0
; RV64F-NEXT: #APP
; RV64F-NEXT: .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret
%1 = load float, ptr @gf
%2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa0},{fs0}"(float %a, float %1)
ret float %2
}
|
