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|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s
;
; fixed avg(x,y) = add(and(x,y),lshr(xor(x,y),1))
;
; ext avg(x,y) = trunc(lshr(add(zext(x),zext(y)),1))
;
define i8 @test_fixed_i8(i8 %a0, i8 %a1) nounwind {
; RV32I-LABEL: test_fixed_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: zext.b a1, a1
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_fixed_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: zext.b a1, a1
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%and = and i8 %a0, %a1
%xor = xor i8 %a0, %a1
%shift = lshr i8 %xor, 1
%res = add i8 %and, %shift
ret i8 %res
}
define i8 @test_ext_i8(i8 %a0, i8 %a1) nounwind {
; RV32I-LABEL: test_ext_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: zext.b a1, a1
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ext_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: zext.b a1, a1
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%x0 = zext i8 %a0 to i16
%x1 = zext i8 %a1 to i16
%sum = add i16 %x0, %x1
%shift = lshr i16 %sum, 1
%res = trunc i16 %shift to i8
ret i8 %res
}
define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {
; RV32I-LABEL: test_fixed_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_fixed_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%and = and i16 %a0, %a1
%xor = xor i16 %a0, %a1
%shift = lshr i16 %xor, 1
%res = add i16 %and, %shift
ret i16 %res
}
define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {
; RV32I-LABEL: test_ext_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ext_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%x0 = zext i16 %a0 to i32
%x1 = zext i16 %a1 to i32
%sum = add i32 %x0, %x1
%shift = lshr i32 %sum, 1
%res = trunc i32 %shift to i16
ret i16 %res
}
define i32 @test_fixed_i32(i32 %a0, i32 %a1) nounwind {
; RV32I-LABEL: test_fixed_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_fixed_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%and = and i32 %a0, %a1
%xor = xor i32 %a1, %a0
%shift = lshr i32 %xor, 1
%res = add i32 %and, %shift
ret i32 %res
}
define i32 @test_ext_i32(i32 %a0, i32 %a1) nounwind {
; RV32I-LABEL: test_ext_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ext_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%x0 = zext i32 %a0 to i64
%x1 = zext i32 %a1 to i64
%sum = add i64 %x0, %x1
%shift = lshr i64 %sum, 1
%res = trunc i64 %shift to i32
ret i32 %res
}
define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-LABEL: test_fixed_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: add a1, a3, a1
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: sltu a2, a0, a2
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: beq a1, a3, .LBB6_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a1, a3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: slli a2, a2, 31
; RV32I-NEXT: srli a3, a1, 1
; RV32I-NEXT: slli a4, a1, 31
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a1, a3, a2
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_fixed_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: ret
%and = and i64 %a0, %a1
%xor = xor i64 %a1, %a0
%shift = lshr i64 %xor, 1
%res = add i64 %and, %shift
ret i64 %res
}
define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-LABEL: test_ext_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: add a1, a3, a1
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: sltu a2, a0, a2
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: beq a1, a3, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a1, a3
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: slli a2, a2, 31
; RV32I-NEXT: srli a3, a1, 1
; RV32I-NEXT: slli a4, a1, 31
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a1, a3, a2
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ext_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: ret
%x0 = zext i64 %a0 to i128
%x1 = zext i64 %a1 to i128
%sum = add i128 %x0, %x1
%shift = lshr i128 %sum, 1
%res = trunc i128 %shift to i64
ret i64 %res
}
|
