1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
declare float @fminf(float, float)
declare double @fmin(double, double)
declare ppc_fp128 @fminl(ppc_fp128, ppc_fp128)
declare float @llvm.minnum.f32(float, float)
declare double @llvm.minnum.f64(double, double)
declare ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128, ppc_fp128)
declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)
define float @test_fminf(float %x, float %y) {
; CHECK-LABEL: test_fminf:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fminf
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call float @fminf(float %x, float %y) readnone
ret float %z
}
define double @test_fmin(double %x, double %y) {
; CHECK-LABEL: test_fmin:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fmin
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call double @fmin(double %x, double %y) readnone
ret double %z
}
define ppc_fp128 @test_fminl(ppc_fp128 %x, ppc_fp128 %y) {
; CHECK-LABEL: test_fminl:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -112(1)
; CHECK-NEXT: stw 0, 116(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stfd 3, 72(1)
; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: stfd 4, 64(1)
; CHECK-NEXT: stw 3, 52(1)
; CHECK-NEXT: lwz 3, 32(1)
; CHECK-NEXT: lfd 1, 56(1)
; CHECK-NEXT: stw 3, 48(1)
; CHECK-NEXT: lwz 3, 76(1)
; CHECK-NEXT: lfd 2, 48(1)
; CHECK-NEXT: stw 3, 92(1)
; CHECK-NEXT: lwz 3, 72(1)
; CHECK-NEXT: stw 3, 88(1)
; CHECK-NEXT: lwz 3, 68(1)
; CHECK-NEXT: lfd 3, 88(1)
; CHECK-NEXT: stw 3, 84(1)
; CHECK-NEXT: lwz 3, 64(1)
; CHECK-NEXT: stw 3, 80(1)
; CHECK-NEXT: lfd 4, 80(1)
; CHECK-NEXT: bl fminl
; CHECK-NEXT: stfd 1, 16(1)
; CHECK-NEXT: lwz 3, 20(1)
; CHECK-NEXT: stfd 2, 24(1)
; CHECK-NEXT: stw 3, 108(1)
; CHECK-NEXT: lwz 3, 16(1)
; CHECK-NEXT: stw 3, 104(1)
; CHECK-NEXT: lwz 3, 28(1)
; CHECK-NEXT: lfd 1, 104(1)
; CHECK-NEXT: stw 3, 100(1)
; CHECK-NEXT: lwz 3, 24(1)
; CHECK-NEXT: stw 3, 96(1)
; CHECK-NEXT: lfd 2, 96(1)
; CHECK-NEXT: lwz 0, 116(1)
; CHECK-NEXT: addi 1, 1, 112
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call ppc_fp128 @fminl(ppc_fp128 %x, ppc_fp128 %y) readnone
ret ppc_fp128 %z
}
define float @test_intrinsic_fmin_f32(float %x, float %y) {
; CHECK-LABEL: test_intrinsic_fmin_f32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fminf
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call float @llvm.minnum.f32(float %x, float %y) readnone
ret float %z
}
define double @test_intrinsic_fmin_f64(double %x, double %y) {
; CHECK-LABEL: test_intrinsic_fmin_f64:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fmin
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call double @llvm.minnum.f64(double %x, double %y) readnone
ret double %z
}
define ppc_fp128 @test_intrinsic_fmin_f128(ppc_fp128 %x, ppc_fp128 %y) {
; CHECK-LABEL: test_intrinsic_fmin_f128:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -112(1)
; CHECK-NEXT: stw 0, 116(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stfd 3, 72(1)
; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: stfd 4, 64(1)
; CHECK-NEXT: stw 3, 52(1)
; CHECK-NEXT: lwz 3, 32(1)
; CHECK-NEXT: lfd 1, 56(1)
; CHECK-NEXT: stw 3, 48(1)
; CHECK-NEXT: lwz 3, 76(1)
; CHECK-NEXT: lfd 2, 48(1)
; CHECK-NEXT: stw 3, 92(1)
; CHECK-NEXT: lwz 3, 72(1)
; CHECK-NEXT: stw 3, 88(1)
; CHECK-NEXT: lwz 3, 68(1)
; CHECK-NEXT: lfd 3, 88(1)
; CHECK-NEXT: stw 3, 84(1)
; CHECK-NEXT: lwz 3, 64(1)
; CHECK-NEXT: stw 3, 80(1)
; CHECK-NEXT: lfd 4, 80(1)
; CHECK-NEXT: bl fminl
; CHECK-NEXT: stfd 1, 16(1)
; CHECK-NEXT: lwz 3, 20(1)
; CHECK-NEXT: stfd 2, 24(1)
; CHECK-NEXT: stw 3, 108(1)
; CHECK-NEXT: lwz 3, 16(1)
; CHECK-NEXT: stw 3, 104(1)
; CHECK-NEXT: lwz 3, 28(1)
; CHECK-NEXT: lfd 1, 104(1)
; CHECK-NEXT: stw 3, 100(1)
; CHECK-NEXT: lwz 3, 24(1)
; CHECK-NEXT: stw 3, 96(1)
; CHECK-NEXT: lfd 2, 96(1)
; CHECK-NEXT: lwz 0, 116(1)
; CHECK-NEXT: addi 1, 1, 112
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %x, ppc_fp128 %y) readnone
ret ppc_fp128 %z
}
define <2 x float> @test_intrinsic_fminf_v2f32(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: test_intrinsic_fminf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -32(1)
; CHECK-NEXT: stw 0, 36(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: .cfi_offset f29, -24
; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: stfd 30, 16(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 30, 2
; CHECK-NEXT: fmr 2, 3
; CHECK-NEXT: stfd 29, 8(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, 24(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 31, 4
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 29, 1
; CHECK-NEXT: fmr 1, 30
; CHECK-NEXT: fmr 2, 31
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 2, 1
; CHECK-NEXT: fmr 1, 29
; CHECK-NEXT: lfd 31, 24(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 16(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 29, 8(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 0, 36(1)
; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
ret <2 x float> %z
}
define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: test_intrinsic_fmin_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -64(1)
; CHECK-NEXT: stw 0, 68(1)
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: .cfi_offset f25, -56
; CHECK-NEXT: .cfi_offset f26, -48
; CHECK-NEXT: .cfi_offset f27, -40
; CHECK-NEXT: .cfi_offset f28, -32
; CHECK-NEXT: .cfi_offset f29, -24
; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: stfd 26, 16(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 26, 2
; CHECK-NEXT: fmr 2, 5
; CHECK-NEXT: stfd 25, 8(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 27, 24(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 27, 3
; CHECK-NEXT: stfd 28, 32(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 28, 4
; CHECK-NEXT: stfd 29, 40(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 29, 6
; CHECK-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 30, 7
; CHECK-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 31, 8
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 25, 1
; CHECK-NEXT: fmr 1, 26
; CHECK-NEXT: fmr 2, 29
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 29, 1
; CHECK-NEXT: fmr 1, 27
; CHECK-NEXT: fmr 2, 30
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 30, 1
; CHECK-NEXT: fmr 1, 28
; CHECK-NEXT: fmr 2, 31
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 4, 1
; CHECK-NEXT: fmr 1, 25
; CHECK-NEXT: fmr 2, 29
; CHECK-NEXT: fmr 3, 30
; CHECK-NEXT: lfd 31, 56(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 48(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 29, 40(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 28, 32(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 27, 24(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 26, 16(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 25, 8(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 0, 68(1)
; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
ret <4 x float> %z
}
define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
; CHECK-LABEL: test_intrinsic_fmin_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -128(1)
; CHECK-NEXT: stw 0, 132(1)
; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: .cfi_offset f17, -120
; CHECK-NEXT: .cfi_offset f18, -112
; CHECK-NEXT: .cfi_offset f19, -104
; CHECK-NEXT: .cfi_offset f20, -96
; CHECK-NEXT: .cfi_offset f21, -88
; CHECK-NEXT: .cfi_offset f22, -80
; CHECK-NEXT: .cfi_offset f23, -72
; CHECK-NEXT: .cfi_offset f24, -64
; CHECK-NEXT: .cfi_offset f25, -56
; CHECK-NEXT: .cfi_offset f26, -48
; CHECK-NEXT: .cfi_offset f27, -40
; CHECK-NEXT: .cfi_offset f28, -32
; CHECK-NEXT: .cfi_offset f29, -24
; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: stfd 25, 72(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 25, 2
; CHECK-NEXT: lfs 2, 136(1)
; CHECK-NEXT: stfd 17, 8(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 18, 16(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 19, 24(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 20, 32(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 21, 40(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 22, 48(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 23, 56(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 24, 64(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 26, 80(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 26, 3
; CHECK-NEXT: stfd 27, 88(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 27, 4
; CHECK-NEXT: stfd 28, 96(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 28, 5
; CHECK-NEXT: stfd 29, 104(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 29, 6
; CHECK-NEXT: stfd 30, 112(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 30, 7
; CHECK-NEXT: stfd 31, 120(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 31, 8
; CHECK-NEXT: lfs 24, 164(1)
; CHECK-NEXT: lfs 23, 160(1)
; CHECK-NEXT: lfs 22, 156(1)
; CHECK-NEXT: lfs 21, 152(1)
; CHECK-NEXT: lfs 20, 148(1)
; CHECK-NEXT: lfs 19, 144(1)
; CHECK-NEXT: lfs 18, 140(1)
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 17, 1
; CHECK-NEXT: fmr 1, 25
; CHECK-NEXT: fmr 2, 18
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 25, 1
; CHECK-NEXT: fmr 1, 26
; CHECK-NEXT: fmr 2, 19
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 26, 1
; CHECK-NEXT: fmr 1, 27
; CHECK-NEXT: fmr 2, 20
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 27, 1
; CHECK-NEXT: fmr 1, 28
; CHECK-NEXT: fmr 2, 21
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 28, 1
; CHECK-NEXT: fmr 1, 29
; CHECK-NEXT: fmr 2, 22
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 29, 1
; CHECK-NEXT: fmr 1, 30
; CHECK-NEXT: fmr 2, 23
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 30, 1
; CHECK-NEXT: fmr 1, 31
; CHECK-NEXT: fmr 2, 24
; CHECK-NEXT: bl fminf
; CHECK-NEXT: fmr 8, 1
; CHECK-NEXT: fmr 1, 17
; CHECK-NEXT: fmr 2, 25
; CHECK-NEXT: fmr 3, 26
; CHECK-NEXT: fmr 4, 27
; CHECK-NEXT: fmr 5, 28
; CHECK-NEXT: fmr 6, 29
; CHECK-NEXT: fmr 7, 30
; CHECK-NEXT: lfd 31, 120(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 112(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 29, 104(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 28, 96(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 27, 88(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 26, 80(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 25, 72(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 24, 64(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 23, 56(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 22, 48(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 21, 40(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 20, 32(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 19, 24(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 18, 16(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 17, 8(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 0, 132(1)
; CHECK-NEXT: addi 1, 1, 128
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
ret <8 x float> %z
}
define ppc_fp128 @fminnum_const(ppc_fp128 %0) {
; CHECK-LABEL: fminnum_const:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -96(1)
; CHECK-NEXT: stw 0, 100(1)
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 3, 76(1)
; CHECK-NEXT: lis 4, 16368
; CHECK-NEXT: stw 3, 68(1)
; CHECK-NEXT: stw 3, 64(1)
; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stw 4, 72(1)
; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: lfd 3, 72(1)
; CHECK-NEXT: stw 3, 52(1)
; CHECK-NEXT: lwz 3, 32(1)
; CHECK-NEXT: lfd 4, 64(1)
; CHECK-NEXT: stw 3, 48(1)
; CHECK-NEXT: lfd 1, 56(1)
; CHECK-NEXT: lfd 2, 48(1)
; CHECK-NEXT: bl fminl
; CHECK-NEXT: stfd 1, 16(1)
; CHECK-NEXT: lwz 3, 20(1)
; CHECK-NEXT: stfd 2, 24(1)
; CHECK-NEXT: stw 3, 92(1)
; CHECK-NEXT: lwz 3, 16(1)
; CHECK-NEXT: stw 3, 88(1)
; CHECK-NEXT: lwz 3, 28(1)
; CHECK-NEXT: lfd 1, 88(1)
; CHECK-NEXT: stw 3, 84(1)
; CHECK-NEXT: lwz 3, 24(1)
; CHECK-NEXT: stw 3, 80(1)
; CHECK-NEXT: lfd 2, 80(1)
; CHECK-NEXT: lwz 0, 100(1)
; CHECK-NEXT: addi 1, 1, 96
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%2 = tail call fast ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %0, ppc_fp128 0xM3FF00000000000000000000000000000)
ret ppc_fp128 %2
}
|
