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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-Fn32-i64:64-n32"
target triple = "powerpc-unknown-linux-gnu"
@md_seq_show___trans_tmp_57 = external global i8
define i32 @md_seq_show(i64 %0, i32 %1) #0 {
; CHECK-LABEL: name: md_seq_show
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: liveins: $r3, $r4, $r5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprc = COPY $r5
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY $r4
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY $r3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]]
; CHECK-NEXT: [[ADDIC:%[0-9]+]]:gprc = ADDIC [[COPY1]], 1, implicit-def $carry
; CHECK-NEXT: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI killed [[ADDIC]], 1
; CHECK-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
; CHECK-NEXT: [[LI1:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
; CHECK-NEXT: BCC 44, [[CMPLWI]], %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.entry:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: liveins: $carry
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
; CHECK-NEXT: liveins: $carry
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gprc_and_gprc_nor0 = PHI [[LI]], %bb.3, [[LI1]], %bb.0
; CHECK-NEXT: [[ADDZE:%[0-9]+]]:gprc = ADDZE [[COPY2]], implicit-def dead $carry, implicit $carry
; CHECK-NEXT: [[ADDIC1:%[0-9]+]]:gprc = ADDIC [[ADDZE]], -1, implicit-def $carry
; CHECK-NEXT: [[SUBFE:%[0-9]+]]:gprc_and_gprc_nor0 = SUBFE killed [[ADDIC1]], [[ADDZE]], implicit-def dead $carry, implicit $carry
; CHECK-NEXT: [[CMPLWI1:%[0-9]+]]:crrc = CMPLWI [[ADDZE]], 0
; CHECK-NEXT: BCC 76, [[CMPLWI1]], %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.6(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
; CHECK-NEXT: successors: %bb.1(0x55555556), %bb.2(0x2aaaaaaa)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprc = PHI [[SUBFE]], %bb.5, [[PHI]], %bb.4
; CHECK-NEXT: [[CMPLWI2:%[0-9]+]]:crrc = CMPLWI killed [[PHI1]], 0
; CHECK-NEXT: BCC 68, killed [[CMPLWI2]], %bb.2
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond.i.preheader:
; CHECK-NEXT: [[LI2:%[0-9]+]]:gprc = LI 0
; CHECK-NEXT: $r3 = COPY [[LI2]]
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.status_resync.exit:
; CHECK-NEXT: [[ADDIC2:%[0-9]+]]:gprc = ADDIC [[COPY]], -1, implicit-def $carry
; CHECK-NEXT: [[SUBFE1:%[0-9]+]]:gprc = SUBFE killed [[ADDIC2]], [[COPY]], implicit-def dead $carry, implicit $carry
; CHECK-NEXT: [[LIS:%[0-9]+]]:gprc_and_gprc_nor0 = LIS target-flags(ppc-ha) @md_seq_show___trans_tmp_57
; CHECK-NEXT: STB killed [[SUBFE1]], target-flags(ppc-lo) @md_seq_show___trans_tmp_57, killed [[LIS]] :: (store (s8) into @md_seq_show___trans_tmp_57)
; CHECK-NEXT: [[LI3:%[0-9]+]]:gprc = LI 0
; CHECK-NEXT: $r3 = COPY [[LI3]]
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
entry:
switch i64 %0, label %status_resync.exit [
i64 -1, label %for.cond.i.preheader
i64 0, label %for.cond.i.preheader
]
for.cond.i.preheader: ; preds = %entry, %entry
ret i32 0
status_resync.exit: ; preds = %entry
%tobool = icmp ne i32 %1, 0
%storedv = zext i1 %tobool to i8
store i8 %storedv, ptr @md_seq_show___trans_tmp_57, align 1
ret i32 0
}
attributes #0 = { "target-features"="-aix-shared-lib-tls-model-opt,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
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