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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s
name: sink-store-load-dep
tracksRegLiveness: true
stack:
- { id: 0, type: default, size: 8, alignment: 8 }
body: |
bb.0:
; CHECK-LABEL: name: sink-store-load-dep
; CHECK: bb.0:
; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32))
; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16))
; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg
; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2:
; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg
%0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32))
%1:gpr = MOVi 55296, 14, $noreg, $noreg
%2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg
%3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16))
%4:gpr = MOVi 0, 14, $noreg, $noreg
early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg
%6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg
CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr
Bcc %bb.2, 3, $cpsr
B %bb.1
bb.1:
%8:gpr = MOVi 0, 14, $noreg, $noreg
$r0 = COPY %8:gpr
BX_RET 14, $noreg, implicit $r0
bb.2:
%9:gpr = MOVi %3:gpr, 14, $noreg, $noreg
$r0 = COPY %9:gpr
BX_RET 14, $noreg, implicit $r0
...
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