1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--- |
target triple = "armv7---gnueabi"
define i32 @test1(i32 %x) {
entry:
unreachable
}
define i32 @test2(i32 %x) {
entry:
unreachable
}
define i32 @test3(i32 %x) {
entry:
unreachable
}
define i32 @test4(i32 %x) {
entry:
unreachable
}
@var = global i32 0
define i32 @test5(i32 %x) {
entry:
unreachable
}
define i32 @vbsl_kill_flags(i32 %x) {
unreachable
}
...
---
name: test1
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0
; CHECK-LABEL: name: test1
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $r1 = MOVi16 500, 0 /* CC::eq */, killed $cpsr, implicit killed $r1
; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r1 = MOVi 2, 14, $noreg, $noreg
CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
$r0 = MOVr killed $r1, 14, $noreg, $noreg
BX_RET 14, $noreg, implicit $r0
...
---
name: test2
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0
; CHECK-LABEL: name: test2
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $r1 = MOVi16 2068, 0 /* CC::eq */, $cpsr, implicit killed $r1
; CHECK-NEXT: $r1 = MOVTi16 $r1, 7637, 0 /* CC::eq */, $cpsr
; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r1 = MOVi 2, 14, $noreg, $noreg
CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
$r0 = MOVr killed $r1, 14, $noreg, $noreg
BX_RET 14, $noreg, implicit $r0
...
---
name: test3
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0, $r1
; CHECK-LABEL: name: test3
; CHECK: liveins: $r0, $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $r0 = MOVr killed $r1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit killed $r0
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
$r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
BX_RET 14, $noreg, implicit $r0
...
---
name: test4
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r0_r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0, $r0_r1
; CHECK-LABEL: name: test4
; CHECK: liveins: $r0, $r0_r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r0 = MOVi16 51712, 14 /* CC::al */, $noreg, implicit-def $r0_r1
; CHECK-NEXT: $r0 = MOVTi16 $r0, 15258, 14 /* CC::al */, $noreg, implicit-def $r0_r1
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r0 = MOVi32imm 1000000000, implicit-def $r0_r1
BX_RET 14, $noreg, implicit $r0
...
---
name: test5
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r0_r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0, $r0_r1
; CHECK-LABEL: name: test5
; CHECK: liveins: $r0, $r0_r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r0 = MOVi16_ga_pcrel target-flags(arm-lo16) @var, 0, implicit-def $r0_r1
; CHECK-NEXT: $r0 = MOVTi16_ga_pcrel $r0, target-flags(arm-hi16) @var, 0, implicit-def $r0_r1
; CHECK-NEXT: $r0 = PICLDR $r0, 0, 14 /* CC::al */, $noreg, implicit-def $r0_r1
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r0 = MOV_ga_pcrel_ldr @var, implicit-def $r0_r1
BX_RET 14, $noreg, implicit $r0
...
---
name: vbsl_kill_flags
alignment: 4
tracksRegLiveness: true
body: |
bb.0 (%ir-block.0):
liveins: $d1
; CHECK-LABEL: name: vbsl_kill_flags
; CHECK: liveins: $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $d0 = VORRd renamable $d1, renamable $d1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $d0 = VBSLd killed renamable $d0, renamable $d1, renamable $d1, 14 /* CC::al */, $noreg
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
renamable $d0 = VBSPd killed renamable $d1, renamable $d1, renamable $d1, 14 /* CC::al */, $noreg
BX_RET 14 /* CC::al */, $noreg, implicit $d0
...
|
