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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to
; create vselects with i64 condition masks.
; FIXME: Should be able to avoid intermediate vselect
define amdgpu_kernel void @widen_vselect_and_mask_v4f64(<4 x double> %arg) #0 {
; GCN-LABEL: widen_vselect_and_mask_v4f64:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[4:5], 16
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_mov_b32_e32 v1, v0
; GCN-NEXT: v_mov_b32_e32 v2, v0
; GCN-NEXT: v_mov_b32_e32 v3, v0
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: v_cmp_u_f64_e64 s[2:3], s[0:1], s[0:1]
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[2:3]
; GCN-NEXT: v_cmp_neq_f64_e64 s[0:1], s[0:1], 0
; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[1:2]
; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GCN-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: v_mov_b32_e32 v2, v0
; GCN-NEXT: v_mov_b32_e32 v1, s0
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm
bb:
%tmp = extractelement <4 x double> %arg, i64 0
%tmp1 = fcmp uno double %tmp, 0.000000e+00
%tmp2 = sext i1 %tmp1 to i64
%tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 0
%tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 1
%tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 2
%tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 3
%tmp7 = fcmp une <4 x double> %arg, zeroinitializer
%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
%tmp9 = and <4 x i1> %tmp8, %tmp7
%tmp10 = select <4 x i1> %tmp9, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, <4 x double> zeroinitializer
store <4 x double> %tmp10, ptr addrspace(1) null, align 32
ret void
}
define amdgpu_kernel void @widen_vselect_and_mask_v4i64(<4 x i64> %arg) #0 {
; GCN-LABEL: widen_vselect_and_mask_v4i64:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_mov_b64 s[8:9], 16
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1
; GCN-NEXT: v_mov_b32_e32 v1, v0
; GCN-NEXT: v_mov_b32_e32 v2, v0
; GCN-NEXT: v_mov_b32_e32 v3, v0
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[0:1], 0
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[2:3]
; GCN-NEXT: v_cmp_ne_u64_e64 s[0:1], s[0:1], 0
; GCN-NEXT: v_mov_b32_e32 v5, v4
; GCN-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[4:5]
; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: v_mov_b32_e32 v5, v0
; GCN-NEXT: v_mov_b32_e32 v6, v0
; GCN-NEXT: v_mov_b32_e32 v7, v0
; GCN-NEXT: s_mov_b32 s6, s10
; GCN-NEXT: s_mov_b32 s7, s11
; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; GCN-NEXT: s_endpgm
bb:
%tmp = extractelement <4 x i64> %arg, i64 0
%tmp1 = icmp eq i64 %tmp, 0
%tmp2 = sext i1 %tmp1 to i64
%tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 0
%tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 1
%tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 2
%tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 3
%tmp7 = icmp ne <4 x i64> %arg, zeroinitializer
%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
%tmp9 = and <4 x i1> %tmp8, %tmp7
%tmp10 = select <4 x i1> %tmp9, <4 x i64> <i64 1, i64 1, i64 1, i64 1>, <4 x i64> zeroinitializer
store <4 x i64> %tmp10, ptr addrspace(1) null, align 32
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone speculatable }
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