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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
# Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE.
---
name: f
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: f
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: $vgpr2_vgpr3 = COPY [[COPY]]
; CHECK-NEXT: S_NOP 0, implicit $vgpr2_vgpr3
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%35:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
$vgpr2_vgpr3 = COPY %35
S_NOP 0, implicit $vgpr2_vgpr3
...
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