1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
;; Test reduction of:
;;
;; DST = lshr i64 X, Y
;;
;; where Y is in the range [63-32] to:
;;
;; DST = [srl i32 X, (Y & 0x1F), 0]
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Test range with metadata
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
define i64 @srl_metadata(i64 %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_metadata:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dword v0, v[2:3]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v0, v1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}
%srl = lshr i64 %arg0, %shift.amt
ret i64 %srl
}
define amdgpu_ps i64 @srl_metadata_sgpr_return(i64 inreg %arg0, ptr addrspace(1) inreg %arg1.ptr) {
; CHECK-LABEL: srl_metadata_sgpr_return:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s0, s[2:3], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_lshr_b32 s0, s1, s0
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: ; return to shader part epilog
%shift.amt = load i64, ptr addrspace(1) %arg1.ptr, !range !0, !noundef !{}
%srl = lshr i64 %arg0, %shift.amt
ret i64 %srl
}
; Exact attribute does not inhibit reduction
define i64 @srl_exact_metadata(i64 %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_exact_metadata:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dword v0, v[2:3]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v0, v1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}
%srl = lshr exact i64 %arg0, %shift.amt
ret i64 %srl
}
define i64 @srl_metadata_two_ranges(i64 %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_metadata_two_ranges:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dword v0, v[2:3]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v0, v1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load i64, ptr %arg1.ptr, !range !1, !noundef !{}
%srl = lshr i64 %arg0, %shift.amt
ret i64 %srl
}
; Known minimum is too low. Reduction must not be done.
define i64 @srl_metadata_out_of_range(i64 %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_metadata_out_of_range:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dword v2, v[2:3]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load i64, ptr %arg1.ptr, !range !2, !noundef !{}
%srl = lshr i64 %arg0, %shift.amt
ret i64 %srl
}
; Bounds cannot be truncated to i32 when load is narrowed to i32.
; Reduction must not be done.
; Bounds were chosen so that if bounds were truncated to i32 the
; known minimum would be 32 and the srl would be erroneously reduced.
define i64 @srl_metadata_cant_be_narrowed_to_i32(i64 %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_metadata_cant_be_narrowed_to_i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dword v2, v[2:3]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load i64, ptr %arg1.ptr, !range !3, !noundef !{}
%srl = lshr i64 %arg0, %shift.amt
ret i64 %srl
}
define <2 x i64> @srl_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_v2_metadata:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v4, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v3
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}
%srl = lshr <2 x i64> %arg0, %shift.amt
ret <2 x i64> %srl
}
; Exact attribute does not inhibit reduction
define <2 x i64> @srl_exact_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_exact_v2_metadata:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v4, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v3
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}
%srl = lshr exact <2 x i64> %arg0, %shift.amt
ret <2 x i64> %srl
}
define <3 x i64> @srl_v3_metadata(<3 x i64> %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_v3_metadata:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dword v0, v[6:7] offset:16
; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[6:7]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v4, v0, v5
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v8, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v10, v3
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}
%srl = lshr <3 x i64> %arg0, %shift.amt
ret <3 x i64> %srl
}
define <4 x i64> @srl_v4_metadata(<4 x i64> %arg0, ptr %arg1.ptr) {
; CHECK-LABEL: srl_v4_metadata:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dwordx4 v[10:13], v[8:9]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_load_dwordx4 v[13:16], v[8:9] offset:16
; CHECK-NEXT: ; kill: killed $vgpr8 killed $vgpr9
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v10, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v12, v3
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v4, v13, v5
; CHECK-NEXT: v_lshrrev_b32_e32 v6, v15, v7
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: v_mov_b32_e32 v7, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}
%srl = lshr <4 x i64> %arg0, %shift.amt
ret <4 x i64> %srl
}
!0 = !{i64 32, i64 64}
!1 = !{i64 32, i64 38, i64 42, i64 48}
!2 = !{i64 31, i64 38, i64 42, i64 48}
!3 = !{i64 32, i64 38, i64 2147483680, i64 2147483681}
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Test range with an "or X, 16"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; These cases must not be reduced because the known minimum, 16, is not in range.
define i64 @srl_or16(i64 %arg0, i64 %shift_amt) {
; CHECK-LABEL: srl_or16:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v2, 16, v2
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %shift_amt, 16
%srl = lshr i64 %arg0, %or
ret i64 %srl
}
define <2 x i64> @srl_v2_or16(<2 x i64> %arg0, <2 x i64> %shift_amt) {
; CHECK-LABEL: srl_v2_or16:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v5, 16, v6
; CHECK-NEXT: v_or_b32_e32 v4, 16, v4
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], v5, v[2:3]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <2 x i64> %shift_amt, splat (i64 16)
%srl = lshr <2 x i64> %arg0, %or
ret <2 x i64> %srl
}
define <3 x i64> @srl_v3_or16(<3 x i64> %arg0, <3 x i64> %shift_amt) {
; CHECK-LABEL: srl_v3_or16:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v7, 16, v10
; CHECK-NEXT: v_or_b32_e32 v8, 16, v8
; CHECK-NEXT: v_or_b32_e32 v6, 16, v6
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v6, v[0:1]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], v8, v[2:3]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], v7, v[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <3 x i64> %shift_amt, splat (i64 16)
%srl = lshr <3 x i64> %arg0, %or
ret <3 x i64> %srl
}
define <4 x i64> @srl_v4_or16(<4 x i64> %arg0, <4 x i64> %shift_amt) {
; CHECK-LABEL: srl_v4_or16:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v9, 16, v14
; CHECK-NEXT: v_or_b32_e32 v11, 16, v12
; CHECK-NEXT: v_or_b32_e32 v10, 16, v10
; CHECK-NEXT: v_or_b32_e32 v8, 16, v8
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v8, v[0:1]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], v10, v[2:3]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], v11, v[4:5]
; CHECK-NEXT: v_lshrrev_b64 v[6:7], v9, v[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <4 x i64> %shift_amt, splat (i64 16)
%srl = lshr <4 x i64> %arg0, %or
ret <4 x i64> %srl
}
; test SGPR
define i64 @srl_or16_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {
; CHECK-LABEL: srl_or16_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_or_b32 s4, s18, 16
; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %shift_amt, 16
%srl = lshr i64 %arg0, %or
ret i64 %srl
}
define amdgpu_ps i64 @srl_or16_sgpr_return(i64 inreg %arg0, i64 inreg %shift_amt) {
; CHECK-LABEL: srl_or16_sgpr_return:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b32 s2, s2, 16
; CHECK-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; CHECK-NEXT: ; return to shader part epilog
%or = or i64 %shift_amt, 16
%srl = lshr i64 %arg0, %or
ret i64 %srl
}
define <2 x i64> @srl_v2_or16_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {
; CHECK-LABEL: srl_v2_or16_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_or_b32 s6, s22, 16
; CHECK-NEXT: s_or_b32 s4, s20, 16
; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4
; CHECK-NEXT: s_lshr_b64 s[6:7], s[18:19], s6
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: v_mov_b32_e32 v2, s6
; CHECK-NEXT: v_mov_b32_e32 v3, s7
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <2 x i64> %shift_amt, splat (i64 16)
%srl = lshr <2 x i64> %arg0, %or
ret <2 x i64> %srl
}
define <3 x i64> @srl_v3_or16_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {
; CHECK-LABEL: srl_v3_or16_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_or_b32 s8, s26, 16
; CHECK-NEXT: s_or_b32 s6, s24, 16
; CHECK-NEXT: s_or_b32 s4, s22, 16
; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4
; CHECK-NEXT: s_lshr_b64 s[6:7], s[18:19], s6
; CHECK-NEXT: s_lshr_b64 s[8:9], s[20:21], s8
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: v_mov_b32_e32 v2, s6
; CHECK-NEXT: v_mov_b32_e32 v3, s7
; CHECK-NEXT: v_mov_b32_e32 v4, s8
; CHECK-NEXT: v_mov_b32_e32 v5, s9
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <3 x i64> %shift_amt, splat (i64 16)
%srl = lshr <3 x i64> %arg0, %or
ret <3 x i64> %srl
}
define <4 x i64> @srl_v4_or16_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {
; CHECK-LABEL: srl_v4_or16_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v0, 16, v0
; CHECK-NEXT: s_or_b32 s8, s28, 16
; CHECK-NEXT: s_or_b32 s6, s26, 16
; CHECK-NEXT: s_or_b32 s4, s24, 16
; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4
; CHECK-NEXT: s_lshr_b64 s[6:7], s[18:19], s6
; CHECK-NEXT: s_lshr_b64 s[8:9], s[20:21], s8
; CHECK-NEXT: v_lshrrev_b64 v[6:7], v0, s[22:23]
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: v_mov_b32_e32 v2, s6
; CHECK-NEXT: v_mov_b32_e32 v3, s7
; CHECK-NEXT: v_mov_b32_e32 v4, s8
; CHECK-NEXT: v_mov_b32_e32 v5, s9
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <4 x i64> %shift_amt, splat (i64 16)
%srl = lshr <4 x i64> %arg0, %or
ret <4 x i64> %srl
}
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Test range with an "or X, 32"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; These cases are reduced because computeKnownBits() can calculate a minimum of 32
; based on the OR with 32.
define i64 @srl_or32(i64 %arg0, i64 %shift_amt) {
; CHECK-LABEL: srl_or32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v2, v1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %shift_amt, 32
%srl = lshr i64 %arg0, %or
ret i64 %srl
}
define <2 x i64> @srl_v2_or32(<2 x i64> %arg0, <2 x i64> %shift_amt) {
; CHECK-LABEL: srl_v2_or32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v4, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v3
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <2 x i64> %shift_amt, splat (i64 32)
%srl = lshr <2 x i64> %arg0, %or
ret <2 x i64> %srl
}
define <3 x i64> @srl_v3_or32(<3 x i64> %arg0, <3 x i64> %shift_amt) {
; CHECK-LABEL: srl_v3_or32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v6, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v8, v3
; CHECK-NEXT: v_lshrrev_b32_e32 v4, v10, v5
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <3 x i64> %shift_amt, splat (i64 32)
%srl = lshr <3 x i64> %arg0, %or
ret <3 x i64> %srl
}
define <4 x i64> @srl_v4_or32(<4 x i64> %arg0, <4 x i64> %shift_amt) {
; CHECK-LABEL: srl_v4_or32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v8, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, v10, v3
; CHECK-NEXT: v_lshrrev_b32_e32 v4, v12, v5
; CHECK-NEXT: v_lshrrev_b32_e32 v6, v14, v7
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: v_mov_b32_e32 v7, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <4 x i64> %shift_amt, splat (i64 32)
%srl = lshr <4 x i64> %arg0, %or
ret <4 x i64> %srl
}
; test SGPR
define i64 @srl_or32_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {
; CHECK-LABEL: srl_or32_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_lshr_b32 s4, s17, s18
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %shift_amt, 32
%srl = lshr i64 %arg0, %or
ret i64 %srl
}
define amdgpu_ps i64 @srl_or32_sgpr_return(i64 inreg %arg0, i64 inreg %shift_amt) {
; CHECK-LABEL: srl_or32_sgpr_return:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_lshr_b32 s0, s1, s2
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: ; return to shader part epilog
%or = or i64 %shift_amt, 32
%srl = lshr i64 %arg0, %or
ret i64 %srl
}
define <2 x i64> @srl_v2_or32_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {
; CHECK-LABEL: srl_v2_or32_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_lshr_b32 s4, s17, s20
; CHECK-NEXT: s_lshr_b32 s5, s19, s22
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v2, s5
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <2 x i64> %shift_amt, splat (i64 32)
%srl = lshr <2 x i64> %arg0, %or
ret <2 x i64> %srl
}
define <3 x i64> @srl_v3_or32_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {
; CHECK-LABEL: srl_v3_or32_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_lshr_b32 s4, s17, s22
; CHECK-NEXT: s_lshr_b32 s5, s19, s24
; CHECK-NEXT: s_lshr_b32 s6, s21, s26
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v2, s5
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v4, s6
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <3 x i64> %shift_amt, splat (i64 32)
%srl = lshr <3 x i64> %arg0, %or
ret <3 x i64> %srl
}
define <4 x i64> @srl_v4_or32_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {
; CHECK-LABEL: srl_v4_or32_sgpr:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_lshr_b32 s4, s17, s24
; CHECK-NEXT: s_lshr_b32 s5, s19, s26
; CHECK-NEXT: s_lshr_b32 s6, s21, s28
; CHECK-NEXT: v_lshrrev_b32_e64 v6, v0, s23
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v2, s5
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v4, s6
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: v_mov_b32_e32 v7, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or <4 x i64> %shift_amt, splat (i64 32)
%srl = lshr <4 x i64> %arg0, %or
ret <4 x i64> %srl
}
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Test range from max/min
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FIXME: This case should be reduced too, but computeKnownBits() cannot
; determine the range. Match current results for now.
define i64 @srl_maxmin(i64 %arg0, i64 noundef %arg1) {
; CHECK-LABEL: srl_maxmin:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[2:3]
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v2, 32, v2, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[2:3]
; CHECK-NEXT: v_cndmask_b32_e32 v2, 63, v2, vcc
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%max = call i64 @llvm.umax.i64(i64 %arg1, i64 32)
%min = call i64 @llvm.umin.i64(i64 %max, i64 63)
%srl = lshr i64 %arg0, %min
ret i64 %srl
}
define <2 x i64> @srl_v2_maxmin(<2 x i64> %arg0, <2 x i64> noundef %arg1) {
; CHECK-LABEL: srl_v2_maxmin:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v4, 32, v4, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]
; CHECK-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%max = call <2 x i64> @llvm.umax.i64(<2 x i64> %arg1, <2 x i64> splat (i64 32))
%min = call <2 x i64> @llvm.umin.i64(<2 x i64> %max, <2 x i64> splat (i64 63))
%srl = lshr <2 x i64> %arg0, %min
ret <2 x i64> %srl
}
define <3 x i64> @srl_v3_maxmin(<3 x i64> %arg0, <3 x i64> noundef %arg1) {
; CHECK-LABEL: srl_v3_maxmin:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]
; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]
; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]
; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], v10, v[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], v8, v[2:3]
; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v6, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%max = call <3 x i64> @llvm.umax.i64(<3 x i64> %arg1, <3 x i64> splat (i64 32))
%min = call <3 x i64> @llvm.umin.i64(<3 x i64> %max, <3 x i64> splat (i64 63))
%srl = lshr <3 x i64> %arg0, %min
ret <3 x i64> %srl
}
define <4 x i64> @srl_v4_maxmin(<4 x i64> %arg0, <4 x i64> noundef %arg1) {
; CHECK-LABEL: srl_v4_maxmin:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]
; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]
; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[12:13]
; CHECK-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v12, 32, v12, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[14:15]
; CHECK-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v14, 32, v14, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[14:15]
; CHECK-NEXT: v_cndmask_b32_e32 v14, 63, v14, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[12:13]
; CHECK-NEXT: v_lshrrev_b64 v[6:7], v14, v[6:7]
; CHECK-NEXT: v_cndmask_b32_e32 v12, 63, v12, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], v12, v[4:5]
; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], v10, v[2:3]
; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v8, v[0:1]
; CHECK-NEXT: s_setpc_b64 s[30:31]
%max = call <4 x i64> @llvm.umax.i64(<4 x i64> %arg1, <4 x i64> splat (i64 32))
%min = call <4 x i64> @llvm.umin.i64(<4 x i64> %max, <4 x i64> splat (i64 63))
%srl = lshr <4 x i64> %arg0, %min
ret <4 x i64> %srl
}
|
