aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
blob: dce1a7fd5783b46e629edd4297e20d338285b4fe (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s

; Ensure NOOP shaders compile at OptNone.

; Confirm registers reserved in SIMachineFunctionInfo are those expected during
; lowering, even when e.g. spilling is required due to being at OptNone.

target triple = "amdgcn-amd-amdpal"

define amdgpu_vs void @noop_vs() {
; GCN-LABEL: noop_vs:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}

define amdgpu_ls void @noop_ls() {
; GCN-LABEL: noop_ls:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}

define amdgpu_hs void @noop_hs() {
; GCN-LABEL: noop_hs:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}

define amdgpu_es void @noop_es() {
; GCN-LABEL: noop_es:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}

define amdgpu_gs void @noop_gs() {
; GCN-LABEL: noop_gs:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}

define amdgpu_ps void @noop_ps() {
; GCN-LABEL: noop_ps:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}

define amdgpu_cs void @noop_cs() {
; GCN-LABEL: noop_cs:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_endpgm
entry:
  ret void
}