1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
|
; RUN: llc -mtriple=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; Test addressing modes when the scratch base is not a frame index.
; GCN-LABEL: {{^}}store_private_offset_i8:
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @store_private_offset_i8() #0 {
store volatile i8 5, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_i16:
; GCN: buffer_store_short v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @store_private_offset_i16() #0 {
store volatile i16 5, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_i32:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @store_private_offset_i32() #0 {
store volatile i32 5, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_v2i32:
; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @store_private_offset_v2i32() #0 {
store volatile <2 x i32> <i32 5, i32 10>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_v4i32:
; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @store_private_offset_v4i32() #0 {
store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}load_private_offset_i8:
; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @load_private_offset_i8() #0 {
%load = load volatile i8, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}sextload_private_offset_i8:
; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @sextload_private_offset_i8(ptr addrspace(1) %out) #0 {
%load = load volatile i8, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
%sextload = sext i8 %load to i32
store i32 %sextload, ptr addrspace(1) poison
ret void
}
; GCN-LABEL: {{^}}zextload_private_offset_i8:
; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @zextload_private_offset_i8(ptr addrspace(1) %out) #0 {
%load = load volatile i8, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
%zextload = zext i8 %load to i32
store i32 %zextload, ptr addrspace(1) poison
ret void
}
; GCN-LABEL: {{^}}load_private_offset_i16:
; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @load_private_offset_i16() #0 {
%load = load volatile i16, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}sextload_private_offset_i16:
; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @sextload_private_offset_i16(ptr addrspace(1) %out) #0 {
%load = load volatile i16, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
%sextload = sext i16 %load to i32
store i32 %sextload, ptr addrspace(1) poison
ret void
}
; GCN-LABEL: {{^}}zextload_private_offset_i16:
; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @zextload_private_offset_i16(ptr addrspace(1) %out) #0 {
%load = load volatile i16, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
%zextload = zext i16 %load to i32
store i32 %zextload, ptr addrspace(1) poison
ret void
}
; GCN-LABEL: {{^}}load_private_offset_i32:
; GCN: buffer_load_dword v{{[0-9]+}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @load_private_offset_i32() #0 {
%load = load volatile i32, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}load_private_offset_v2i32:
; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @load_private_offset_v2i32() #0 {
%load = load volatile <2 x i32>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}load_private_offset_v4i32:
; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:8
define amdgpu_kernel void @load_private_offset_v4i32() #0 {
%load = load volatile <4 x i32>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset:
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[12:15], 0 offset:4095
define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 {
store volatile i8 5, ptr addrspace(5) inttoptr (i32 4095 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus1:
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[12:15], 0 offen{{$}}
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 {
store volatile i8 5, ptr addrspace(5) inttoptr (i32 4096 to ptr addrspace(5))
ret void
}
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus2:
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[12:15], 0 offen offset:1{{$}}
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {
store volatile i8 5, ptr addrspace(5) inttoptr (i32 4097 to ptr addrspace(5))
ret void
}
; MUBUF used for stack access has bounds checking enabled before gfx9,
; so a possibly negative base index can't be used for the vgpr offset.
; GCN-LABEL: {{^}}store_private_unknown_bits_vaddr:
; SICIVI: {{buffer|flat}}_load_dword [[VADDR:v[0-9]+]],
; SICIVI: v_lshlrev_b32_e32 [[ADDR:v[0-9]+]], 2, [[VADDR]]
; SICIVI-NOT [[ADDR]]
; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR]]
; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
; GFX9: global_load_dword [[VADDR:v[0-9]+]],
; GFX9: v_lshlrev_b32_e32 [[ADDR:v[0-9]+]], 2, [[VADDR]]
; GFX9-NOT [[ADDR]]
; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen offset:32
define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
%vaddr = load volatile i32, ptr addrspace(1) poison
%vaddr.off = add i32 %vaddr, 8
%gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %vaddr.off
store volatile i32 9, ptr addrspace(5) %gep
ret void
}
attributes #0 = { nounwind }
|
