1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-SDAG %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-GISEL %s
declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float>, <2 x float>, <4 x float>, i32, i32, i32)
declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float>, <2 x float>, <16 x float>, i32, i32, i32)
define amdgpu_kernel void @test_mfma_f32_16x16x8xf32(ptr addrspace(1) %arg) #0 {
; GFX942-SDAG-LABEL: test_mfma_f32_16x16x8xf32:
; GFX942-SDAG: ; %bb.0: ; %bb
; GFX942-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, 2.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0x40400000
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4.0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, s0
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, s1
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, s2
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, s3
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[4:5], v[0:1], a[0:3] cbsz:1 abid:2 blgp:3
; GFX942-SDAG-NEXT: s_nop 6
; GFX942-SDAG-NEXT: global_store_dwordx4 v2, a[0:3], s[6:7]
; GFX942-SDAG-NEXT: s_endpgm
;
; GFX942-GISEL-LABEL: test_mfma_f32_16x16x8xf32:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX942-GISEL-NEXT: s_mov_b32 s4, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s5, 2.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
; GFX942-GISEL-NEXT: s_mov_b32 s4, 0x40400000
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s5, 4.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a0, s0
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a1, s1
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a2, s2
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a3, s3
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX942-GISEL-NEXT: s_nop 5
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7]
; GFX942-GISEL-NEXT: s_endpgm
bb:
%in.1 = load <4 x float>, ptr addrspace(1) %arg
%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <4 x float> %in.1, i32 1, i32 2, i32 3)
store <4 x float> %mai.1, ptr addrspace(1) %arg
ret void
}
define amdgpu_kernel void @test_mfma_f32_16x16x8xf32_vgprcd(ptr addrspace(1) %arg) #1 {
; GFX942-SDAG-LABEL: test_mfma_f32_16x16x8xf32_vgprcd:
; GFX942-SDAG: ; %bb.0: ; %bb
; GFX942-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, 2.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, 0x40400000
; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, 4.0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, 0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_mfma_f32_16x16x8_xf32 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
; GFX942-SDAG-NEXT: s_nop 6
; GFX942-SDAG-NEXT: global_store_dwordx4 v8, v[0:3], s[6:7]
; GFX942-SDAG-NEXT: s_endpgm
;
; GFX942-GISEL-LABEL: test_mfma_f32_16x16x8xf32_vgprcd:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX942-GISEL-NEXT: s_mov_b32 s4, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s5, 2.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: s_mov_b32 s4, 0x40400000
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s5, 4.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_16x16x8_xf32 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX942-GISEL-NEXT: s_nop 5
; GFX942-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX942-GISEL-NEXT: s_endpgm
bb:
%in.1 = load <4 x float>, ptr addrspace(1) %arg
%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <4 x float> %in.1, i32 1, i32 2, i32 3)
store <4 x float> %mai.1, ptr addrspace(1) %arg
ret void
}
define amdgpu_kernel void @test_mfma_f32_32x32x4xf32(ptr addrspace(1) %arg) #0 {
; GFX942-SDAG-LABEL: test_mfma_f32_32x32x4xf32:
; GFX942-SDAG: ; %bb.0: ; %bb
; GFX942-SDAG-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 1.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 2.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0x40400000
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4.0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, s0
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, s1
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, s2
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, s3
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a4, s4
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a5, s5
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a6, s6
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a7, s7
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a8, s8
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a9, s9
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a10, s10
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a11, s11
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a12, s12
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a13, s13
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a14, s14
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a15, s15
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[2:3], v[0:1], a[0:15] cbsz:1 abid:2 blgp:3
; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX942-SDAG-NEXT: s_nop 7
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
; GFX942-SDAG-NEXT: s_endpgm
;
; GFX942-GISEL-LABEL: test_mfma_f32_32x32x4xf32:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
; GFX942-GISEL-NEXT: s_mov_b32 s18, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s19, 2.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[18:19]
; GFX942-GISEL-NEXT: s_mov_b32 s18, 0x40400000
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s19, 4.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[18:19]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a0, s0
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a1, s1
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a2, s2
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a3, s3
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a4, s4
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a5, s5
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a6, s6
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a7, s7
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a8, s8
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a9, s9
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a10, s10
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a11, s11
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a12, s12
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a13, s13
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a14, s14
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a15, s15
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX942-GISEL-NEXT: s_nop 7
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
; GFX942-GISEL-NEXT: s_endpgm
bb:
%in.1 = load <16 x float>, ptr addrspace(1) %arg
%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <16 x float> %in.1, i32 1, i32 2, i32 3)
store <16 x float> %mai.1, ptr addrspace(1) %arg
ret void
}
define amdgpu_kernel void @test_mfma_f32_32x32x4xf32_vgprcd(ptr addrspace(1) %arg) #1 {
; GFX942-SDAG-LABEL: test_mfma_f32_32x32x4xf32_vgprcd:
; GFX942-SDAG: ; %bb.0: ; %bb
; GFX942-SDAG-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, 1.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, 2.0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, 0x40400000
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, 4.0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_mfma_f32_32x32x4_xf32 v[0:15], v[16:17], v[18:19], v[0:15] cbsz:1 abid:2 blgp:3
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, 0
; GFX942-SDAG-NEXT: s_nop 7
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
; GFX942-SDAG-NEXT: s_endpgm
;
; GFX942-GISEL-LABEL: test_mfma_f32_32x32x4xf32_vgprcd:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
; GFX942-GISEL-NEXT: s_mov_b32 s18, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s19, 2.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[18:19]
; GFX942-GISEL-NEXT: s_mov_b32 s18, 0x40400000
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s19, 4.0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_32x32x4_xf32 v[0:15], v[16:17], v[18:19], v[0:15] cbsz:1 abid:2 blgp:3
; GFX942-GISEL-NEXT: v_mov_b32_e32 v16, 0
; GFX942-GISEL-NEXT: s_nop 7
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
; GFX942-GISEL-NEXT: s_endpgm
bb:
%in.1 = load <16 x float>, ptr addrspace(1) %arg
%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <16 x float> %in.1, i32 1, i32 2, i32 3)
store <16 x float> %mai.1, ptr addrspace(1) %arg
ret void
}
attributes #0 = { "amdgpu-flat-work-group-size"="1,256" }
attributes #1 = { "amdgpu-flat-work-group-size"="512,512" "amdgpu-agpr-alloc"="0,0" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX942: {{.*}}
|
