1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=1 < %s | FileCheck -check-prefix=GISEL_W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=1 < %s | FileCheck -check-prefix=GISEL_W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W32 %s
declare i1 @llvm.amdgcn.inverse.ballot.i64(i64)
; Test ballot(0)
define amdgpu_cs void @constant_false_inverse_ballot(ptr addrspace(1) %out) {
; GISEL_W64-LABEL: constant_false_inverse_ballot:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: s_mov_b64 s[0:1], 0
; GISEL_W64-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: constant_false_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: s_mov_b64 s[0:1], 0
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s2
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: constant_false_inverse_ballot:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: s_mov_b32 s0, 0
; GISEL_W32-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: constant_false_inverse_ballot:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: s_mov_b32 s0, 0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; SDAG_W32-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
entry:
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 0)
%sel = select i1 %ballot, i64 1, i64 0
store i64 %sel, ptr addrspace(1) %out
ret void
}
; Test ballot(1)
define amdgpu_cs void @constant_true_inverse_ballot(ptr addrspace(1) %out) {
; GISEL_W64-LABEL: constant_true_inverse_ballot:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: s_mov_b64 s[0:1], -1
; GISEL_W64-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: constant_true_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: s_mov_b64 s[0:1], -1
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s2
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: constant_true_inverse_ballot:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: s_mov_b32 s0, -1
; GISEL_W32-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: constant_true_inverse_ballot:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: s_mov_b32 s0, 0
; SDAG_W32-NEXT: s_mov_b32 s1, -1
; SDAG_W32-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
entry:
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 u0xFFFFFFFFFFFFFFFF)
%sel = select i1 %ballot, i64 1, i64 0
store i64 %sel, ptr addrspace(1) %out
ret void
}
; Test ballot(u0x0040F8010000)
define amdgpu_cs void @constant_mask_inverse_ballot(ptr addrspace(1) %out) {
; GISEL_W64-LABEL: constant_mask_inverse_ballot:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: s_mov_b32 s0, 0xf8010000
; GISEL_W64-NEXT: s_mov_b32 s1, 64
; GISEL_W64-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: constant_mask_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: s_mov_b32 s0, 0xf8010000
; SDAG_W64-NEXT: s_mov_b32 s1, 64
; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s2
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: constant_mask_inverse_ballot:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: s_mov_b32 s0, 0xf8010000
; GISEL_W32-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: constant_mask_inverse_ballot:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: s_mov_b32 s0, 0
; SDAG_W32-NEXT: s_mov_b32 s1, 0xf8010000
; SDAG_W32-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
entry:
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 u0x0040F8010000)
%sel = select i1 %ballot, i64 1, i64 0
store i64 %sel, ptr addrspace(1) %out
ret void
}
; Test inverse ballot using a vgpr as input
define amdgpu_cs void @vgpr_inverse_ballot(i64 %input, ptr addrspace(1) %out) {
; GISEL_W64-LABEL: vgpr_inverse_ballot:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: v_readfirstlane_b32 s0, v0
; GISEL_W64-NEXT: v_readfirstlane_b32 s1, v1
; GISEL_W64-NEXT: v_mov_b32_e32 v5, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[2:3], v[4:5], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: vgpr_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: v_readfirstlane_b32 s0, v0
; SDAG_W64-NEXT: v_readfirstlane_b32 s1, v1
; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: v_mov_b32_e32 v1, s2
; SDAG_W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SDAG_W64-NEXT: global_store_b64 v[2:3], v[0:1], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: vgpr_inverse_ballot:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: v_readfirstlane_b32 s0, v0
; GISEL_W32-NEXT: v_mov_b32_e32 v1, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[2:3], v[0:1], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: vgpr_inverse_ballot:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: v_readfirstlane_b32 s1, v0
; SDAG_W32-NEXT: s_mov_b32 s0, 0
; SDAG_W32-NEXT: v_mov_b32_e32 v1, s0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; SDAG_W32-NEXT: global_store_b64 v[2:3], v[0:1], off
; SDAG_W32-NEXT: s_endpgm
entry:
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %input)
%sel = select i1 %ballot, i64 1, i64 0
store i64 %sel, ptr addrspace(1) %out
ret void
}
define amdgpu_cs void @sgpr_inverse_ballot(i64 inreg %input, ptr addrspace(1) %out) {
; GISEL_W64-LABEL: sgpr_inverse_ballot:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: sgpr_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: s_mov_b32 s0, 0
; SDAG_W64-NEXT: s_waitcnt_depctr 0xfffe
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: sgpr_inverse_ballot:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: sgpr_inverse_ballot:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; SDAG_W32-NEXT: s_mov_b32 s0, 0
; SDAG_W32-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
entry:
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %input)
%sel = select i1 %ballot, i64 1, i64 0
store i64 %sel, ptr addrspace(1) %out
ret void
}
; Test ballot after phi
define amdgpu_cs void @phi_uniform(i64 inreg %s0_1, i64 inreg %s2, ptr addrspace(1) %out) {
; GISEL_W64-LABEL: phi_uniform:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: s_cmp_lg_u64 s[2:3], 0
; GISEL_W64-NEXT: s_cbranch_scc1 .LBB5_2
; GISEL_W64-NEXT: ; %bb.1: ; %if
; GISEL_W64-NEXT: s_add_u32 s0, s0, 1
; GISEL_W64-NEXT: s_addc_u32 s1, s1, 0
; GISEL_W64-NEXT: .LBB5_2: ; %endif
; GISEL_W64-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: phi_uniform:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: s_cmp_lg_u64 s[2:3], 0
; SDAG_W64-NEXT: s_cbranch_scc1 .LBB5_2
; SDAG_W64-NEXT: ; %bb.1: ; %if
; SDAG_W64-NEXT: s_add_u32 s0, s0, 1
; SDAG_W64-NEXT: s_addc_u32 s1, s1, 0
; SDAG_W64-NEXT: .LBB5_2: ; %endif
; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s2
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: phi_uniform:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: s_cmp_lg_u64 s[2:3], 0
; GISEL_W32-NEXT: s_cbranch_scc1 .LBB5_2
; GISEL_W32-NEXT: ; %bb.1: ; %if
; GISEL_W32-NEXT: s_add_u32 s0, s0, 1
; GISEL_W32-NEXT: .LBB5_2: ; %endif
; GISEL_W32-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: phi_uniform:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: s_cmp_lg_u64 s[2:3], 0
; SDAG_W32-NEXT: s_cbranch_scc1 .LBB5_2
; SDAG_W32-NEXT: ; %bb.1: ; %if
; SDAG_W32-NEXT: s_add_u32 s0, s0, 1
; SDAG_W32-NEXT: .LBB5_2: ; %endif
; SDAG_W32-NEXT: s_mov_b32 s1, 0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; SDAG_W32-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
entry:
%cc = icmp ne i64 %s2, 0
br i1 %cc, label %endif, label %if
if:
%tmp = add i64 %s0_1, 1
br label %endif
endif:
%input = phi i64 [ %s0_1, %entry ], [ %tmp, %if ]
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %input)
%sel = select i1 %ballot, i64 1, i64 0
store i64 %sel, ptr addrspace(1) %out
ret void
}
; Test for branching
; The change in the branch affects all lanes, not just the branching ones.
; This test will be fixed once GISel correctly takes uniformity analysis into account.
define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr addrspace(1) %out) {
; GISEL_W64-LABEL: inverse_ballot_branch:
; GISEL_W64: ; %bb.0: ; %entry
; GISEL_W64-NEXT: s_xor_b64 s[4:5], s[2:3], -1
; GISEL_W64-NEXT: s_and_saveexec_b64 s[2:3], s[4:5]
; GISEL_W64-NEXT: ; %bb.1: ; %if
; GISEL_W64-NEXT: s_add_u32 s0, s0, 1
; GISEL_W64-NEXT: s_addc_u32 s1, s1, 0
; GISEL_W64-NEXT: ; %bb.2: ; %endif
; GISEL_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; GISEL_W64-NEXT: v_mov_b32_e32 v3, s1
; GISEL_W64-NEXT: v_mov_b32_e32 v2, s0
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: inverse_ballot_branch:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W64-NEXT: v_mov_b32_e32 v2, s0
; SDAG_W64-NEXT: s_xor_b64 s[4:5], s[2:3], -1
; SDAG_W64-NEXT: s_and_saveexec_b64 s[2:3], s[4:5]
; SDAG_W64-NEXT: ; %bb.1: ; %if
; SDAG_W64-NEXT: s_add_u32 s0, s0, 1
; SDAG_W64-NEXT: s_addc_u32 s1, s1, 0
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W64-NEXT: v_mov_b32_e32 v2, s0
; SDAG_W64-NEXT: ; %bb.2: ; %endif
; SDAG_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: inverse_ballot_branch:
; GISEL_W32: ; %bb.0: ; %entry
; GISEL_W32-NEXT: s_xor_b32 s3, s2, -1
; GISEL_W32-NEXT: s_and_saveexec_b32 s2, s3
; GISEL_W32-NEXT: ; %bb.1: ; %if
; GISEL_W32-NEXT: s_add_u32 s0, s0, 1
; GISEL_W32-NEXT: s_addc_u32 s1, s1, 0
; GISEL_W32-NEXT: ; %bb.2: ; %endif
; GISEL_W32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GISEL_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: inverse_ballot_branch:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; SDAG_W32-NEXT: s_xor_b32 s3, s2, -1
; SDAG_W32-NEXT: s_and_saveexec_b32 s2, s3
; SDAG_W32-NEXT: ; %bb.1: ; %if
; SDAG_W32-NEXT: s_add_u32 s0, s0, 1
; SDAG_W32-NEXT: s_addc_u32 s1, s1, 0
; SDAG_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; SDAG_W32-NEXT: ; %bb.2: ; %endif
; SDAG_W32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
entry:
%ballot = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %s2)
br i1 %ballot, label %endif, label %if
if:
%tmp = add i64 %s0_1, 1
br label %endif
endif:
%sel = phi i64 [ %s0_1, %entry ], [ %tmp, %if ]
store i64 %sel, ptr addrspace(1) %out
ret void
}
|
