1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GCN,GFX-942 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GCN,GFX-950 %s
; TODO: Add global-isel when it can support bf16
define amdgpu_ps float @v_test_cvt_bf16_f32_v(bfloat %v) {
; GCN-LABEL: v_test_cvt_bf16_f32_v:
; GCN: ; %bb.0:
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: ; return to shader part epilog
%cvt = fpext bfloat %v to float
ret float %cvt
}
define amdgpu_ps float @v_test_cvt_bf16_f32_s(bfloat inreg %v) {
; GCN-LABEL: v_test_cvt_bf16_f32_s:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshl_b32 s0, s0, 16
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ; return to shader part epilog
%cvt = fpext bfloat %v to float
ret float %cvt
}
define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_v(<2 x float> %src) {
; GFX-942-LABEL: v_test_cvt_v2f32_v2bf16_v:
; GFX-942: ; %bb.0:
; GFX-942-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v2, v2, v0, s0
; GFX-942-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX-942-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX-942-NEXT: v_add3_u32 v2, v2, v1, s0
; GFX-942-NEXT: v_or_b32_e32 v3, 0x400000, v1
; GFX-942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
; GFX-942-NEXT: s_nop 0
; GFX-942-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX-942-NEXT: v_perm_b32 v0, v1, v0, s0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: v_test_cvt_v2f32_v2bf16_v:
; GFX-950: ; %bb.0:
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
; GFX-950-NEXT: ; return to shader part epilog
%res = fptrunc <2 x float> %src to <2 x bfloat>
%cast = bitcast <2 x bfloat> %res to float
ret float %cast
}
define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
; GFX-942-LABEL: v_test_cvt_v2f32_v2bf16_s:
; GFX-942: ; %bb.0:
; GFX-942-NEXT: s_bfe_u32 s2, s1, 0x10010
; GFX-942-NEXT: s_add_i32 s2, s2, s1
; GFX-942-NEXT: s_or_b32 s4, s1, 0x400000
; GFX-942-NEXT: s_add_i32 s5, s2, 0x7fff
; GFX-942-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
; GFX-942-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX-942-NEXT: s_cselect_b32 s1, s4, s5
; GFX-942-NEXT: s_lshr_b32 s2, s1, 16
; GFX-942-NEXT: s_bfe_u32 s1, s0, 0x10010
; GFX-942-NEXT: s_add_i32 s1, s1, s0
; GFX-942-NEXT: s_or_b32 s3, s0, 0x400000
; GFX-942-NEXT: s_add_i32 s4, s1, 0x7fff
; GFX-942-NEXT: v_cmp_u_f32_e64 s[0:1], s0, s0
; GFX-942-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX-942-NEXT: s_cselect_b32 s0, s3, s4
; GFX-942-NEXT: s_lshr_b32 s0, s0, 16
; GFX-942-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX-942-NEXT: v_mov_b32_e32 v0, s0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: v_test_cvt_v2f32_v2bf16_s:
; GFX-950: ; %bb.0:
; GFX-950-NEXT: v_mov_b32_e32 v0, s1
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, s0, v0
; GFX-950-NEXT: ; return to shader part epilog
%res = fptrunc <2 x float> %src to <2 x bfloat>
%cast = bitcast <2 x bfloat> %res to float
ret float %cast
}
define amdgpu_ps float @v_test_cvt_f32_bf16_v(float %src) {
; GFX-942-LABEL: v_test_cvt_f32_bf16_v:
; GFX-942: ; %bb.0:
; GFX-942-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v1, v1, v0, s0
; GFX-942-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX-942-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: v_test_cvt_f32_bf16_v:
; GFX-950: ; %bb.0:
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX-950-NEXT: ; return to shader part epilog
%trunc = fptrunc float %src to bfloat
%ext = fpext bfloat %trunc to float
ret float %ext
}
define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX-942-LABEL: v_test_cvt_v2f64_v2bf16_v:
; GFX-942: ; %bb.0:
; GFX-942-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s4, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s4
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX-942-NEXT: v_cvt_f32_f64_e32 v5, v[2:3]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
; GFX-942-NEXT: v_and_b32_e32 v6, 1, v5
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[0:1]|
; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v6
; GFX-942-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v0, v5, v0
; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX-942-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX-942-NEXT: v_add3_u32 v1, v1, v0, s4
; GFX-942-NEXT: v_or_b32_e32 v0, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[2:3]
; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
; GFX-942-NEXT: s_nop 0
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX-942-NEXT: v_perm_b32 v0, v0, v4, s0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: v_test_cvt_v2f64_v2bf16_v:
; GFX-950: ; %bb.0:
; GFX-950-NEXT: v_cvt_f32_f64_e32 v6, v[2:3]
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v2, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v2, v6, v2
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cvt_f32_f64_e32 v5, v[0:1]
; GFX-950-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[2:3], v5
; GFX-950-NEXT: v_and_b32_e32 v6, 1, v5
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[2:3]
; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v6
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v5, v0
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, v4
; GFX-950-NEXT: ; return to shader part epilog
%res = fptrunc <2 x double> %src to <2 x bfloat>
%cast = bitcast <2 x bfloat> %res to float
ret float %cast
}
define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
; GFX-942-LABEL: fptrunc_f32_f32_to_v2bf16:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v2, v2, v0, s0
; GFX-942-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX-942-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX-942-NEXT: v_add3_u32 v2, v2, v1, s0
; GFX-942-NEXT: v_or_b32_e32 v3, 0x400000, v1
; GFX-942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
; GFX-942-NEXT: s_nop 0
; GFX-942-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX-942-NEXT: v_perm_b32 v0, v1, v0, s0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: fptrunc_f32_f32_to_v2bf16:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
; GFX-950-NEXT: ; return to shader part epilog
entry:
%a.cvt = fptrunc float %a to bfloat
%b.cvt = fptrunc float %b to bfloat
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
}
define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16_mods(float %a, float %b) {
; GFX-942-LABEL: fptrunc_f32_f32_to_v2bf16_mods:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX-942-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v3, v3, v2, s0
; GFX-942-NEXT: v_or_b32_e32 v2, 0x400000, v2
; GFX-942-NEXT: v_cmp_u_f32_e64 vcc, -v0, -v0
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX-942-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
; GFX-942-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX-942-NEXT: v_add3_u32 v3, v3, v2, s0
; GFX-942-NEXT: v_or_b32_e32 v2, 0x400000, v2
; GFX-942-NEXT: v_cmp_u_f32_e64 vcc, |v1|, |v1|
; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
; GFX-942-NEXT: s_nop 0
; GFX-942-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX-942-NEXT: v_perm_b32 v0, v1, v0, s0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: fptrunc_f32_f32_to_v2bf16_mods:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, -v0, |v1|
; GFX-950-NEXT: ; return to shader part epilog
entry:
%a.neg = fneg float %a
%a.cvt = fptrunc float %a.neg to bfloat
%b.abs = call float @llvm.fabs.f32(float %b)
%b.cvt = fptrunc float %b.abs to bfloat
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
}
define amdgpu_ps void @fptrunc_f32_to_bf16(float %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f32_to_bf16:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_mov_b32_e32 v3, v2
; GFX-942-NEXT: v_mov_b32_e32 v2, v1
; GFX-942-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v1, v1, v0, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f32_to_bf16:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_mov_b32_e32 v3, v2
; GFX-950-NEXT: v_mov_b32_e32 v2, v1
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
entry:
%a.cvt = fptrunc float %a to bfloat
store bfloat %a.cvt, ptr %out
ret void
}
define amdgpu_ps void @fptrunc_f32_to_bf16_abs(float %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f32_to_bf16_abs:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_mov_b32_e32 v3, v2
; GFX-942-NEXT: v_mov_b32_e32 v2, v1
; GFX-942-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
; GFX-942-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v4, v4, v1, s0
; GFX-942-NEXT: v_or_b32_e32 v1, 0x400000, v1
; GFX-942-NEXT: v_cmp_u_f32_e64 vcc, |v0|, |v0|
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f32_to_bf16_abs:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_mov_b32_e32 v3, v2
; GFX-950-NEXT: v_mov_b32_e32 v2, v1
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, |v0|, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
entry:
%a.abs = call float @llvm.fabs.f32(float %a)
%a.cvt = fptrunc float %a.abs to bfloat
store bfloat %a.cvt, ptr %out
ret void
}
define amdgpu_ps void @fptrunc_f32_to_bf16_neg(float %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f32_to_bf16_neg:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_mov_b32_e32 v3, v2
; GFX-942-NEXT: v_mov_b32_e32 v2, v1
; GFX-942-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
; GFX-942-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v4, v4, v1, s0
; GFX-942-NEXT: v_or_b32_e32 v1, 0x400000, v1
; GFX-942-NEXT: v_cmp_u_f32_e64 vcc, -v0, -v0
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f32_to_bf16_neg:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_mov_b32_e32 v3, v2
; GFX-950-NEXT: v_mov_b32_e32 v2, v1
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, -v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
entry:
%a.neg = fneg float %a
%a.cvt = fptrunc float %a.neg to bfloat
store bfloat %a.cvt, ptr %out
ret void
}
define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f64_to_bf16:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
entry:
%a.cvt = fptrunc double %a to bfloat
store bfloat %a.cvt, ptr %out
ret void
}
define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16_neg:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], -v[0:1], v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f64_to_bf16_neg:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], -v[0:1], v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
entry:
%a.neg = fneg double %a
%a.cvt = fptrunc double %a.neg to bfloat
store bfloat %a.cvt, ptr %out
ret void
}
define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16_abs:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[0:1]|
; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f64_to_bf16_abs:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
entry:
%a.abs = call double @llvm.fabs.f64(double %a)
%a.cvt = fptrunc double %a.abs to bfloat
store bfloat %a.cvt, ptr %out
ret void
}
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
|
