1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s
define amdgpu_ps <2 x float> @test_add_u64_vv(i64 %a, i64 %b) {
; GFX12-LABEL: test_add_u64_vv:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_vs(i64 %a, i64 inreg %b) {
; GFX12-LABEL: test_add_u64_vs:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, s0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_vs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_sv(i64 inreg %a, i64 %b) {
; GFX12-LABEL: test_add_u64_sv:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_sv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_ss(i64 inreg %a, i64 inreg %b) {
; GCN-LABEL: test_add_u64_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GCN-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_v_inline_lit(i64 %a) {
; GFX12-LABEL: test_add_u64_v_inline_lit:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 5
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_v_inline_lit:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 5, v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 5
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_v_small_imm(i64 %a) {
; GFX12-LABEL: test_add_u64_v_small_imm:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x1f4, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_v_small_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 0x1f4, v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 500
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_v_64bit_imm(i64 %a) {
; GFX12-LABEL: test_add_u64_v_64bit_imm:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x3b9ac9ff, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 1, v1, vcc_lo
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_v_64bit_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], lit64(0x13b9ac9ff), v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 5294967295
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
define amdgpu_ps <2 x float> @test_add_u64_s_small_imm(i64 inreg %a) {
; GCN-LABEL: test_add_u64_s_small_imm:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x1f4
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GCN-NEXT: ; return to shader part epilog
%add = add i64 %a, 500
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
|
