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//===--- Xtensa.h - Declare Xtensa target feature support -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares Xtensa TargetInfo objects.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H
#define LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H
#include "clang/Basic/TargetInfo.h"
#include "clang/Basic/TargetOptions.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/Compiler.h"
#include "llvm/TargetParser/Triple.h"
#include "clang/Basic/Builtins.h"
#include "clang/Basic/MacroBuilder.h"
#include "clang/Basic/TargetBuiltins.h"
namespace clang {
namespace targets {
class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
protected:
std::string CPU;
public:
XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple) {
// no big-endianess support yet
BigEndian = false;
NoAsmVariants = true;
LongLongAlign = 64;
SuitableAlign = 32;
DoubleAlign = LongDoubleAlign = 64;
SizeType = UnsignedInt;
PtrDiffType = SignedInt;
IntPtrType = SignedInt;
WCharType = SignedInt;
WIntType = UnsignedInt;
UseZeroLengthBitfieldAlignment = true;
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32");
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override {
return {};
}
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::XtensaABIBuiltinVaList;
}
std::string_view getClobbers() const override { return ""; }
ArrayRef<const char *> getGCCRegNames() const override {
static const char *const GCCRegNames[] = {
// General register name
"a0", "sp", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10",
"a11", "a12", "a13", "a14", "a15",
// Special register name
"sar"};
return llvm::ArrayRef(GCCRegNames);
}
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
return {};
}
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) {
default:
return false;
case 'a':
Info.setAllowsRegister();
return true;
}
return false;
}
int getEHDataRegisterNumber(unsigned RegNo) const override {
return (RegNo < 2) ? RegNo : -1;
}
bool isValidCPUName(StringRef Name) const override {
return llvm::StringSwitch<bool>(Name).Case("generic", true).Default(false);
}
bool setCPU(const std::string &Name) override {
CPU = Name;
return isValidCPUName(Name);
}
};
} // namespace targets
} // namespace clang
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H
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