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2025-02-19[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)Nikita Popov1-2/+2
The standard libcalls for half to float and float to half conversion are __extendhfsf2 and __truncsfhf2. However, LLVM currently uses __gnu_h2f_ieee and __gnu_f2h_ieee instead. As far as I can tell, these libcalls are an ARM-ism and only provided by libgcc on that platform. compiler-rt always provides both libcalls. Use the standard libcalls by default, and only use the __gnu libcalls on ARM.
2024-07-08[LegalizeDAG] Optimize CodeGen for `ISD::CTLZ_ZERO_UNDEF` (#83039)Manish Kausik H1-3/+3
Previously we had the same instructions being generated for `ISD::CTLZ` and `ISD::CTLZ_ZERO_UNDEF` which did not take advantage of the fact that zero is an invalid input for `ISD::CTLZ_ZERO_UNDEF`. This commit separates codegen for the two cases to allow for the optimization for the latter case. The details of the optimization are outlined in #82075 Fixes #82075 Co-authored-by: Manish Kausik H <hmamishkausik@gmail.com>
2024-04-15[GlobalISel] Fix fewerElementsVectorPhi to insert after G_PHIs (#87927)Dávid Ferenc Szabó1-3/+3
Currently the inserted mergelike instructions will be inserted at the location of the G_PHI. Seems like the behaviour was correct before, but the rework done in https://reviews.llvm.org/D114198 forgot to include the part which makes sure the instructions will be inserted after all the G_PHIs.
2024-03-07[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)Michael Maitland1-2/+2
Recommits llvm/llvm-project#80378 which was reverted in llvm/llvm-project#84330. The problem was that the change in llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir used 217 as an opcode instead of a regex.
2024-03-07Revert "[GISEL] Add IRTranslation for shufflevector on scalable vector ↵Michael Maitland1-2/+2
types" (#84330) Reverts llvm/llvm-project#80378 causing Buildbot failures that did not show up with check-llvm or CI.
2024-03-07[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)Michael Maitland1-2/+2
This patch is stacked on https://github.com/llvm/llvm-project/pull/80372, https://github.com/llvm/llvm-project/pull/80307, and https://github.com/llvm/llvm-project/pull/80306. ShuffleVector on scalable vector types gets IRTranslate'd to G_SPLAT_VECTOR since a ShuffleVector that has operates on scalable vectors is a splat vector where the value of the splat vector is the 0th element of the first operand, because the index mask operand is the zeroinitializer (undef and poison are treated as zeroinitializer here). This is analogous to what happens in SelectionDAG for ShuffleVector. `buildSplatVector` is renamed to`buildBuildVectorSplatVector`. I did not make this a separate patch because it would cause problems to revert that change without reverting this change too.
2024-01-26[GISel] Lower scalar G_SELECT in LegalizerHelper (#79342)Kai Nacke1-0/+41
The LegalizerHelper only has support to lower G_SELECT with vector operands. The approach is the same for scalar arguments, which this PR adds.
2024-01-03[GlobalISel][AArch64] Tail call libcalls. (#74929)David Green1-1/+3
This tries to allow libcalls to be tail called, using a similar method to DAG where the type is checked to make sure they match, and if so the backend, through lowerCall checks that the tailcall is valid for all arguments.
2023-01-25[unittests] Use GTEST_SKIP() instead of return when appropriatePaul Robinson1-93/+93
Basically NFC: A TEST/TEST_F/etc that bails out early (usually because setup failed or some other runtime condition wasn't met) generally should use GTEST_SKIP() to report its status correctly, unless it takes steps to report another status (e.g., FAIL()). I did see a handful of tests show up as SKIPPED after this change, which is not unexpected. The status seemed appropriate in all the new cases.
2023-01-13MachineIRBuilder: Rename buildMerge. NFCDiana Picus1-5/+5
`buildMerge` may build a G_MERGE_VALUES, G_BUILD_VECTOR or G_CONCAT_VECTORS. Rename it to `buildMergeLikeInstr`. This is a follow-up suggested in https://reviews.llvm.org/D140964 Differential Revision: https://reviews.llvm.org/D141372
2022-12-07[NFC] Use Register instead of unsigned for variables that receive a Register ↵Gregory Alfonso1-4/+4
object Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D139451
2022-08-02[GIsel] Add missing libcall for G_MUL to LegalizerHelperKai Nacke1-0/+58
The LegalizerHelper misses the code to lower G_MUL to a library call, which this change adds. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D130987
2022-04-12GlobalISel: Implement MoreElements for select of vector conditionsMatt Arsenault1-0/+47
2022-04-12GlobalISel: Handle widening umulo/smulo condition outputsMatt Arsenault1-0/+35
2021-12-23[GlobalISel] Rework more/fewer elements for vectorsPetar Avramovic1-90/+85
Artifact combiner is not able to access individual elements after using LCMTy style merge/unmerge, extract and insert to change vector number of elements (pad with undef or split to sub-vector instructions). Use unmerge to individual elements instead and then merge elements into requested types. Change argument lowering for vectors and moreElementsVector to use buildPadVectorWithUndefElements and buildDeleteTrailingVectorElements. FewerElementsVector had a few helpers that had different behavior, introduce new helper for most of the opcodes. FewerElementsVector helper is more flexible since it can create leftover instruction smaller then requested type (useful in case target wants to avoid pad with undef and use fewer registers). If target does not want leftover of different type it should call more elements first. Some helpers were performing more elements first to have split without leftover. Opcodes that used this helper use clampMaxNumElementsStrict (does more elements first) in LegalizerInfo to avoid test changes. Fixes failures caused by failing to combine artifacts created during more/fewer elements vector. Differential Revision: https://reviews.llvm.org/D114198
2021-10-04Delay outgoing register assignments to last.Amara Emerson1-2/+2
The delayed stack protector feature which is currently used for SDAG (and thus allows for more commonly generating tail calls) depends on being able to extract the tail call into a separate return block. To do this it also has to extract the vreg->physreg copies that set up the call's arguments, since if it doesn't then the call inst ends up using undefined physregs in it's new spliced block. SelectionDAG implementations can do this because they delay emitting register copies until *after* the stack arguments are set up. GISel however just processes and emits the arguments in IR order, so stack arguments always end up last, and thus this breaks the code that looks for any register arg copies that precede the call instruction. This patch adds a thunk argument to the assignValueToReg() and custom assignment hooks. For outgoing arguments, register assignments use this return param to return a thunk that does the actual generating of the copies. We collect these until all the outgoing stack assignments have been done and then execute them, so that the copies (and perhaps some artifacts like G_SEXTs) are placed after any stores. Differential Revision: https://reviews.llvm.org/D110610
2021-08-10[GlobalISel] Look through truncs and extends in narrowScalarShiftKonstantin Schwarz1-0/+43
If a G_SHL is fed by a G_CONSTANT, the lower and upper bits of the source can be shifted individually by the constant shift amount. However in case the shift amount came from a G_TRUNC(G_CONSTANT), the generic shift legalization code was used, producing intermediate shifts that are potentially illegal on some targets. This change teaches narrowScalarShift to look through G_TRUNCs and G_*EXTs. Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D89100
2021-08-06[GlobalISel] Improve widening of cttz/cttz_zero_undefJay Foad1-4/+4
Differential Revision: https://reviews.llvm.org/D107631
2021-08-06[GlobalISel] Improve legalization of narrow CTTZJay Foad1-1/+1
Differential Revision: https://reviews.llvm.org/D107457
2021-07-10[AArch64][GlobalISel] Implement moreElements legalization for G_SHUFFLE_VECTOR.Amara Emerson1-0/+47
Differential Revision: https://reviews.llvm.org/D103301
2021-07-08GlobalISel: Track original argument index in ArgInfoMatt Arsenault1-1/+1
SelectionDAG's equivalents in ISD::InputArg/OutputArg track the original argument index. Mips relies on this, and its currently reinventing its own parallel CallLowering infrastructure which tracks these indexes on the side. Add this to help move towards deleting the custom mips handling.
2021-06-30CodeGen: Print/parse LLTs in MachineMemOperandsMatt Arsenault1-1/+1
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-06-24[GlobalISel] NFC: Change LLT::vector to take ElementCount.Sander de Smalen1-33/+33
This also adds new interfaces for the fixed- and scalable case: * LLT::fixed_vector * LLT::scalable_vector The strategy for migrating to the new interfaces was as follows: * If the new LLT is a (modified) clone of another LLT, taking the same number of elements, then use LLT::vector(OtherTy.getElementCount()) or if the number of elements is halfed/doubled, it uses .divideCoefficientBy(2) or operator*. That is because there is no reason to specifically restrict the types to 'fixed_vector'. * If the algorithm works on the number of elements (as unsigned), then just use fixed_vector. This will need to be fixed up in the future when modifying the algorithm to also work for scalable vectors, and will need then need additional tests to confirm the behaviour works the same for scalable vectors. * If the test used the '/*Scalable=*/true` flag of LLT::vector, then this is replaced by LLT::scalable_vector. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D104451
2021-06-08GlobalISel: Avoid use of G_INSERT in insertPartsMatt Arsenault1-5/+5
G_INSERT legalization is incomplete and doesn't work very well. Instead try to use sequences of G_MERGE_VALUES/G_UNMERGE_VALUES padding with undef values (although this can get pretty large). For the case of load/store narrowing, this is still performing the load/stores in irregularly sized pieces. It might be cleaner to split this down into equal sized pieces, and rely on load/store merging to optimize it.
2021-06-01[globalisel][legalizer] Separate the deprecated LegalizerInfo from the ↵Daniel Sanders1-2/+2
current one It's still in use in a few places so we can't delete it yet but there's not many at this point. Differential Revision: https://reviews.llvm.org/D103352
2021-05-26Fix unit test after 324af79dbc6066Jessica Paquette1-62/+85
Needed to add in an extra parameter to calls to `libcall`.
2021-04-01Revert "[globalisel][unittests] Rename setUp() to avoid potential mix up ↵Daniel Sanders1-88/+88
with SetUp() from gtest" Forgot to apply commit message changes from phabricator This reverts commit 3a016e31ecef7eeb876b540c928a25a7c5d2e07a.
2021-04-01[globalisel][unittests] Rename setUp() to avoid potential mix up with ↵Daniel Sanders1-88/+88
SetUp() from gtest Also, make it structurally required so it can't be forgotten and re-introduce the bug that led to the rotten green tests. Differential Revision: https://reviews.llvm.org/D99692
2021-03-30[GlobalISel] Implement lowering for G_ROTR and G_ROTL.Amara Emerson1-0/+156
This is a straightforward port. Differential Revision: https://reviews.llvm.org/D99449
2021-03-10GlobalISel: Try to combine G_[SU]DIV and G_[SU]REMChristudasan Devadasan1-0/+62
It is good to have a combined `divrem` instruction when the `div` and `rem` are computed from identical input operands. Some targets can lower them through a single expansion that computes both division and remainder. It effectively reduces the number of instructions than individually expanding them. Reviewed By: arsenm, paquette Differential Revision: https://reviews.llvm.org/D96013
2021-03-02GlobalISel: Merge and cleanup more AMDGPU call lowering codeMatt Arsenault1-2/+2
This merges more AMDGPU ABI lowering code into the generic call lowering. Start cleaning up by factoring away more of the pack/unpack logic into the buildCopy{To|From}Parts functions. These could use more improvement, and the SelectionDAG versions are significantly more complex, and we'll eventually have to emulate all of those cases too. This is mostly NFC, but does result in some minor instruction reordering. It also removes some of the limitations with mismatched sizes the old code had. However, similarly to the merge on the input, this is forcing gfx6/gfx7 to use the gfx8+ ABI (which is what we actually want, but SelectionDAG is stuck using the weird emergent ABI). This also changes the load/store size for stack passed EVTs for AArch64, which makes it consistent with the DAG behavior.
2021-02-22[GlobalISel] Implement narrowScalar for SADDE/SSUBE/UADDE/USUBECassie Jones1-0/+156
Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D96673
2021-02-22[GlobalISel] Implement narrowScalar for SADDO/SSUBOCassie Jones1-0/+74
Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D96672
2021-02-22[GlobalISel] Implement narrowScalar for UADDO/USUBOCassie Jones1-0/+74
Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D96671
2021-02-12[RGT][GlobalIsel] Add missing setUp() calls to legalizer unittestsPaul Robinson1-21/+66
Some of these accidentally disabled tests failed as a result; updated tests per @qcolombet instructions. A small number needed additional updates because legalization has actually changed since they were written. Found by the Rotten Green Tests project. Differential Revision: https://reviews.llvm.org/D95257
2021-01-28[GlobalISel] Implement widenScalar for carry-in add/subCassie Jones1-0/+160
These are widened to a wider UADDE/USUBE, with the overflow value unused, and with the same synthesis of a new overflow value as for the O operations. Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D95326
2021-01-25Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo ↵Mitch Phillips1-6/+84
method"" This reverts commit 554b3211fefd09b56b64357b9edd66c78ae200b5. Differential Revision: https://reviews.llvm.org/D95035
2021-01-22Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method"Mitch Phillips1-84/+6
This reverts commit 2bb92bf451d7eb2c817f3e5403353e7c0c14d350. Dependent patch broke UBSan on Android: 3dedad475da45c05bc4f66cd14e9f44581edf0bc
2021-01-22[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo methodCassie Jones1-6/+84
The widenScalar implementation for signed and unsigned overflowing operations were very similar: both are checked by truncating the result and then re-sign/zero-extending it and checking that it matches the computed operation. Using a truncate + zero-extend for the unsigned case instead of manually producing the AND instruction like before leads to an extra copy instruction during legalization, but this should be harmless. Differential Revision: https://reviews.llvm.org/D95035
2020-09-29[GlobalISel] fix widenScalarUnmerge if widen type is not a multiple of ↵Dominik Montada1-0/+44
destination type Fix creation of illegal unmerge when widen was requested to a type which is not a multiple of the destination type. E.g. when trying to widen an s48 unmerge to s64 the existing code would create an illegal unmerge from s64 to s48. Instead, create further unmerges to a GCD type, then use this to remerge these intermediate results to the actual destinations. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D88422
2020-09-24GlobalISel: Use unmerge when copying wide vectors to result registersMatt Arsenault1-1/+4
Avoid using G_EXTRACT and move towards a more consistent vector legalization strategy.
2020-08-18GlobalISel: Implement fewerElementsVector for G_INSERT_VECTOR_ELTMatt Arsenault1-0/+81
Add unit tests since AMDGPU will only trigger this for gigantic vectors, and won't use the annoying odd sized breakdown case.
2020-08-03GlobalISel: Reimplement moreElementsVectorDstMatt Arsenault1-2/+1
Use pad with undef and unmerge with unused results. This is annoyingly similar to several other places in LegalizerHelper, but they're all slightly different.
2020-06-09GlobalISel: Set instr/debugloc before any legalizer actionMatt Arsenault1-0/+37
It was annoying enough that every custom lowering needed to set the insert point, but this was made worse since now these all needed to be updated to setInstrAndDebugLoc. Consolidate these so every legalization action has the right insert position by default. This should fix dropping debug info in every custom AMDGPU legalization.
2020-06-05GlobalISel: Add G_EXTRACT/G_INSERT offset to legalize infoMatt Arsenault1-1/+1
Immediate legalize fields were added for G_SEXT_INREG. Simiarly, these are likely not legal except for certain offsets.
2020-04-17[GlobalISel][AMDGPU] add legalization for G_FREEZEDominik Montada1-0/+211
Summary: Copy the legalization rules from SelectionDAG: -widenScalar using anyext -narrowScalar using intermediate merges -scalarize/fewerElements using unmerge -moreElements using G_IMPLICIT_DEF and insert Add G_FREEZE legalization actions to AMDGPULegalizerInfo. Use the same legalization actions as G_IMPLICIT_DEF. Depends on D77795. Reviewers: dsanders, arsenm, aqjune, aditya_nandakumar, t.p.northover, lebedev.ri, paquette, aemerson Reviewed By: arsenm Subscribers: kzhuravl, yaxunl, dstuttard, tpr, t-tye, jvesely, nhaehnle, kerbowa, wdng, rovka, hiraditya, volkan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78092
2020-04-08[GlobalISel] support narrow G_IMPLICIT_DEF for DstSize % NarrowSize != 0Dominik Montada1-0/+56
Summary: When narrowing G_IMPLICIT_DEF where the original size is not a multiple of the narrow size, emit a smaller G_IMPLICIT_DEF and use G_ANYEXT. To prevent a potential endless loop in the legalizer, the condition to combine G_ANYEXT(G_IMPLICIT_DEF) is changed from isInstUnsupported to !isInstLegal, since in this case the combine is only valid if consequent legalization of the newly combined G_IMPLICIT_DEF does not introduce G_ANYEXT due to narrowing. Although this legalization for G_IMPLICIT_DEF would also be valid for the general case, it actually caused a lot of code regressions when tried due to superfluous COPYs and combines not getting hit anymore. Reviewers: dsanders, aemerson, volkan, arsenm, aditya_nandakumar Reviewed By: arsenm Subscribers: jvesely, nhaehnle, kerbowa, wdng, rovka, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76598
2020-03-30[Alignment][NFC] Use Align version of getMachineMemOperandGuillaume Chatelet1-2/+2
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: jyknight, sdardis, nemanjai, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, jfb, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77059
2020-03-26[GlobalISel] add helper function to create arbitrary libcallsDominik Montada1-0/+26
Summary: The existing helper function can only create a libcall to functions available in RTLIB. Add a helper function that can create a libcall to a given function name using the provided calling convention. Reviewers: aditya_nandakumar, t.p.northover, rovka, arsenm, dsanders Reviewed By: arsenm Subscribers: wdng, hiraditya, volkan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76845
2020-03-24GlobalISel: Introduce bitcast legalize actionMatt Arsenault1-0/+157
For some operations, the type is unimportant and only the number of bits matters. For example I don't want to treat <4 x s8> as a legal type, but I also don't want to decompose loads of this into smaller pieces to get legal register types. On AMDGPU in SelectionDAG, we legalize a number of operations (most notably load and store) by coercing all types to vectors of i32. For GlobalISel, I'm trying very hard to avoid doing this for every type, but I don't think this strategy can be completely avoided. I'm trying to avoid bitcasts for any legitimately legal type we can operate on, since the intervening bitcasts have proven to be a hassle. For loads, I think I can get away without ever casting the result type, and handling any arbitrary bitwidth during selection (I will eventually want new tablegen support to help with this, rather than having to add every possible type as legal). The unmerge required to do anything with the value should expand to the expected shifts. This is trickier for stores, since it would now require handling a wide array of truncates during selection which I don't want. Future potentially interesting case are for vector indexing, where sub-dword type should be indexed in s32 pieces.