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2025-06-09Remove GlobalObject::getAlign/setAlignment (#143188)Eli Friedman1-3/+4
Currently, GlobalObject has an "alignment" property... but it's basically nonsense: alignment doesn't mean the same thing for variables and functions, and it's completely meaningless for ifuncs. This "removes" (actually marking protected) the methods from GlobalObject, adds the relevant methods to Function and GlobalVariable, and adjusts the code appropriately. This should make future alignment-related cleanups easier.
2025-05-26[PowerPC] Remove unused includes (NFC) (#141449)Kazu Hirata1-1/+0
These are identified by misc-include-cleaner. I've filtered out those that break builds. Also, I'm staying away from llvm-config.h, config.h, and Compiler.h, which likely cause platform- or compiler-specific build failures.
2025-04-14[NFC][LLVM][PowerPC] Cleanup pass initialization for PowerPC (#134422)Rahul Joshi1-3/+1
- Remove calls to pass initialization from pass constructors. - https://github.com/llvm/llvm-project/issues/111767
2025-02-20Revert "[CodeGen] Remove static member function Register::isVirtualRegister. ↵Christopher Di Bella1-1/+1
NFC (#127968)" This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
2025-02-20[CodeGen] Remove static member function Register::isVirtualRegister. NFC ↵Craig Topper1-1/+1
(#127968) Use nonstatic member instead. This requires explicit conversions, but many will go away as we continue converting unsigned to Register. In a few places where it was simple, I changed unsigned to Register.
2025-01-30[CodeGen] Use non-static Register::virtRegIndex() instead of static ↵Craig Topper1-4/+3
Register::virtReg2Index. NFC (#125031) These are the the ones where we already had a Register object being used. Some places are still using unsigned which I did not convert.
2024-11-14[PowerPC] Remove unused includes (NFC) (#116163)Kazu Hirata1-1/+0
Identified with misc-include-cleaner.
2024-11-12[llvm] Remove redundant control flow statements (NFC) (#115831)Kazu Hirata1-1/+0
Identified with readability-redundant-control-flow.
2024-10-31Promote 32bit pseudo instr that infer extsw removal to 64bit in ↵zhijian lin1-1/+10
PPCMIPeephole (#85451) Fixes: https://github.com/llvm/llvm-project/issues/71030 Bug only happens in 64bit involving spills. Since we don't know when the spill will happen, all instructions in the chain used to deduce sign extension for eliminating 'extsw' will need to be promoted to 64-bit pseudo instructions. The following instruction will promoted in PPCMIPeepholes: EXTSH, LHA, ISEL to EXTSH8, LHA8, ISEL8
2024-07-16[PowerPC] Ensure MI peephole knows about instr modified by combineRLWINM() ↵Lei Huang1-0/+4
(#97134) Ensure registers used in instructions modified by `combineRLWINM()` are added to list of `RegsToUpdate`.
2024-07-12[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)paperchalice1-4/+4
- Add `MachineBlockFrequencyAnalysis`. - Add `MachineBlockFrequencyPrinterPass`. - Use `MachineBlockFrequencyInfoWrapperPass` in legacy pass manager. - `LazyMachineBlockFrequencyInfo::print` is empty, drop it due to new pass manager migration.
2024-07-09[CodeGen][NewPM] Port `LiveVariables` to new pass manager (#97880)paperchalice1-4/+4
- Port `LiveVariables` to new pass manager. - Convert to `LiveVariablesWrapperPass` in legacy pass manager.
2024-06-20[PowerPC] Make verifier happy after peephole on MMA COPYs (#94321)Kai Luo1-0/+3
2024-06-12[CodeGen][NewPM] Split `MachinePostDominators` into a concrete analysis ↵paperchalice1-4/+4
result (#95113) `MachinePostDominators` version of #94571.
2024-06-11[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis ↵paperchalice1-4/+4
result (#94571) Prepare for new pass manager version of `MachineDominatorTreeAnalysis`. We may need a machine dominator tree version of `DomTreeUpdater` to handle `SplitCriticalEdge` in some CodeGen passes.
2024-04-28[PPC]add DEBUG_COUNTER for PPCMIPeephole passChen Zheng1-0/+14
2023-10-06[PowerPC] Fix missing kill flag update for XVCVDPSP transformations (#67997)Lei1-1/+2
Add transformed register to kill flag work list for XVCVDPSP tranformations. Ref: reviews.llvm.org/D133103
2023-10-05Use BlockFrequency type in more places (NFC) (#68266)Matthias Braun1-2/+2
The `BlockFrequency` class abstracts `uint64_t` frequency values. Use it more consistently in various APIs and disable implicit conversion to make usage more consistent and explicit. - Use `BlockFrequency Freq` parameter for `setBlockFreq`, `getProfileCountFromFreq` and `setBlockFreqAndScale` functions. - Return `BlockFrequency` in `getEntryFreq()` functions. - While on it change some `const BlockFrequency& Freq` parameters to plain `BlockFreqency Freq`. - Mark `BlockFrequency(uint64_t)` constructor as explicit. - Add missing `BlockFrequency::operator!=`. - Remove `uint64_t BlockFreqency::getMaxFrequency()`. - Add `BlockFrequency BlockFrequency::max()` function.
2023-09-26[PowerPC] A fix for D159073. Do not optimize when register classes are ↵esmeyi1-0/+8
different in src and dst. For example: ``` %298:g8rc = RLDICL %297:g8rc, 0, 48 %299:gprc = COPY killed %298.sub_32:g8rc dead %498:gprc = ANDI_rec killed %299:gprc, 1, implicit-def dead $cr0, implicit-def $cr0gt ```
2023-09-26Reland https://reviews.llvm.org/D159073.esmeyi1-0/+54
The patch failed in test-suite due to a liveness error after rebasing on https://reviews.llvm.org/D133103, and now it's fixed. ``` [PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel. Summary: rldicl/rldicr can be eliminated if it's used to clear thehigh-order or low-order n bits and all bits cleared will be ANDed with 0 byandi/andis. Or they can be folded to `andi 0` if all bits to AND are alreadyzero in the input. Reviewed By: qiucf, shchenz Differential Revision: https://reviews.llvm.org/D159073 ```
2023-09-25Revert "[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel."esmeyi1-54/+0
This reverts commit 2de74e1bd4d540063d7495fa6254781abd41e179. A test-suite failure occurs due to this commit, will fix soon.
2023-09-25[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.esmeyi1-0/+54
Summary: rldicl/rldicr can be eliminated if it's used to clear the high-order or low-order n bits and all bits cleared will be ANDed with 0 by andi/andis. Or they can be folded to `andi 0` if all bits to AND are already zero in the input. Reviewed By: qiucf, shchenz Differential Revision: https://reviews.llvm.org/D159073
2023-09-22[PowerPC] Improve kill flag computation and add verification after MI peepholeNemanja Ivanovic1-29/+179
The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations require re-computation of kill flags but don't do a good job of re-computing them. This causes us to have very common failures when the compiler is built with expensive checks. Over time, we added and augmented a function that is supposed to go and fix up kill flags after each transformation but we keep missing cases. This patch does the following: - Removes the function to re-compute kill flags - Adds LiveVariables to compute and maintain kill flags while transforming code - Adds re-computation of kill flags for the post-RA peepholes for each block that contains a transformed instruction Reviewed By: stefanp Differential Revision: https://reviews.llvm.org/D133103
2023-07-12[PowerPC] remove XXSWAPD after vector splat immediateTing Wang1-3/+5
Redundant XXSWAPD has been observed on little-endian in D138883 test case. Remove those associated with vector splat instructions. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D139193
2023-05-08[PowerPC] Look through OR, AND, XOR instructions when checking a clear.Stefan Pintilie1-0/+14
This patch adds the additional step of looking through AND, OR, XOR instructions when we check the number of leading zeros. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D149223
2023-04-24[PPCMIPeephole] Fix incorrect compare eliminationFangrui Song1-1/+4
D38236 moves a redundant compare instruction from the loop body to the preheader. It has a bug: when `MBB1 == &MBB2`, there may be only one compare instruction in the loop. The code will lift the compare instruction to the preheader, failing to account for the change of the compare result in a tail call, leading to a miscompile. Suppress the compare elimination to fix https://github.com/llvm/llvm-project/issues/62294 Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D149030
2023-02-16[PowerPC] remove XXSWAPD after load from CP which is a splat valueTing Wang1-0/+14
If the value from constant-pool is a splat value of vector type, do not need swap after load from constant-pool. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D139491
2023-02-02[PowerPC] add a peephole to remove redundant swap instructions after vector ↵Ting Wang1-0/+12
splats on P8 Vector store on P8 little endian will have swap instruction added before the store in PPCISelLowring. If the vector is generated by splat, the swap instruction can be eliminated. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D139691
2023-01-31[PowerPC] Do not convert lwz to lwa if the offset is not a multiple of 4Nemanja Ivanovic1-1/+2
The transform that converts this checks the alignment of the global object being accessed. However, there was no check for the offset within the global object which caused the compiler to produce a DS relocation for an unaligned address.
2023-01-28[Target] Use llvm::count{l,r}_{zero,one} (NFC)Kazu Hirata1-1/+1
2023-01-13[CodeGen][Target] Remove uses of ↵Craig Topper1-24/+20
Register::isPhysicalRegister/isVirtualRegister. NFC Use isPhysical/isVirtual methods.
2022-12-13[rereland][Alignment][NFC] Remove access to deprecated ↵Guillaume Chatelet1-1/+1
GlobalObject::getAlignment from llvm Differential Revision: https://reviews.llvm.org/D139836
2022-12-12Revert "[reland][Alignment][NFC] Remove access to deprecated ↵Guillaume Chatelet1-1/+1
GlobalObject::getAlignment from llvm" This reverts commit 3bbfaee23d41c099547c652f87b252ab6e1f6c46.
2022-12-12[reland][Alignment][NFC] Remove access to deprecated ↵Guillaume Chatelet1-1/+1
GlobalObject::getAlignment from llvm Differential Revision: https://reviews.llvm.org/D139836
2022-12-12Revert D139836 "[Alignment][NFC] Remove deprecated GlobalObject::getAlignment"Guillaume Chatelet1-1/+1
This breaks lldb. This reverts commit f3f15ca27fbb433ad5a65b1a1e0a071d2e9af505.
2022-12-12[Alignment][NFC] Remove deprecated GlobalObject::getAlignmentGuillaume Chatelet1-1/+1
Differential Revision: https://reviews.llvm.org/D139836
2022-12-01[NFC][PowerPC] More descriptive debug messages for rr to ri conversionNemanja Ivanovic1-0/+6
2022-08-23[NFC][PowerPC] Clean up a couple of lambdas from the PPCMIPeephole.Stefan Pintilie1-36/+34
There were two sections of code that had a lot of lambdas and in the patch D40554 it was suggested that we clean them up as a follow-up NFC patch. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D132394
2022-08-19[PowerPC] Fix bugs in sign-/zero-extension eliminationStefan Pintilie1-9/+36
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass. - Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer). - Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D40554
2022-08-07[llvm] Fix comment typos (NFC)Kazu Hirata1-1/+1
2022-03-16[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated ↵Shengchen Kan1-1/+1
comments
2022-03-16Cleanup codegen includesserge-sans-paille1-0/+1
This is a (fixed) recommit of https://reviews.llvm.org/D121169 after: 1061034926 before: 1063332844 Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-1/+0
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
2022-03-10Cleanup codegen includesserge-sans-paille1-0/+1
after: 1061034926 before: 1063332844 Differential Revision: https://reviews.llvm.org/D121169
2022-01-23[Target] Use range-based for loops (NFC)Kazu Hirata1-4/+4
2022-01-19[NFC] Use Register instead of unsignedJim Lin1-12/+12
2022-01-07[llvm] Use true/false instead of 1/0 (NFC)Kazu Hirata1-2/+1
Identified with modernize-use-bool-literals.
2022-01-02Remove redundant void arguments (NFC)Kazu Hirata1-4/+4
Identified by modernize-redundant-void-arg.
2021-11-19[PowerPC] Add a flag for conditional trap optimizationVictor Huang1-2/+9
This patch adds a flag to enable/disable conditional trap optimization. Optimization disabled by default. Peer reviewed by: nemanjai
2021-11-18[PowerPC] Remove the redundant terminator instruction when optimizing ↵Victor Huang1-3/+3
conditional trap This patch is a follow up patch for ae27ca9a678301969c35f2e27c76f14c9d2bb396 to the remove redundant terminator when optimizing conditional trap. Peer reviewed by: nemanjai
generated by cgit v1.1 at 2025-08-03 01:54:31 +0000