aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AArch64/AArch64InstrInfo.td
AgeCommit message (Expand)AuthorFilesLines
2024-02-25Revert "[AArch64] Intrinsics aarch64_{get,set}_fpsr (#81867)"revert-81867-aa64.intrSerge Pavlov1-12/+1
2024-02-24[AArch64] Intrinsics aarch64_{get,set}_fpsr (#81867)Serge Pavlov1-1/+12
2024-02-21[AArch64] Fix syntax of gcsstr and gcssttr instructions (#82385)John Brawn1-1/+1
2024-02-14[AArch64] Materialize constants via fneg. (#80641)David Green1-6/+10
2024-02-08[AArch64] Indirect tail-calls cannot use x16 with pac-ret+pc (#81020)ostannard1-9/+38
2024-02-06[AArch64] Set predicates for FP/SIMD InstAliases (#79033)ostannard1-1/+23
2024-02-02[AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)chuongg31-0/+12
2024-02-01[AArch64][PAC] Expand blend(reg, imm) operation in aarch64-pauth pass (#74729)Anatoly Trosinenko1-3/+4
2024-01-31[AArch64] Use DAG->isAddLike in add_and_or_is_add (#79563)David Green1-1/+1
2024-01-31[AArch64] Use add_and_or_is_add for CSINC (#79552)David Green1-3/+3
2024-01-22Arm64EC entry/exit thunks, consolidated. (#79067)Eli Friedman1-0/+11
2024-01-22[GlobalISel][AArch64] Combine Vector Reduction Add Long (#76241)chuongg31-0/+23
2024-01-20[AArch64] Rename LDAPR<x>pre to LDAPR<x>post (#77340)nsurbay1-14/+14
2024-01-16[AArch64] Fix a typo in predicate expression (NFC) (#78162)Momchil Velikov1-1/+1
2024-01-15[AArch64][GlobalISel] Combine vecreduce(ext) to {U/S}ADDLV (#75832)chuongg31-8/+17
2024-01-12[AArch64] Disable FP loads/stores when fp-armv8 not enabled (#77817)ostannard1-1/+41
2023-12-22[AArch64] paci<k>171615 auti<k>171615 assembly (#76227)Tomas Matheson1-0/+5
2023-12-21Re-land "[AArch64] Add FEAT_PAuthLR assembler support" (#75947)Tomas Matheson1-0/+39
2023-12-21Revert "[AArch64] Add FEAT_PAuthLR assembler support"Tomas Matheson1-39/+0
2023-12-21[AArch64] Add FEAT_PAuthLR assembler supportOliver Stannard1-0/+39
2023-12-21[AArch64][GlobalISel] Lower scalarizing G_UNMERGE_VALUES to G_EXTRACT_VECTOR_ELTDavid Green1-6/+6
2023-12-20Reland: [AArch64] Assembly support for the Checked Pointer Arithmetic Extensi...Lucas Duarte Prates1-0/+19
2023-12-02[AArch64] Stack probing for dynamic allocas in SelectionDAG (#66525)Momchil Velikov1-0/+14
2023-12-02Revert HWASAN failure (#74163)Kirill Stoimenov1-19/+0
2023-11-30[AArch64] Stack probing for function prologues (#66524)Momchil Velikov1-2/+23
2023-11-30[AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)Lucas Duarte Prates1-0/+19
2023-11-22Revert "Revert "[SVE2.1][Clang][LLVM]Add BFloat16 builtin in Clang an… (#73...CarolineConcatto1-1/+1
2023-11-20[AArch64] Add missing bf16 store pattern (#72844)dewen1-0/+5
2023-11-20[AArch64][SME] Add support for sme-fa64 (#70809)Matthew Devereau1-0/+2
2023-11-13[AArch64][GlobalISel] TableGen Selection for G_VECREDUCE_ADD (#70785)chuongg31-0/+16
2023-11-09[AArch64][GlobalISel] Legalize G_VECREDUCE_{MIN/MAX} (#69461)chuongg31-0/+37
2023-11-03[llvm][AArch64][Assembly]: Add SME_F8F16 and SME_F8F32 Ass/Disass. (#70640)Hassnaa Hamdi1-0/+4
2023-11-02[llvm][AArch64][Assembly]: Add LUT assembly/disassembly. (#70802)Hassnaa Hamdi1-0/+11
2023-11-01[llvm][AArch64][Assembly]: Add FDOT2/FDOT4 assembly and disassembly. (#70237)hassnaaHamdi1-0/+24
2023-11-01[llvm][AArch64][Assembly]: Add FP8FMA assembly and disassembly. (#70134)hassnaaHamdi1-0/+22
2023-10-31[AArch64] Add intrinsic to count trailing zero elementsKerry McLaughlin1-0/+3
2023-10-30[AArch64] Add support for v8.4a `ldapur`/`stlur`Antonio Frighetto1-1/+1
2023-10-29[AArch64] Add additional concat trunc -> UZP1 patternsDavid Green1-0/+11
2023-10-27[LLVM][AArch64][Assembly]: Add FAMINMAX assembly/disasse… (#70115)hassnaaHamdi1-0/+8
2023-10-26[llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (#6...hassnaaHamdi1-0/+15
2023-10-20[llvm][AArch64][Assembly] Implement support to read/write FPMR (#69618)hassnaaHamdi1-0/+2
2023-10-13[AArch64][NFC] Refactor NEON, SVE and SME classes and multiclasses fo… (#68...CarolineConcatto1-1/+1
2023-10-04[AArch64][PAC] Specify Defs and Uses of PAUTH_(PROLOGUE|EPILOGUE)Anatoly Trosinenko1-0/+2
2023-09-29[AArch64] Don't expand RSHRN intrinsics to add+srl+trunc.David Green1-2/+28
2023-09-22[AArch64] Move PAuth codegen down the machine pipelineAnatoly Trosinenko1-0/+9
2023-09-19[AArch64] Remove copy instruction between uaddlv with v4i16/v8i16 and dup (#6...JinGu Kang1-0/+12
2023-09-15[AArch64][GlobalISel] Select llvm.aarch64.neon.st* intrinsics (#65491)Vladislav Dzhidzhoev1-3/+3
2023-09-11Add missing vrnd intrinsicsMax Iyengar1-0/+10
2023-09-05[AArch64] Remove copy instruction between uaddlv and dupJingu Kang1-0/+7
2023-08-23[AArch64][GlobalISel] Select USHLL2 InstructionTuan Chuong Goh1-9/+9
generated by cgit v1.1 at 2024-09-07 05:53:11 +0000