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2025-07-19[NFC][RA] Refactor RABasic into a Separate Header (#149555)Kyungwoo Lee1-91/+6
This change refactors the RABasic type by moving it from RegAllocBasic.cpp to a new header file, RegAllocBasic.h. This separation of header and implementation aligns with the structure used by other register allocators, such as RegAllocGreedy. The refactoring is intended to facilitate future use of RABasic in other contexts.
2025-05-22[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties ↵users/pcc/spr/main.elf-add-branch-to-branch-optimizationRahul Joshi1-4/+2
(#140002) Add per-property has<Prop>/set<Prop>/reset<Prop> functions to MachineFunctionProperties.
2025-02-26RegAlloc: Use new approach to handling failed allocations (#128469)Matt Arsenault1-1/+0
This fixes an assert after allocation failure. Rather than collecting failed virtual registers and hacking on the uses after the fact, directly hack on the uses and rewrite the registers to the dummy assignment immediately. Previously we were bypassing LiveRegMatrix and directly assigning in the VirtRegMap. This resulted in inconsistencies where illegal overlapping assignments were missing. Rather than try to hack in some system to manage these in LiveRegMatrix (i.e. hacking around cases with invalid iterators), avoid this by directly using the physreg. This should also allow removal of special casing in virtregrewriter for failed allocations.
2025-02-26Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" ↵Matt Arsenault1-0/+1
(#128400) Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" This reverts commit 0c50054820799578be8f62b6fd2cc3fbc751c01e. Reapply with more fixes to avoid expensive_checks failures. Make sure to call splitSeparateComponents after shrinkToUses, and update the VirtRegMap with the split registers. Also set undef on all physical register aliases to the assigned register. Move physreg handling. Not sure if necessary Remove intervals from regunits. Not sure if necessary
2025-02-22Revert "RegAlloc: Fix verifier error after failed allocation (#119690)"Matt Arsenault1-1/+0
This reverts commit 34167f99668ce4d4d6a1fb88453a8d5b56d16ed5. Different set of verifier errors appears after other regalloc failure tests with EXPENSIVE_CHECKS.
2025-02-21RegAlloc: Fix verifier error after failed allocation (#119690)Matt Arsenault1-0/+1
In some cases after reporting an allocation failure, this would fail the verifier. It picks the first allocatable register and assigns it, but didn't update the liveness appropriately. When VirtRegRewriter relied on the liveness to set kill flags, it would incorrectly add kill flags if there was another overlapping kill of the virtual register. We can't properly assign the register to an overlapping range, so break the liveness of the failing register (and any other interfering registers) instead. Give the virtual register dummy liveness by effectively deleting all the uses by setting them to undef. The edge case not tested here which I'm worried about is if the read of the register is a def of a subregister. I've been unable to come up with a test where this occurs. https://reviews.llvm.org/D122616
2025-02-12Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)Akshat Oke1-1/+1
`RegisterClassInfo` was supposed to be kept alive between pass runs, which wasn't being done leading to recomputations increasing the compile time. Now the Impl class is a member of the legacy and new passes so that it is not reconstructed on every pass run. --------- Co-authored-by: Christudasan Devadasan <christudasan.devadasan@amd.com>
2025-02-08Revert "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126268)Akshat Oke1-1/+1
This reverts commit 5aa4979c47255770cac7b557f3e4a980d0131d69 while I investigate what's causing the compile-time regression.
2025-02-05CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)Christudasan Devadasan1-1/+1
2025-02-03[CodeGen][NewPM] Port RegisterCoalescer to NPM (#124698)Akshat Oke1-1/+1
2025-01-13Reapply "Spiller: Detach legacy pass and supply analyses instead (#119181)" ↵Akshat Oke1-5/+11
(#122665) Makes Inline Spiller amenable to the new PM. This reapplies commit a531800344dc54e9c197a13b22e013f919f3f5e1 reverted because of two unused private members reported on sanitizer bots.
2025-01-10Revert "Spiller: Detach legacy pass and supply analyses instead (#119… ↵Akshat Oke1-11/+5
(#122426) …181)" This reverts commit a531800344dc54e9c197a13b22e013f919f3f5e1.
2025-01-10Spiller: Detach legacy pass and supply analyses instead (#119181)Akshat Oke1-5/+11
Makes Inline Spiller amenable to the new PM.
2024-12-06[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)Akshat Oke1-3/+3
2024-12-04[CodeGen][NewPM] Port LiveDebugVariables to NPM (#115468)Akshat Oke1-3/+3
The existing analysis was already a pimpl wrapper. I have extracted legacy pass logic to a LDVImpl wrapper named `LiveDebugVariables` which is the analysis::Result now. This controls whether to activate the LDV (depending on `-live-debug-variables` and DIsubprogram) itself. The legacy and new analysis only construct the LiveDebugVariables. VirtRegRewriter will test this.
2024-10-22[NewPM][CodeGen] Port LiveRegMatrix to NPM (#109938)Akshat Oke1-4/+4
2024-10-22[NewPM][CodeGen] Port VirtRegMap to NPM (#109936)Akshat Oke1-4/+4
2024-10-21[regalloc][basic] Change spill weight for optsize funcs (#112960)Ellis Hoag1-1/+5
Change the spill weight calculations for `optsize` functions to remove the block frequency multiplier. For those functions, we do not want to consider the runtime cost of spilling, only the codesize cost. I built a large app with the basic and greedy (default) register allocator enabled. | Regalloc Type | Uncompressed Size Delta | Compressed Size Delta | | - | - | - | | Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) | | Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) | Since I only saw a size win with the basic register allocator, I decided to only change the behavior for that type.
2024-07-22[CodeGen] change prototype of regalloc filter function (#93525)Christudasan Devadasan1-6/+4
[CodeGen] Change the prototype of regalloc filter function Change the prototype of the filter function so that we can filter not just by RegClass. We need to implement more complicated filter based upon some other info associated with each register. Patch provided by: Gang Chen (gangc@amd.com)
2024-07-12[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)paperchalice1-5/+5
- Add `MachineBlockFrequencyAnalysis`. - Add `MachineBlockFrequencyPrinterPass`. - Use `MachineBlockFrequencyInfoWrapperPass` in legacy pass manager. - `LazyMachineBlockFrequencyInfo::print` is empty, drop it due to new pass manager migration.
2024-07-10[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)paperchalice1-4/+4
- Add `LiveIntervalsAnalysis`. - Add `LiveIntervalsPrinterPass`. - Use `LiveIntervalsWrapperPass` in legacy pass manager. - Use `std::unique_ptr` instead of raw pointer for `LICalc`, so destructor and default move constructor can handle it correctly. This would be the last analysis required by `PHIElimination`.
2024-07-09[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)paperchalice1-2/+2
- Add `SlotIndexesAnalysis`. - Add `SlotIndexesPrinterPass`. - Use `SlotIndexesWrapperPass` in legacy pass.
2024-07-09[CodeGen][NewPM] Port `machine-loops` to new pass manager (#97793)paperchalice1-4/+5
- Add `MachineLoopAnalysis`. - Add `MachineLoopPrinterPass`. - Convert to `MachineLoopInfoWrapperPass` in legacy pass manager.
2024-06-27[CodeGen] Use range-based for loops (NFC) (#96855)Kazu Hirata1-6/+4
2024-06-21[RegAlloc] Don't call always-true ShouldAllocClass (#96296)Alexis Engelke1-1/+1
Previously, there was at least one virtual function call for every allocated register. The only users of this feature are AMDGPU and RISC-V (RVV), other targets don't use this. To easily identify these cases, change the default functor to nullptr and don't call it for every allocated register.
2024-06-11[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis ↵paperchalice1-1/+1
result (#94571) Prepare for new pass manager version of `MachineDominatorTreeAnalysis`. We may need a machine dominator tree version of `DomTreeUpdater` to handle `SplitCriticalEdge` in some CodeGen passes.
2024-04-15[NFC][LLVM][CodeGen] Move LiveDebugVariables.h into ↵Piyou Chen1-1/+1
llvm/include/llvm/CodeGen (#88374) This patch make `LiveDebugVariables` can be used by passes outside of `lib/CodeGen`. If we run a pass that occurs between the split register allocation pass without preserving this pass, it will be freed and recomputed until it encounters the next pass that needs LiveDebugVariables. However, `LiveDebugVariables` will raise an assertion due to the pass being freed without emitting a debug value. This is reason we need `LiveDebugVariables` to be available for passes outside of lib/Codegen.
2023-06-16[MC] Add MCRegisterInfo::regunits for iteration over register unitsSergei Barannikov1-2/+2
Reviewed By: foad Differential Revision: https://reviews.llvm.org/D152098
2023-04-18Fix uninitialized pointer membersAkshay Khadse1-1/+1
Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D148495
2022-07-18CodeGen: Remove AliasAnalysis from regallocMatt Arsenault1-0/+1
This was stored in LiveIntervals, but not actually used for anything related to LiveIntervals. It was only used in one check for if a load instruction is rematerializable. I also don't think this was entirely correct, since it was implicitly assuming constant loads are also dereferenceable. Remove this and rely only on the invariant+dereferenceable flags in the memory operand. Set the flag based on the AA query upfront. This should have the same net benefit, but has the possible disadvantage of making this AA query nonlazy. Preserve the behavior of assuming pointsToConstantMemory implying dereferenceable for now, but maybe this should be changed.
2022-03-16Cleanup codegen includesserge-sans-paille1-3/+0
This is a (fixed) recommit of https://reviews.llvm.org/D121169 after: 1061034926 before: 1063332844 Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-0/+3
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
2022-03-10Cleanup codegen includesserge-sans-paille1-3/+0
after: 1061034926 before: 1063332844 Differential Revision: https://reviews.llvm.org/D121169
2022-02-03[nfc][regalloc] const LiveIntervals within the allocatorMircea Trofin1-15/+15
Once built, LiveIntervals are immutable. This patch captures that. Differential Revision: https://reviews.llvm.org/D118918
2021-11-02[NFC][Regalloc] Ensure Query::interferingVRegs is accurate.Mircea Trofin1-3/+1
To correctly use Query, one had to first call collectInterferingVRegs to pre-cache the query result, then call interferingVRegs. Failing the former, interferingVRegs could be stale. This did cause a bug which was addressed in D98232, but the underlying usability issue of the Query API wasn't. This patch addresses the latter by making collectInterferingVRegs an implementation detail, and having interferingVRegs play both roles. One side-effect of this is that interferingVRegs is not const anymore. Differential Revision: https://reviews.llvm.org/D112882
2021-07-13RegAlloc: Allow targets to split register allocationMatt Arsenault1-5/+10
AMDGPU normally spills SGPRs to VGPRs. Previously, since all register classes are handled at the same time, this was problematic. We don't know ahead of time how many registers will be needed to be reserved to handle the spilling. If no VGPRs were left for spilling, we would have to try to spill to memory. If the spilled SGPRs were required for exec mask manipulation, it is highly problematic because the lanes active at the point of spill are not necessarily the same as at the restore point. Avoid this problem by fully allocating SGPRs in a separate regalloc run from VGPRs. This way we know the exact number of VGPRs needed, and can reserve them for a second run. This fixes the most serious issues, but it is still possible using inline asm to make all VGPRs unavailable. Start erroring in the case where we ever would require memory for an SGPR spill. This is implemented by giving each regalloc pass a callback which reports if a register class should be handled or not. A few passes need some small changes to deal with leftover virtual registers. In the AMDGPU implementation, a new pass is introduced to take the place of PrologEpilogInserter for SGPR spills emitted during the first run. One disadvantage of this is currently StackSlotColoring is no longer used for SGPR spills. It would need to be run again, which will require more work. Error if the standard -regalloc option is used. Introduce new separate -sgpr-regalloc and -vgpr-regalloc flags, so the two runs can be controlled individually. PBQB is not currently supported, so this also prevents using the unhandled allocator.
2021-02-19[NFC][Regalloc] Share the VirtRegAuxInfo object with LiveRangeEditMircea Trofin1-1/+1
VirtRegAuxInfo is an extensibility point, so the register allocator's decision on which implementation to use should be communicated to the other users - namely, LiveRangeEdit. Differential Revision: https://reviews.llvm.org/D96898
2021-02-17[CodeGen] Use range-based for loops (NFC)Kazu Hirata1-6/+4
2020-11-03[NFC] Use [MC]Register in register allocationGaurav Jain1-4/+4
Differential Revision: https://reviews.llvm.org/D90725
2020-11-02[NFC][regalloc] Use MCRegister appropriatelyMircea Trofin1-2/+2
Differential Revision: https://reviews.llvm.org/D90506
2020-10-28RegAlloc: Clear isSSAMatt Arsenault1-0/+5
The MIR parser may infer SSA, so -run-pass=regallocgreedy would hit a verifier error after multiple vreg defs are added.
2020-10-12[NFC][MC] Use MCRegister in LiveRangeMatrixMircea Trofin1-7/+8
The change starts from LiveRangeMatrix and also checks the users of the APIs are typed accordingly. Differential Revision: https://reviews.llvm.org/D89145
2020-10-12[NFC][Regalloc] Pass VirtRegMap by reference.Mircea Trofin1-1/+1
It's never null - the reason it's modeled as a pointer is because the pass can't init it in its ctor. Passing by ref simplifies the code, too, as the null checks were unnecessary complexity. Differential Revision: https://reviews.llvm.org/D89171
2020-10-05[NFC][regalloc] Separate iteration from AllocationOrderMircea Trofin1-1/+2
This separates the two concerns - encapsulation of traversal order; and iteration. Differential Revision: https://reviews.llvm.org/D88256
2020-09-30[NFC][regalloc] Make VirtRegAuxInfo part of allocator stateMircea Trofin1-4/+3
All the state of VRAI is allocator-wide, so we can avoid creating it every time we need it. In addition, the normalization function is allocator-specific. In a next change, we can simplify that design in favor of just having it as a virtual member. Differential Revision: https://reviews.llvm.org/D88499
2020-09-29[NFC][regalloc] Unit test for AllocationOrder iteration.Mircea Trofin1-1/+2
Added unittests. In the process, separated core construction - which just needs the hits, order, and 'HardHints' values - from construction from current register allocation state, to simplify testing. Differential Revision: https://reviews.llvm.org/D88455
2020-09-16[NFC][Regalloc] accessors for 'reg' and 'weight'Mircea Trofin1-4/+4
Also renamed the fields to follow style guidelines. Accessors help with readability - weight mutation, in particular, is easier to follow this way. Differential Revision: https://reviews.llvm.org/D87725
2020-06-30RegAlloc: Start using RegisterMatt Arsenault1-11/+11
2020-04-26[Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directlySimon Pilgrim1-1/+1
Both PassSupport.h and PassAnalysisSupport.h are only supposed to be included via Pass.h. Differential Revision: https://reviews.llvm.org/D78815
2020-03-09Move Spiller.h from lib/ directory path to include/CodeGen. NFCMarcello Maggioni1-1/+1
This allows Spiller.h to be used and included outside of the lib/CodeGen directory. For example to be used in the lib/Target directory or other places.
generated by cgit v1.1 at 2025-08-02 21:17:34 +0000