aboutsummaryrefslogtreecommitdiff
path: root/clang/lib/Headers/immintrin.h
AgeCommit message (Expand)AuthorFilesLines
2024-01-17[Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (#77686)Paul T Robinson1-0/+57
2023-12-21[clang] Separate Intel ADC instrinsics from ADX intrinsics (#75992)Max Winkler1-2/+6
2023-10-27[Headers] Add \returns to _rdpid_u32 (#70481)Paul T Robinson1-1/+3
2023-07-20[X86] Add AVX-VNNI-INT16 instructions.Freddy Ye1-0/+5
2023-07-20[X86] Add SM4 instructions.Freddy Ye1-0/+5
2023-07-20[X86] Add SM3 instructions.Freddy Ye1-0/+5
2023-07-20[X86] Add SHA512 instructions.Freddy Ye1-0/+5
2023-04-26[Headers] Revise conditional for rdrand64_stepPaul Robinson1-8/+4
2023-04-06[X86] Add AMX_COMPLEX to GraniterapidsFreddy Ye1-1/+1
2023-04-04[Headers] Add some intrinsic function descriptions to immintrin.h.Paul Robinson1-0/+87
2023-04-04[X86] Support AMX Complex instructionsXiang1 Zhang1-0/+5
2023-02-03[clang] Change AMX macros to match names from GCCJoe Loser1-2/+2
2022-11-30[X86] include cmpccxaddintrin.h from immintrin.h to x86gprintrin.hFreddy Ye1-5/+0
2022-10-31[X86] Add AVX-NE-CONVERT instructions.Freddy Ye1-0/+5
2022-10-28[X86] Add AVX-VNNI-INT8 instructions.Freddy Ye1-0/+5
2022-10-28[X86] Add AVX-IFMA instructions.Freddy Ye1-0/+5
2022-10-25[X86] Add CMPCCXADD instructions.Freddy Ye1-0/+5
2022-10-22[X86] Add AMX-FP16 instructions.Xiang1 Zhang1-0/+4
2022-08-24[X86] Emulate _rdrand64_step with two rdrand32 if it is 32bitBing1 Yu1-0/+17
2022-08-24Revert "[X86] Emulate _rdrand64_step with two rdrand32 if it is 32bit"Bing1 Yu1-17/+0
2022-08-24[X86] Emulate _rdrand64_step with two rdrand32 if it is 32bitBing1 Yu1-0/+17
2022-08-23[X86][AVX512FP16] Relax limitation to AVX512FP16 intrinsics. NFCIPhoebe Wang1-8/+4
2022-05-08[X86] Fix some signedness errors in x86 headersSimon Pilgrim1-15/+15
2021-11-17[clang] Make -masm=intel affect inline asm styleNico Weber1-8/+8
2021-09-14Check supported architectures in sseXYZ/avxXYZ headersserge-sans-paille1-0/+4
2021-08-10[X86] AVX512FP16 instructions enabling 1/6Wang, Pengfei1-0/+14
2021-03-28[X86] Don't define vpclmulqdq or vaes intrinsics in the headers unless avx512...Craig Topper1-5/+5
2020-10-31[X86] Support Intel avxvnniLiu, Chen31-0/+5
2020-10-13[X86] Add HRESET instruction.Wang, Pengfei1-0/+2
2020-10-04[X86] Consolidate wide Key Locker intrinsics into the same header as the othe...Craig Topper1-6/+1
2020-09-30[X86] Support Intel Key LockerXiang1 Zhang1-0/+10
2020-07-07[X86-64] Support Intel AMX IntrinsicXiang1 Zhang1-0/+5
2020-04-30Add header guards for header files that should not be included on the PS4 pla...Douglas Yung1-72/+126
2020-04-09[X86] Add TSXLDTRK instructions.WangTianQing1-0/+4
2020-04-02[X86] Add SERIALIZE instruction.WangTianQing1-0/+4
2019-12-19[X86] Mark various pointer arguments in builtins as constWarren Ristow1-3/+3
2019-10-11[X86] Always define the tzcnt intrinsics even when _MSC_VER is defined.Craig Topper1-2/+1
2019-06-06[X86] Add ENQCMD instructionsPengfei Wang1-0/+4
2019-05-31[X86] Add VP2INTERSECT instructionsPengfei Wang1-0/+10
2019-05-13[X86] Make `x86intrin.h`, `immintrin.h` includable with `-fno-gnu-inline-asm`.Volodymyr Sapsai1-2/+2
2019-05-06Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper ...Luo, Yuanke1-0/+9
2019-04-08Move the builtin headers to use the new license file header.Chandler Carruth1-17/+3
2019-03-24[X86] Add BSR/BSF/BSWAP intrinsics to ia32intrin.h to match gcc.Craig Topper1-12/+0
2019-01-16Recommit r351160 "[X86] Make _xgetbv/_xsetbv on non-windows platforms"Craig Topper1-2/+1
2019-01-15Revert "[X86] Make _xgetbv/_xsetbv on non-windows platforms"Benjamin Kramer1-1/+2
2019-01-15[X86] Make _xgetbv/_xsetbv on non-windows platformsCraig Topper1-2/+1
2018-09-28[X86] Add the movbe instruction intrinsics from icc.Craig Topper1-0/+59
2018-06-14[X86] Add inline assembly versions of _InterlockedExchange_HLEAcquire/Release...Craig Topper1-0/+84
2018-05-30[X86] Remove 'return' from a bunch of intrinsics that return void and use a b...Craig Topper1-4/+4
2018-05-25[x86] invpcid intrinsicGabor Buella1-0/+4