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47 hours[Clang][CodeGen] Emit “trap reasons” on UBSan traps (#145967)Anthony Tran3-31/+88
This patch adds a human readable trap category and message to UBSan traps. The category and message are encoded in a fake frame in the debug info where the function is a fake inline function where the name encodes the trap category and message. This is the same mechanism used by Clang’s `__builtin_verbose_trap()`. This change allows consumers of binaries built with trapping UBSan to more easily identify the reason for trapping. In particular LLDB already has a frame recognizer that recognizes the fake function names emitted in debug info by this patch. A patch testing this behavior in LLDB will be added in a separately. The human readable trap messages are based on the messages currently emitted by the userspace runtime for UBSan in compiler-rt. Note the wording is not identical because the userspace UBSan runtime has access to dynamic information that is not available during Clang’s codegen. Test cases for each UBSan trap kind are included. This complements the [`-fsanitize-annotate-debug-info` feature](https://github.com/llvm/llvm-project/pull/141997). While `-fsanitize-annotate-debug-info` attempts to annotate all UBSan-added instructions, this feature (`-fsanitize-debug-trap-reasons`) only annotates the final trap instruction using SanitizerHandler information. This work is part of a GSoc 2025 project.
48 hours[ObjCARC] Completely remove ObjCARCAPElimPass (#150717)AZero131-6/+0
ObjCARCAPElimPass has been made obsolete now that we remove unused autorelease pools.
3 days[WebAssembly,clang] Add __builtin_wasm_test_function_pointer_signature (#150201)Hood Chatham1-0/+61
Tests if the runtime type of the function pointer matches the static type. If this returns false, calling the function pointer will trap. Uses `@llvm.wasm.ref.test.func` added in #147486. Also adds a "gc" wasm feature to gate the use of the ref.test instruction.
4 days[AMDGPU] Support builtin/intrinsics for load monitors on gfx1250 (#150540)Changpeng Fang1-0/+35
4 days[HLSL] Avoid putting the byval attribute on out and inout parameters (#150495)Deric C.1-14/+22
Fixes #148063 by preventing the ByVal attribute from being placed on out and inout function parameters which causes them to be eliminated by the Dead Store Elimination (DSE) pass.
4 daysclang: Handle deleting pointers to incomplete array types (#150359)Harald van Dijk1-24/+3
CodeGenFunction::EmitCXXDeleteExpr contains logic to go from a pointer to an array to a pointer to the first element of the array using a getelementptr LLVM IR instruction. This was done for pointers that were not variable length arrays, as pointers to variable length arrays never existed in LLVM IR, but rather than checking for arrays that were not variable length arrays, it checked for arrays that had a constant bound. This caused incomplete arrays to be inadvertently omitted. This getelementptr was necessary back when LLVM IR used typed pointers, but they have been gone for a while, a gep with a constant zero offset does nothing now, so we can simplify the code by removing that.
4 days[OpenMP] Fix initialization order for CopyOverlappedEntryGaps (#150431)Julian Brown1-2/+2
NFC.
4 days[OpenMP] Don't emit redundant zero-sized mapping nodes for overlapped ↵Julian Brown1-47/+110
structs (#148947) The handling of overlapped structure mapping in CGOpenMPRuntime.cpp can lead to redundant zero-sized mapping nodes at runtime. This patch fixes it using a combination of approaches: trivially adjacent struct members won't have a mapping node created between them, and for more complicated cases (inheritance) the physical layout of the struct/class is used to make sure that elements aren't missed. I've introduced a new class to track the state whilst iterating over the struct. This reduces a bit of redundancy in the code (accumulating CombinedInfo both during and after the loop), which I think is a bit neater. Before: omptarget --> Entry 0: Base=0x00007fff8d483830, Begin=0x00007fff8d483830, Size=48, Type=0x20, Name=unknown omptarget --> Entry 1: Base=0x00007fff8d483830, Begin=0x00007fff8d483830, Size=0, Type=0x1000000000003, Name=unknown omptarget --> Entry 2: Base=0x00007fff8d483830, Begin=0x00007fff8d483834, Size=0, Type=0x1000000000003, Name=unknown omptarget --> Entry 3: Base=0x00007fff8d483830, Begin=0x00007fff8d483838, Size=0, Type=0x1000000000003, Name=unknown omptarget --> Entry 4: Base=0x00007fff8d483830, Begin=0x00007fff8d48383c, Size=20, Type=0x1000000000003, Name=unknown omptarget --> Entry 5: Base=0x00007fff8d483830, Begin=0x00007fff8d483854, Size=0, Type=0x1000000000003, Name=unknown omptarget --> Entry 6: Base=0x00007fff8d483830, Begin=0x00007fff8d483858, Size=0, Type=0x1000000000003, Name=unknown omptarget --> Entry 7: Base=0x00007fff8d483830, Begin=0x00007fff8d48385c, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 8: Base=0x00007fff8d483830, Begin=0x00007fff8d483830, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 9: Base=0x00007fff8d483830, Begin=0x00007fff8d483834, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 10: Base=0x00007fff8d483830, Begin=0x00007fff8d483838, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 11: Base=0x00007fff8d483840, Begin=0x00005e7665275130, Size=32, Type=0x1000000000013, Name=unknown omptarget --> Entry 12: Base=0x00007fff8d483830, Begin=0x00007fff8d483850, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 13: Base=0x00007fff8d483830, Begin=0x00007fff8d483854, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 14: Base=0x00007fff8d483830, Begin=0x00007fff8d483858, Size=4, Type=0x1000000000003, Name=unknown After: omptarget --> Entry 0: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e0, Size=48, Type=0x20, Name=unknown omptarget --> Entry 1: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562ec, Size=20, Type=0x1000000000003, Name=unknown omptarget --> Entry 2: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f5630c, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 3: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e0, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 4: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e4, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 5: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e8, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 6: Base=0x00007fffd0f562f0, Begin=0x000058b6013fb130, Size=32, Type=0x1000000000013, Name=unknown omptarget --> Entry 7: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f56300, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 8: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f56304, Size=4, Type=0x1000000000003, Name=unknown omptarget --> Entry 9: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f56308, Size=4, Type=0x1000000000003, Name=unknown For code: #include <cstdlib> #include <cstdio> struct S { int x; int y; int z; int *p1; int *p2; }; struct T : public S { int a; int b; int c; }; int main() { T v; v.p1 = (int*) calloc(8, sizeof(int)); v.p2 = (int*) calloc(8, sizeof(int)); #pragma omp target map(tofrom: v, v.x, v.y, v.z, v.p1[:8], v.a, v.b, v.c) { v.x++; v.y += 2; v.z += 3; v.p1[0] += 4; v.a += 7; v.b += 5; v.c += 6; } return 0; }
4 days[NFC][AMDGPU] Rename "amdgpu-as" to "amdgpu-synchronize-as" (#148627)Pierre van Houtryve1-1/+1
"amdgpu-as" is way too vague and doesn't give enough context. We may want to support it on normal atomics too, to control the synchronized (ordered) AS. If we do that, the name has to be less vague.
5 days[NFC][Clang][FMV] Make FMV priority data type future proof. (#150079)Alexandros Lamprineas3-7/+8
FMV priority is the returned value of a polymorphic function. On RISC-V and X86 targets a 32-bit value is enough. On AArch64 we currently need 64 bits and we will soon exceed that. APInt seems to be a suitable replacement for uint64_t, presumably with minimal compile time overhead. It allows bit manipulation, comparison and variable bit width.
6 days[Clang] Add elementwise maximumnum/minimumnum builtin functions (#149775)Wenju He1-0/+16
Addresses https://github.com/llvm/llvm-project/issues/112164. minimumnum and maximumnum intrinsics were added in 5bf81e53dbea. The new built-ins can be used for implementing OpenCL math function fmax and fmin in #128506.
6 days[KeyInstr] Inline asm atoms (#149076)Orlando Cazalet-Hyams1-1/+6
7 daysAMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)Changpeng Fang1-0/+5
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
7 days[DebugInfo] Remove intrinsic-flavours of findDbgUsers (#149816)Jeremy Morse1-3/+2
This is one of the final remaining debug-intrinsic specific codepaths out there, and pieces of cross-LLVM infrastructure to do with debug intrinsics.
7 days[KeyInstr] goto stmt atoms (#149101)Orlando Cazalet-Hyams1-0/+4
9 daysReland [Clang] Make the SizeType, SignedSizeType and PtrdiffType be named ↵YexuanXiao5-8/+10
sugar types (#149613) The checks for the 'z' and 't' format specifiers added in the original PR #143653 had some issues and were overly strict, causing some build failures and were consequently reverted at https://github.com/llvm/llvm-project/commit/4c85bf2fe8042c855c9dd5be4b02191e9d071ffd. In the latest commit https://github.com/llvm/llvm-project/pull/149613/commits/27c58629ec76a703fde9c0b99b170573170b4a7a, I relaxed the checks for the 'z' and 't' format specifiers, so warnings are now only issued when they are used with mismatched types. The original intent of these checks was to diagnose code that assumes the underlying type of `size_t` is `unsigned` or `unsigned long`, for example: ```c printf("%zu", 1ul); // Not portable, but not an error when size_t is unsigned long ``` However, it produced a significant number of false positives. This was partly because Clang does not treat the `typedef` `size_t` and `__size_t` as having a common "sugar" type, and partly because a large amount of existing code either assumes `unsigned` (or `unsigned long`) is `size_t`, or they define the equivalent of size_t in their own way (such as sanitizer_internal_defs.h).https://github.com/llvm/llvm-project/blob/2e67dcfdcd023df2f06e0823eeea23990ce41534/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h#L203
10 days[Sanitizer] remove array-bounds-pseudofn (#149430)Florian Mayer1-16/+7
This has been replaced by -fsanitize-annotate-debug-info
10 days[Clang][AMDGPU] Add the missing builtin `__builtin_amdgcn_sqrt_bf16` (#149447)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
10 days[clang][CodeGen] Set `dead_on_return` when passing arguments indirectlyAntonio Frighetto1-1/+14
Let Clang emit `dead_on_return` attribute on pointer arguments that are passed indirectly, namely, large aggregates that the ABI mandates be passed by value; thus, the parameter is destroyed within the callee. Writes to such arguments are not observable by the caller after the callee returns. This should desirably enable further MemCpyOpt/DSE optimizations. Previous discussion: https://discourse.llvm.org/t/rfc-add-dead-on-return-attribute/86871.
10 days[AMDGPU] Add support for `v_tanh_f16` on gfx1250 (#149439)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
10 daysRevert "[Clang] Make the SizeType, SignedSizeType and PtrdiffType be named ↵Kazu Hirata5-10/+8
sugar types instead of built-in types (#143653)" This reverts commit c27e283cfbca2bd22f34592430e98ee76ed60ad8. A builbot failure has been reported: https://lab.llvm.org/buildbot/#/builders/186/builds/10819/steps/10/logs/stdio I'm also getting a large number of warnings related to %zu and %zx.
11 days[Clang] Make the SizeType, SignedSizeType and PtrdiffType be named sugar ↵YexuanXiao5-8/+10
types instead of built-in types (#143653) Including the results of `sizeof`, `sizeof...`, `__datasizeof`, `__alignof`, `_Alignof`, `alignof`, `_Countof`, `size_t` literals, and signed `size_t` literals, the results of pointer-pointer subtraction and checks for standard library functions (and their calls). The goal is to enable clang and downstream tools such as clangd and clang-tidy to provide more portable hints and diagnostics. The previous discussion can be found at #136542. This PR implements this feature by introducing a new subtype of `Type` called `PredefinedSugarType`, which was considered appropriate in discussions. I tried to keep `PredefinedSugarType` simple enough yet not limited to `size_t` and `ptrdiff_t` so that it can be used for other purposes. `PredefinedSugarType` wraps a canonical `Type` and provides a name, conceptually similar to a compiler internal `TypedefType` but without depending on a `TypedefDecl` or a source file. Additionally, checks for the `z` and `t` format specifiers in format strings for `scanf` and `printf` were added. It will precisely match expressions using `typedef`s or built-in expressions. The affected tests indicates that it works very well. Several code require that `SizeType` is canonical, so I kept `SizeType` to its canonical form. The failed tests in CI are allowed to fail. See the [comment](https://github.com/llvm/llvm-project/pull/135386#issuecomment-3049426611) in another PR #135386.
11 days[CodeGen] Remove an unnecessary cast (NFC) (#149339)Kazu Hirata1-2/+1
getExceptionMode() already returns LangOptions::FPExceptionModeKind.
11 days[AMDGPU] Add support for `v_tanh_f32` on gfx1250 (#149360)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
11 days[AMDGPU] Add support for `v_cos_bf16` on gfx1250 (#149355)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
11 days[Clang][CodeGen][X86] don't coerce int128 into `{i64,i64}` for SysV-like ↵T0b1-iOS1-8/+24
ABIs (#135230) Currently, clang coerces (u)int128_t to two i64 IR parameters when they are passed in registers. This leads to broken debug info for them after applying SROA+InstCombine. SROA generates IR like this ([godbolt](https://godbolt.org/z/YrTa4chfc)): ```llvm define dso_local { i64, i64 } @add(i64 noundef %a.coerce0, i64 noundef %a.coerce1) { entry: %a.sroa.2.0.insert.ext = zext i64 %a.coerce1 to i128 %a.sroa.2.0.insert.shift = shl nuw i128 %a.sroa.2.0.insert.ext, 64 %a.sroa.0.0.insert.ext = zext i64 %a.coerce0 to i128 %a.sroa.0.0.insert.insert = or i128 %a.sroa.2.0.insert.shift, %a.sroa.0.0.insert.ext #dbg_value(i128 %a.sroa.0.0.insert.insert, !17, !DIExpression(), !18) // ... !17 = !DILocalVariable(name: "a", arg: 1, scope: !10, file: !11, line: 1, type: !14) // ... ``` and InstCombine then removes the `or`, moving it into the `DIExpression`, and the `shl` at which point the debug info salvaging in `Transforms/Local` replaces the arguments with `poison` as it does not allow constants larger than 64 bit in `DIExpression`s. I'm working under the assumption that there is interest in fixing this. If not, please tell me. By not coercing `int128_t`s into `{i64, i64}` but keeping them as `i128`, the debug info stays intact and SelectionDAG then generates two `DW_OP_LLVM_fragment` expressions for the two corresponding argument registers. Given that the ABI code for x64 seems to not coerce the argument when it is passed on the stack, it should not lead to any problems keeping it as an `i128` when it is passed in registers. Alternatively, this could be fixed by checking if a constant value fits in 64 bits in the debug info salvaging code and then extending the value on the expression stack to the necessary width. This fixes InstCombine breaking the debug info but then SelectionDAG removes the expression and that seems significantly more complex to debug. Another fix may be to generate `DW_OP_LLVM_fragment` expressions when removing the `or` as it gets marked as disjoint by InstCombine. However, I don't know if the KnownBits information is still available at the time the `or` gets removed and it would probably require refactoring of the debug info salvaging code as that currently only seems to replace single expressions and is not designed to support generating new debug records. Converting `(u)int128_t` arguments to `i128` in the IR seems like the simpler solution, if it doesn't cause any ABI issues.
11 days[AMDGPU] Add support for `v_sin_bf16` on gfx1250 (#149241)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
11 days[AMDGPU] Add support for `v_exp_bf16` on gfx1250 (#149229)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
11 days[Sanitize] fix crash in -fsanitize-annotate-debug-info (#149237)Florian Mayer1-5/+8
12 days[clang][CodeGen] Fix metadata when vectorization is disabled by pragma (#135163)Ryotaro Kasuga1-17/+29
Currently, when specifying `vectorize(disable) unroll_count(8)`, the generated metadata appears as follows: ``` !loop0 = !{!"loop0", !vectorize_width, !followup} !vectorize_width = !{!"llvm.loop.vectorize.width", i32 1} !followup = !{!"llvm.loop.vectorize.followup_all", !unroll} !unroll = !{!"llvm.loop.unroll_count", i32 8} ``` Since the metadata `!vectorize_width` implies that the vectorization is disabled, the vectorization process is skipped, and the `!followup` metadata is not processed correctly. This patch addresses the issue by directly appending properties to the metadata node when vectorization is disabled, instead of creating a new follow-up MDNode. In the above case, the generated metadata will now look like this: ``` !loop0 = !{!"loop0", !vectorize_width, !vectorize_width, !unroll} !vectorize_width = !{!"llvm.loop.vectorize.width", i32 1} !unroll = !{!"llvm.loop.unroll_count", i32 8} ```
12 days[AMDGPU] Add support for `v_log_bf16` on gfx1250 (#149201)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
12 days[AMDGPU] Add support for `v_rsq_bf16` on gfx1250 (#149194)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
12 days[HLSL][DXIL] Implement `refract` intrinsic (#147342)raoanag1-0/+12
- [x] Implement refract using HLSL source in hlsl_intrinsics.h - [x] Implement the refract SPIR-V target built-in in clang/include/clang/Basic/BuiltinsSPIRV.td - [x] Add sema checks for refract to CheckSPIRVBuiltinFunctionCall in clang/lib/Sema/SemaSPIRV.cpp - [x] Add codegen for spv refract to EmitSPIRVBuiltinExpr in CGBuiltin.cpp - [x] Add codegen tests to clang/test/CodeGenHLSL/builtins/refract.hlsl - [x] Add spv codegen test to clang/test/CodeGenSPIRV/Builtins/refract.c - [x] Add sema tests to clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl - [x] Add spv sema tests to clang/test/SemaSPIRV/BuiltIns/refract-errors.c - [x] Create the int_spv_refract intrinsic in IntrinsicsSPIRV.td - [x] In SPIRVInstructionSelector.cpp create the refract lowering and map it to int_spv_refract in SPIRVInstructionSelector::selectIntrinsic. - [x] Create SPIR-V backend test case in llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll - [x] Check for what OpenCL support is needed. Resolves https://github.com/llvm/llvm-project/issues/99153
12 days[clang] Move `ExceptionHandling` from `LangOptions` to `CodeGenOptions` ↵Jan Svoboda2-28/+31
(#148982) This PR removes the command line parsing workaround introduced in https://github.com/llvm/llvm-project/pull/146342 by moving `LangOptions::ExceptionHandling` to `CodeGenOptions` that get parsed even for IR input. Additionally, this improves layering, where the codegen library now checks `CodeGenOptions` instead of `LangOptions` for exception handling. (This got enabled by https://github.com/llvm/llvm-project/pull/146422.)
12 days[KeyInstr] Fix verifier check (#149043)Orlando Cazalet-Hyams1-0/+4
The verifier check was in the wrong place, meaning it wasn't actually checking many instructions. Fixing that causes a test failure (coro-dwarf-key-instrs.cpp) because coros turn off the feature but still annotate instructions with the metadata (which is a supported situation, but the verifier doesn't like it, and it's hard to teach the verifier to like it). Fix that by avoiding emitting any key instruction metadata if the DISubprogram has opted out of key instructions.
12 days[RISCV] Implement Builtins for XAndesBFHCvt extension. (#148804)Jim Lin1-0/+6
XAndesBFHCvt provides two builtins functions for converting between float and bf16. Users can use them to convert bf16 values loaded from memory to float, perform arithmetic operations, then convert them back to bf16 and store them to memory. The load/store and move operations for bf16 will be handled in a later patch.
13 daysAMDGPU: Implement builtins for gfx1250 wmma instructions (#148991)Changpeng Fang1-1/+198
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Co-authored-by: Shilei Tian <Shilei.Tian@amd.com>
13 days[Clang] Fix FE crash during CGCoroutine GRO Alloca Emission (#148962)Yuxuan Chen1-5/+9
Fixes: https://github.com/llvm/llvm-project/issues/148953 Currently when coroutine return object type is const qualified, we don't do direct emission. The regular emission logic assumed that the auto var emission will always result in an `AllocaInst`. However, based on my findings, NRVO var emissions don't result in `AllocaInst`s. Therefore, this [assertion](https://github.com/llvm/llvm-project/blob/1a940bfff9176fb38a71b0045d7ae25df9a4ca7d/clang/lib/CodeGen/CGCoroutine.cpp#L712) will fail. Since the NRVOed returned object don't live on the coroutine frame, we won't have the problem of it outliving the coroutine frame, therefore, we can safely omit this metadata.
13 days[AMDGPU] Add support for `v_rcp_bf16` on gfx1250 (#148916)Shilei Tian1-0/+1
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
13 days[clang][modules] Serialize `CodeGenOptions` (#146422)Jan Svoboda3-20/+25
Some `LangOptions` duplicate their `CodeGenOptions` counterparts. My understanding is that this was done solely because some infrastructure (like preprocessor initialization, serialization, module compatibility checks, etc.) were only possible/convenient for `LangOptions`. This PR implements the missing support for `CodeGenOptions`, which makes it possible to remove some duplicate `LangOptions` fields and simplify the logic. Motivated by https://github.com/llvm/llvm-project/pull/146342.
13 days[PowerPC] Add DMF basic builtins (#145372)RolandF771-0/+5
Add support for PPC Dense Math basic builtins dmsetdmrz, dmmr, dmxor.
13 daysRemove Native Client support (#133661)Brad Smith5-123/+2
Remove the Native Client support now that it has finally reached end of life.
13 days[DebugInfo][RemoveDIs] Suppress getNextNonDebugInfoInstruction (#144383)Jeremy Morse1-2/+2
There are no longer debug-info instructions, thus we don't need this skipping. Horray!
13 days[CodeGen][ObjC] Include all referenced protocols in protocol list (#148827)Hugo Melder1-2/+3
When constructing the protocol list in the class metadata generation (`GenerateClass`), only the protocols from the base class are added but not protocols declared in class extensions. This is fixed by using `all_referenced_protocol_{begin, end}` instead of `protocol_{begin, end}`, matching the behaviour on Apple platforms. A unit test is included to check if all protocol metadata was emitted and that no duplication occurs in the protocol list. Fixes https://github.com/gnustep/libobjc2/issues/339 CC: @davidchisnall
14 days[clang][ObjC][PAC] Add ptrauth protections to objective-c (#147899)Oliver Hunt4-31/+140
This PR introduces the use of pointer authentication to objective-c[++]. This includes: * __ptrauth qualifier support for ivars * protection of isa and super fields * protection of SEL typed ivars * protection of class_ro_t data * protection of methodlist pointers and content
14 days[AMDGPU] Add support for `v_tanh_bf16` on gfx1250 (#147425)Shilei Tian1-0/+3
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
14 days[DebugInfo] Add option for producing no source-file hash (#148657)Jeremy Morse1-0/+2
Clang can chose which sort of source-file hash is attached to a DIFile metadata node. However, whenever hashing is possible, we /always/ attach a hash. This patch permits users who want DWARF5 but don't want the file hashes to opt out, by adding a "none" option to the -gsrc-hash option that skips hash computation.
2025-07-14[KeyInstr] Disable key-instructions for coroutine scopes (#147551)Jeremy Morse1-1/+5
At this time (immediately prior to llvm21 branching) we haven't instrumented coroutine generation to identify the "key" instructions of things like co_return and similar. This will lead to worse stepping behaviours, as there won't be any key instruction for those lines. This patch removes the key-instructions flag from the DISubprograms for coroutines, which will cause AsmPrinter to use the "old" / existing linetable stepping behaviour, avoiding a regression until we can instrument these constructs. (I'm going to post on discourse about whether this is a good idea or not in a moment)
2025-07-11[clang][CodeGen] Preserve addrspace of enqueue_kernel builtin. (#148062)jofrn1-2/+2
__enqueue_kernel_varargs' last parameter is in addrspace(5), but CodeGen currently misses this qualifier. This commit fixes the code to preserve the qualifier by referencing Alloca, which has its casts removed, rather than TmpPtr.
2025-07-09[SPIRV] Add more id and range builtIns (#143909)Victor Lomuller2-3/+55
The patch adds intrinsics and lowering logic for GlobalSize, GlobalOffset, SubgroupMaxSize, NumWorkgroups, WorkgroupSize, WorkgroupId, LocalInvocationId, GlobalInvocationId, SubgroupSize, NumSubgroups, SubgroupId and SubgroupLocalInvocationId SPIR-V builtins. The patch also extend spv_thread_id, spv_group_id and spv_thread_id_in_group to return anyint rather than i32. This allows the intrinsics to support the opencl environment. For each of the intrinsics, new clang builtins were added as well as a binding for the SPIR-V "friendly" format. The original format doesn't define such binding (uses global variables) but it is not possible to express the Input SC which is normally required by the environement specs, and using builtin functions is the most usual approach for other backend and programming models.