diff options
Diffstat (limited to 'mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp')
| -rw-r--r-- | mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp index 456bfab..d22364e 100644 --- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp +++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp @@ -61,10 +61,10 @@ static Value truncOrExtToLLVMType(ConversionPatternRewriter &rewriter, IntegerType::get(rewriter.getContext(), converter.getIndexTypeBitwidth()); // TODO: use <=> in C++20. if (indexBitwidth > intWidth) { - return rewriter.create<LLVM::SExtOp>(loc, indexBitwidthType, value); + return LLVM::SExtOp::create(rewriter, loc, indexBitwidthType, value); } if (indexBitwidth < intWidth) { - return rewriter.create<LLVM::TruncOp>(loc, indexBitwidthType, value); + return LLVM::TruncOp::create(rewriter, loc, indexBitwidthType, value); } return value; } @@ -82,12 +82,12 @@ static bool canBeCalledWithBarePointers(gpu::GPUFuncOp func) { static Value getLaneId(ConversionPatternRewriter &rewriter, Location loc, const unsigned indexBitwidth) { auto int32Type = IntegerType::get(rewriter.getContext(), 32); - Value zero = rewriter.create<arith::ConstantIntOp>(loc, 0, 32); - Value minus1 = rewriter.create<arith::ConstantIntOp>(loc, -1, 32); - Value mbcntLo = rewriter.create<ROCDL::MbcntLoOp>(loc, int32Type, - ValueRange{minus1, zero}); - Value laneId = rewriter.create<ROCDL::MbcntHiOp>(loc, int32Type, - ValueRange{minus1, mbcntLo}); + Value zero = arith::ConstantIntOp::create(rewriter, loc, 0, 32); + Value minus1 = arith::ConstantIntOp::create(rewriter, loc, -1, 32); + Value mbcntLo = ROCDL::MbcntLoOp::create(rewriter, loc, int32Type, + ValueRange{minus1, zero}); + Value laneId = ROCDL::MbcntHiOp::create(rewriter, loc, int32Type, + ValueRange{minus1, mbcntLo}); return laneId; } static constexpr StringLiteral amdgcnDataLayout = @@ -110,21 +110,21 @@ struct GPULaneIdOpToROCDL : ConvertOpToLLVMPattern<gpu::LaneIdOp> { // followed by: %lid = call @llvm.amdgcn.mbcnt.hi(-1, %mlo) Type intTy = IntegerType::get(context, 32); - Value zero = rewriter.create<arith::ConstantIntOp>(loc, 0, 32); - Value minus1 = rewriter.create<arith::ConstantIntOp>(loc, -1, 32); - Value mbcntLo = - rewriter.create<ROCDL::MbcntLoOp>(loc, intTy, ValueRange{minus1, zero}); - Value laneId = rewriter.create<ROCDL::MbcntHiOp>( - loc, intTy, ValueRange{minus1, mbcntLo}); + Value zero = arith::ConstantIntOp::create(rewriter, loc, 0, 32); + Value minus1 = arith::ConstantIntOp::create(rewriter, loc, -1, 32); + Value mbcntLo = ROCDL::MbcntLoOp::create(rewriter, loc, intTy, + ValueRange{minus1, zero}); + Value laneId = ROCDL::MbcntHiOp::create(rewriter, loc, intTy, + ValueRange{minus1, mbcntLo}); // Truncate or extend the result depending on the index bitwidth specified // by the LLVMTypeConverter options. const unsigned indexBitwidth = getTypeConverter()->getIndexTypeBitwidth(); if (indexBitwidth > 32) { - laneId = rewriter.create<LLVM::SExtOp>( - loc, IntegerType::get(context, indexBitwidth), laneId); + laneId = LLVM::SExtOp::create( + rewriter, loc, IntegerType::get(context, indexBitwidth), laneId); } else if (indexBitwidth < 32) { - laneId = rewriter.create<LLVM::TruncOp>( - loc, IntegerType::get(context, indexBitwidth), laneId); + laneId = LLVM::TruncOp::create( + rewriter, loc, IntegerType::get(context, indexBitwidth), laneId); } rewriter.replaceOp(op, {laneId}); return success(); @@ -149,8 +149,8 @@ struct GPUSubgroupSizeOpToROCDL : ConvertOpToLLVMPattern<gpu::SubgroupSizeOp> { /*bitWidth=*/32, /*lower=*/isBeforeGfx10 ? 64 : 32, /*upper=*/op.getUpperBoundAttr().getInt() + 1); } - Value wavefrontOp = rewriter.create<ROCDL::WavefrontSizeOp>( - op.getLoc(), rewriter.getI32Type(), bounds); + Value wavefrontOp = ROCDL::WavefrontSizeOp::create( + rewriter, op.getLoc(), rewriter.getI32Type(), bounds); wavefrontOp = truncOrExtToLLVMType(rewriter, op.getLoc(), wavefrontOp, *getTypeConverter()); rewriter.replaceOp(op, {wavefrontOp}); @@ -190,44 +190,44 @@ struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> { auto int32Type = IntegerType::get(rewriter.getContext(), 32); Value width = adaptor.getWidth(); - Value zero = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 0); - Value negwidth = rewriter.create<LLVM::SubOp>(loc, int32Type, zero, width); - Value add = rewriter.create<LLVM::AddOp>(loc, int32Type, srcLaneId, width); + Value zero = LLVM::ConstantOp::create(rewriter, loc, int32Type, 0); + Value negwidth = LLVM::SubOp::create(rewriter, loc, int32Type, zero, width); + Value add = LLVM::AddOp::create(rewriter, loc, int32Type, srcLaneId, width); Value widthOrZeroIfOutside = - rewriter.create<LLVM::AndOp>(loc, int32Type, add, negwidth); + LLVM::AndOp::create(rewriter, loc, int32Type, add, negwidth); Value dstLane; switch (op.getMode()) { case gpu::ShuffleMode::UP: - dstLane = rewriter.create<LLVM::SubOp>(loc, int32Type, srcLaneId, - adaptor.getOffset()); + dstLane = LLVM::SubOp::create(rewriter, loc, int32Type, srcLaneId, + adaptor.getOffset()); break; case gpu::ShuffleMode::DOWN: - dstLane = rewriter.create<LLVM::AddOp>(loc, int32Type, srcLaneId, - adaptor.getOffset()); + dstLane = LLVM::AddOp::create(rewriter, loc, int32Type, srcLaneId, + adaptor.getOffset()); break; case gpu::ShuffleMode::XOR: - dstLane = rewriter.create<LLVM::XOrOp>(loc, int32Type, srcLaneId, - adaptor.getOffset()); + dstLane = LLVM::XOrOp::create(rewriter, loc, int32Type, srcLaneId, + adaptor.getOffset()); break; case gpu::ShuffleMode::IDX: dstLane = adaptor.getOffset(); break; } - Value isActiveSrcLane = rewriter.create<LLVM::ICmpOp>( - loc, LLVM::ICmpPredicate::slt, dstLane, widthOrZeroIfOutside); - Value selectDstLane = rewriter.create<LLVM::SelectOp>(loc, isActiveSrcLane, - dstLane, srcLaneId); - Value two = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 2); + Value isActiveSrcLane = LLVM::ICmpOp::create( + rewriter, loc, LLVM::ICmpPredicate::slt, dstLane, widthOrZeroIfOutside); + Value selectDstLane = LLVM::SelectOp::create(rewriter, loc, isActiveSrcLane, + dstLane, srcLaneId); + Value two = LLVM::ConstantOp::create(rewriter, loc, int32Type, 2); Value dwordAlignedDstLane = - rewriter.create<LLVM::ShlOp>(loc, int32Type, selectDstLane, two); + LLVM::ShlOp::create(rewriter, loc, int32Type, selectDstLane, two); SmallVector<Value> decomposed = LLVM::decomposeValue(rewriter, loc, initShflValue, int32Type); SmallVector<Value> swizzled; for (Value v : decomposed) { - Value res = rewriter.create<ROCDL::DsBpermuteOp>(loc, int32Type, - dwordAlignedDstLane, v); + Value res = ROCDL::DsBpermuteOp::create(rewriter, loc, int32Type, + dwordAlignedDstLane, v); swizzled.emplace_back(res); } Value shflValue = |