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-rw-r--r--llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp9
-rw-r--r--llvm/utils/TableGen/CompressInstEmitter.cpp205
-rw-r--r--llvm/utils/TableGen/InstrInfoEmitter.cpp13
3 files changed, 104 insertions, 123 deletions
diff --git a/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp b/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
index 7f90d6b..a280604 100644
--- a/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
@@ -242,11 +242,10 @@ public:
SmallVector<const Record *, 1024> AllRuntimeLibcallImpls(
AllRuntimeLibcallImplsRaw);
- // Sort by libcall impl name, not the enum name. This keeps the order
- // suitable for using the name table for libcall recognition binary search.
- llvm::sort(AllRuntimeLibcallImpls, [](const Record *A, const Record *B) {
- return A->getValueAsString("LibCallFuncName") <
- B->getValueAsString("LibCallFuncName");
+ // Sort by libcall impl name and secondarily by the enum name.
+ sort(AllRuntimeLibcallImpls, [](const Record *A, const Record *B) {
+ return std::pair(A->getValueAsString("LibCallFuncName"), A->getName()) <
+ std::pair(B->getValueAsString("LibCallFuncName"), B->getName());
});
RuntimeLibcallImplDefList.reserve(AllRuntimeLibcallImpls.size());
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index afc892b..af119c3 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -86,16 +86,22 @@ namespace {
class CompressInstEmitter {
struct OpData {
enum MapKind { Operand, Imm, Reg } Kind;
- union {
+ // Info for an operand.
+ struct OpndInfo {
+ // Record from the Dag.
+ const Record *DagRec;
// Operand number mapped to.
- unsigned OpNo;
+ unsigned Idx;
+ // Tied operand index within the instruction.
+ int TiedOpIdx;
+ };
+ union {
+ OpndInfo OpInfo;
// Integer immediate value.
int64_t ImmVal;
// Physical register.
const Record *RegRec;
};
- // Tied operand index within the instruction.
- int TiedOpIdx = -1;
};
struct ArgData {
unsigned DAGOpNo;
@@ -217,12 +223,8 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
Inst.Operands.back().MIOperandNo + Inst.Operands.back().MINumOperands;
OperandMap.grow(NumMIOperands);
- // TiedCount keeps track of the number of operands skipped in Inst
- // operands list to get to the corresponding Dag operand. This is
- // necessary because the number of operands in Inst might be greater
- // than number of operands in the Dag due to how tied operands
- // are represented.
- unsigned TiedCount = 0;
+ // Tied operands are not represented in the DAG so we count them separately.
+ unsigned DAGOpNo = 0;
unsigned OpNo = 0;
for (const auto &Opnd : Inst.Operands) {
int TiedOpIdx = Opnd.getTiedRegister();
@@ -231,15 +233,25 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
// Set the entry in OperandMap for the tied operand we're skipping.
OperandMap[OpNo] = OperandMap[TiedOpIdx];
++OpNo;
- ++TiedCount;
+
+ // Source instructions can have at most 1 tied operand.
+ if (IsSourceInst && (OpNo - DAGOpNo > 1))
+ PrintFatalError(Rec->getLoc(),
+ "Input operands for Inst '" + Inst.TheDef->getName() +
+ "' and input Dag operand count mismatch");
+
continue;
}
- for (unsigned SubOp = 0; SubOp != Opnd.MINumOperands; ++SubOp, ++OpNo) {
- unsigned DAGOpNo = OpNo - TiedCount;
+ for (unsigned SubOp = 0; SubOp != Opnd.MINumOperands;
+ ++SubOp, ++OpNo, ++DAGOpNo) {
const Record *OpndRec = Opnd.Rec;
if (Opnd.MINumOperands > 1)
OpndRec = cast<DefInit>(Opnd.MIOperandInfo->getArg(SubOp))->getDef();
+ if (DAGOpNo >= Dag->getNumArgs())
+ PrintFatalError(Rec->getLoc(), "Inst '" + Inst.TheDef->getName() +
+ "' and Dag operand count mismatch");
+
if (const auto *DI = dyn_cast<DefInit>(Dag->getArg(DAGOpNo))) {
if (DI->getDef()->isSubClassOf("Register")) {
// Check if the fixed register belongs to the Register class.
@@ -267,9 +279,34 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
"' in the corresponding instruction operand!");
OperandMap[OpNo].Kind = OpData::Operand;
+ OperandMap[OpNo].OpInfo.DagRec = DI->getDef();
+ OperandMap[OpNo].OpInfo.TiedOpIdx = -1;
+
+ // Create a mapping between the operand name in the Dag (e.g. $rs1) and
+ // its index in the list of Dag operands and check that operands with
+ // the same name have the same type. For example in 'C_ADD $rs1, $rs2'
+ // we generate the mapping $rs1 --> 0, $rs2 ---> 1. If the operand
+ // appears twice in the same Dag (tied in the compressed instruction),
+ // we note the previous index in the TiedOpIdx field.
+ StringRef ArgName = Dag->getArgNameStr(DAGOpNo);
+ if (ArgName.empty())
+ continue;
+
+ if (IsSourceInst) {
+ auto It = Operands.find(ArgName);
+ if (It != Operands.end()) {
+ OperandMap[OpNo].OpInfo.TiedOpIdx = It->getValue().MIOpNo;
+ if (OperandMap[It->getValue().MIOpNo].OpInfo.DagRec != DI->getDef())
+ PrintFatalError(Rec->getLoc(),
+ "Input Operand '" + ArgName +
+ "' has a mismatched tied operand!");
+ }
+ }
+
+ Operands[ArgName] = {DAGOpNo, OpNo};
} else if (const auto *II = dyn_cast<IntInit>(Dag->getArg(DAGOpNo))) {
// Validate that corresponding instruction operand expects an immediate.
- if (OpndRec->isSubClassOf("RegisterClass"))
+ if (!OpndRec->isSubClassOf("Operand"))
PrintFatalError(Rec->getLoc(), "Error in Dag '" + Dag->getAsString() +
"' Found immediate: '" +
II->getAsString() +
@@ -286,69 +323,13 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
} else {
llvm_unreachable("Unhandled CompressPat argument type!");
}
-
- // Create a mapping between the operand name in the Dag (e.g. $rs1) and
- // its index in the list of Dag operands and check that operands with the
- // same name have the same type. For example in 'C_ADD $rs1, $rs2' we
- // generate the mapping $rs1 --> 0, $rs2 ---> 1. If the operand appears
- // twice in the same Dag (tied in the compressed instruction), we note
- // the previous index in the TiedOpIdx field.
- StringRef ArgName = Dag->getArgNameStr(DAGOpNo);
- if (ArgName.empty())
- continue;
-
- if (IsSourceInst) {
- auto It = Operands.find(ArgName);
- if (It != Operands.end()) {
- OperandMap[OpNo].TiedOpIdx = It->getValue().MIOpNo;
- if (!validateArgsTypes(Dag->getArg(It->getValue().DAGOpNo),
- Dag->getArg(DAGOpNo)))
- PrintFatalError(Rec->getLoc(),
- "Input Operand '" + ArgName +
- "' has a mismatched tied operand!");
- }
- }
-
- Operands[ArgName] = {DAGOpNo, OpNo};
}
}
-}
-
-// Verify the Dag operand count is enough to build an instruction.
-static bool verifyDagOpCount(const CodeGenInstruction &Inst, const DagInit *Dag,
- bool IsSource) {
- unsigned NumMIOperands = 0;
-
- unsigned TiedOpCount = 0;
- for (const auto &Op : Inst.Operands) {
- NumMIOperands += Op.MINumOperands;
- if (Op.getTiedRegister() != -1)
- TiedOpCount++;
- }
- if (Dag->getNumArgs() == NumMIOperands)
- return true;
-
- // Source instructions are non compressed instructions and have at most one
- // tied operand.
- if (IsSource && (TiedOpCount > 1))
- PrintFatalError(Inst.TheDef->getLoc(),
- "Input operands for Inst '" + Inst.TheDef->getName() +
- "' and input Dag operand count mismatch");
-
- // The Dag can't have more arguments than the Instruction.
- if (Dag->getNumArgs() > NumMIOperands)
- PrintFatalError(Inst.TheDef->getLoc(),
- "Inst '" + Inst.TheDef->getName() +
- "' and Dag operand count mismatch");
-
- // The Instruction might have tied operands so the Dag might have
- // a fewer operand count.
- if (Dag->getNumArgs() != (NumMIOperands - TiedOpCount))
- PrintFatalError(Inst.TheDef->getLoc(),
- "Inst '" + Inst.TheDef->getName() +
- "' and Dag operand count mismatch");
- return true;
+ // We shouldn't have extra Dag operands.
+ if (DAGOpNo != Dag->getNumArgs())
+ PrintFatalError(Rec->getLoc(), "Inst '" + Inst.TheDef->getName() +
+ "' and Dag operand count mismatch");
}
// Check that all names in the source DAG appear in the destionation DAG.
@@ -398,8 +379,9 @@ void CompressInstEmitter::createInstOperandMapping(
if (DestOperandMap[OpNo].Kind == OpData::Operand)
// No need to fill the SourceOperandMap here since it was mapped to
// destination operand 'TiedInstOpIdx' in a previous iteration.
- LLVM_DEBUG(dbgs() << " " << DestOperandMap[OpNo].OpNo << " ====> "
- << OpNo << " Dest operand tied with operand '"
+ LLVM_DEBUG(dbgs() << " " << DestOperandMap[OpNo].OpInfo.Idx
+ << " ====> " << OpNo
+ << " Dest operand tied with operand '"
<< TiedInstOpIdx << "'\n");
++OpNo;
continue;
@@ -424,8 +406,8 @@ void CompressInstEmitter::createInstOperandMapping(
"Incorrect operand mapping detected!\n");
unsigned SourceOpNo = SourceOp->getValue().MIOpNo;
- DestOperandMap[OpNo].OpNo = SourceOpNo;
- SourceOperandMap[SourceOpNo].OpNo = OpNo;
+ DestOperandMap[OpNo].OpInfo.Idx = SourceOpNo;
+ SourceOperandMap[SourceOpNo].OpInfo.Idx = OpNo;
LLVM_DEBUG(dbgs() << " " << SourceOpNo << " ====> " << OpNo << "\n");
}
}
@@ -463,7 +445,6 @@ void CompressInstEmitter::evaluateCompressPat(const Record *Rec) {
// Checking we are transforming from compressed to uncompressed instructions.
const Record *SourceOperator = SourceDag->getOperatorAsDef(Rec->getLoc());
CodeGenInstruction SourceInst(SourceOperator);
- verifyDagOpCount(SourceInst, SourceDag, true);
// Validate output Dag operands.
const DagInit *DestDag = Rec->getValueAsDag("Output");
@@ -472,7 +453,6 @@ void CompressInstEmitter::evaluateCompressPat(const Record *Rec) {
const Record *DestOperator = DestDag->getOperatorAsDef(Rec->getLoc());
CodeGenInstruction DestInst(DestOperator);
- verifyDagOpCount(DestInst, DestDag, false);
if (SourceOperator->getValueAsInt("Size") <=
DestOperator->getValueAsInt("Size"))
@@ -668,7 +648,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
StringRef PrevOp;
StringRef CurOp;
CaseStream << " switch (MI.getOpcode()) {\n";
- CaseStream << " default: return false;\n";
+ CaseStream << " default: return false;\n";
bool CompressOrCheck =
EType == EmitterType::Compress || EType == EmitterType::CheckCompress;
@@ -681,7 +661,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
.str()
: "";
- for (auto &CompressPat : CompressPatterns) {
+ for (const auto &CompressPat : CompressPatterns) {
if (EType == EmitterType::Uncompress && CompressPat.IsCompressOnly)
continue;
@@ -689,23 +669,25 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
std::string CodeString;
raw_string_ostream CondStream(CondString);
raw_string_ostream CodeStream(CodeString);
- CodeGenInstruction &Source =
+ const CodeGenInstruction &Source =
CompressOrCheck ? CompressPat.Source : CompressPat.Dest;
- CodeGenInstruction &Dest =
+ const CodeGenInstruction &Dest =
CompressOrCheck ? CompressPat.Dest : CompressPat.Source;
- IndexedMap<OpData> SourceOperandMap = CompressOrCheck
- ? CompressPat.SourceOperandMap
- : CompressPat.DestOperandMap;
- IndexedMap<OpData> &DestOperandMap = CompressOrCheck
- ? CompressPat.DestOperandMap
- : CompressPat.SourceOperandMap;
+ const IndexedMap<OpData> &SourceOperandMap =
+ CompressOrCheck ? CompressPat.SourceOperandMap
+ : CompressPat.DestOperandMap;
+ const IndexedMap<OpData> &DestOperandMap =
+ CompressOrCheck ? CompressPat.DestOperandMap
+ : CompressPat.SourceOperandMap;
CurOp = Source.TheDef->getName();
// Check current and previous opcode to decide to continue or end a case.
if (CurOp != PrevOp) {
- if (!PrevOp.empty())
- CaseStream.indent(6) << "break;\n } // case " + PrevOp + "\n";
- CaseStream.indent(4) << "case " + TargetName + "::" + CurOp + ": {\n";
+ if (!PrevOp.empty()) {
+ CaseStream.indent(4) << "break;\n";
+ CaseStream.indent(2) << "} // case " + PrevOp + "\n";
+ }
+ CaseStream.indent(2) << "case " + TargetName + "::" + CurOp + ": {\n";
}
std::set<std::pair<bool, StringRef>> FeaturesSet;
@@ -747,21 +729,24 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
// Start Source Inst operands validation.
unsigned OpNo = 0;
for (const auto &SourceOperand : Source.Operands) {
- if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
- if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
- CondStream.indent(8)
- << "(MI.getOperand(" << OpNo << ").isReg()) && (MI.getOperand("
- << SourceOperandMap[OpNo].TiedOpIdx << ").isReg()) &&\n"
- << indent(8) << "(MI.getOperand(" << OpNo
- << ").getReg() == MI.getOperand("
- << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
- else
- PrintFatalError("Unexpected tied operand types!");
- }
for (unsigned SubOp = 0; SubOp != SourceOperand.MINumOperands; ++SubOp) {
// Check for fixed immediates\registers in the source instruction.
switch (SourceOperandMap[OpNo].Kind) {
case OpData::Operand:
+ if (SourceOperandMap[OpNo].OpInfo.TiedOpIdx != -1) {
+ if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
+ CondStream.indent(8) << "(MI.getOperand(" << OpNo
+ << ").isReg()) && (MI.getOperand("
+ << SourceOperandMap[OpNo].OpInfo.TiedOpIdx
+ << ").isReg()) &&\n"
+ << indent(8) << "(MI.getOperand(" << OpNo
+ << ").getReg() == MI.getOperand("
+ << SourceOperandMap[OpNo].OpInfo.TiedOpIdx
+ << ").getReg()) &&\n";
+ else
+ PrintFatalError("Unexpected tied operand types!");
+ }
+
// We don't need to do anything for source instruction operand checks.
break;
case OpData::Imm:
@@ -799,7 +784,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
switch (DestOperandMap[OpNo].Kind) {
case OpData::Operand: {
- unsigned OpIdx = DestOperandMap[OpNo].OpNo;
+ unsigned OpIdx = DestOperandMap[OpNo].OpInfo.Idx;
+ DestRec = DestOperandMap[OpNo].OpInfo.DagRec;
// Check that the operand in the Source instruction fits
// the type for the Dest instruction.
if (DestRec->isSubClassOf("RegisterClass") ||
@@ -809,7 +795,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
: DestRec->getValueAsDef("RegClass");
// This is a register operand. Check the register class.
// Don't check register class if this is a tied operand, it was done
- // for the operand its tied to.
+ // for the operand it's tied to.
if (DestOperand.getTiedRegister() == -1) {
CondStream.indent(8) << "MI.getOperand(" << OpIdx << ").isReg()";
if (EType == EmitterType::CheckCompress)
@@ -855,7 +841,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
DestRec, "MCOperandPredicate");
CondStream.indent(8)
<< ValidatorName << "("
- << "MCOperand::createImm(" << DestOperandMap[OpNo].Imm
+ << "MCOperand::createImm(" << DestOperandMap[OpNo].ImmVal
<< "), STI, " << Entry << ") &&\n";
} else {
unsigned Entry =
@@ -889,9 +875,10 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
mergeCondAndCode(CaseStream, CondString, CodeString);
PrevOp = CurOp;
}
- Func << CaseString << "\n";
+ Func << CaseString;
+ Func.indent(4) << "break;\n";
// Close brace for the last case.
- Func.indent(4) << "} // case " << CurOp << "\n";
+ Func.indent(2) << "} // case " << CurOp << "\n";
Func.indent(2) << "} // switch\n";
Func.indent(2) << "return false;\n}\n";
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index f028fcd..fa38d01 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -248,9 +248,7 @@ void InstrInfoEmitter::emitOperandNameMappings(
/// scan of the instructions below.
// Map of operand names to their ID.
- std::map<StringRef, unsigned> OperandNameToID;
- // Map from operand name enum value -> ID.
- std::vector<unsigned> OperandEnumToID;
+ MapVector<StringRef, unsigned> OperandNameToID;
/// The keys of this map is a map which have OpName ID values as their keys
/// and instruction operand indices as their values. The values of this map
@@ -278,16 +276,13 @@ void InstrInfoEmitter::emitOperandNameMappings(
}
const size_t NumOperandNames = OperandNameToID.size();
- OperandEnumToID.reserve(NumOperandNames);
- for (const auto &Op : OperandNameToID)
- OperandEnumToID.push_back(Op.second);
OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
OS << "namespace llvm::" << Namespace << " {\n";
OS << "enum class OpName {\n";
- for (const auto &[I, Op] : enumerate(OperandNameToID))
- OS << " " << Op.first << " = " << I << ",\n";
+ for (const auto &[Op, I] : OperandNameToID)
+ OS << " " << Op << " = " << I << ",\n";
OS << " NUM_OPERAND_NAMES = " << NumOperandNames << ",\n";
OS << "}; // enum class OpName\n\n";
OS << "LLVM_READONLY\n";
@@ -312,7 +307,7 @@ void InstrInfoEmitter::emitOperandNameMappings(
// Emit a row of the OperandMap table.
OS << " {";
- for (unsigned ID : OperandEnumToID) {
+ for (unsigned ID = 0; ID < NumOperandNames; ++ID) {
auto Iter = OpList.find(ID);
OS << (Iter != OpList.end() ? (int)Iter->second : -1) << ", ";
}
generated by cgit v1.1 at 2025-07-27 01:47:45 +0000