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-rw-r--r--llvm/utils/TableGen/Basic/DirectiveEmitter.cpp22
-rw-r--r--llvm/utils/TableGen/Common/CodeGenRegisters.cpp30
-rw-r--r--llvm/utils/TableGen/Common/CodeGenRegisters.h4
-rw-r--r--llvm/utils/TableGen/RegisterInfoEmitter.cpp2
4 files changed, 35 insertions, 23 deletions
diff --git a/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp b/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
index 177eece..f0e2369 100644
--- a/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
@@ -106,8 +106,16 @@ static void generateEnumClass(ArrayRef<const Record *> Records, raw_ostream &OS,
bool ExportEnums) {
OS << "\n";
OS << "enum class " << Enum << " {\n";
- for (const Record *R : Records) {
- OS << " " << getIdentifierName(R, Prefix) << ",\n";
+ if (!Records.empty()) {
+ std::string N;
+ for (auto [I, R] : llvm::enumerate(Records)) {
+ N = getIdentifierName(R, Prefix);
+ OS << " " << N << ",\n";
+ // Make the sentinel names less likely to conflict with actual names...
+ if (I == 0)
+ OS << " First_ = " << N << ",\n";
+ }
+ OS << " Last_ = " << N << ",\n";
}
OS << "};\n";
OS << "\n";
@@ -282,6 +290,7 @@ static void emitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
if (DirLang.hasEnableBitmaskEnumInNamespace())
OS << "#include \"llvm/ADT/BitmaskEnum.h\"\n";
+ OS << "#include \"llvm/ADT/Sequence.h\"\n";
OS << "#include \"llvm/ADT/StringRef.h\"\n";
OS << "#include \"llvm/Frontend/Directive/Spelling.h\"\n";
OS << "#include \"llvm/Support/Compiler.h\"\n";
@@ -375,6 +384,15 @@ static void emitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
for (auto Ns : reverse(Namespaces))
OS << "} // namespace " << Ns << "\n";
+ // These specializations need to be in ::llvm.
+ for (StringRef Enum : {"Association", "Category", "Directive", "Clause"}) {
+ OS << "\n";
+ OS << "template <> struct enum_iteration_traits<"
+ << DirLang.getCppNamespace() << "::" << Enum << "> {\n";
+ OS << " static constexpr bool is_iterable = true;\n";
+ OS << "};\n";
+ }
+
OS << "} // namespace llvm\n";
OS << "#endif // LLVM_" << Lang << "_INC\n";
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index c43cc9a..28b542f 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -701,11 +701,13 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
Orders.resize(1 + AltOrders->size());
// Default allocation order always contains all registers.
+ MemberBV.resize(RegBank.getRegisters().size());
Artificial = true;
for (const Record *Element : *Elements) {
Orders[0].push_back(Element);
const CodeGenRegister *Reg = RegBank.getReg(Element);
Members.push_back(Reg);
+ MemberBV.set(CodeGenRegBank::getRegIndex(Reg));
Artificial &= Reg->Artificial;
if (!Reg->getSuperRegs().empty())
RegsWithSuperRegsTopoSigs.set(Reg->getTopoSig());
@@ -767,9 +769,11 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
RegsWithSuperRegsTopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1),
RSI(Props.RSI), CopyCost(0), Allocatable(true), AllocationPriority(0),
GlobalPriority(false), TSFlags(0) {
+ MemberBV.resize(RegBank.getRegisters().size());
Artificial = true;
GeneratePressureSet = false;
for (const auto R : Members) {
+ MemberBV.set(CodeGenRegBank::getRegIndex(R));
if (!R->getSuperRegs().empty())
RegsWithSuperRegsTopoSigs.set(R->getTopoSig());
Artificial &= R->Artificial;
@@ -833,7 +837,7 @@ bool CodeGenRegisterClass::hasType(const ValueTypeByHwMode &VT) const {
}
bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
- return llvm::binary_search(Members, Reg, deref<std::less<>>());
+ return MemberBV.test(CodeGenRegBank::getRegIndex(Reg));
}
unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank &RegBank) const {
@@ -2295,9 +2299,6 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
SRSets[I].push_back(R);
}
- for (auto I : SRSets)
- sortAndUniqueRegisters(I.second);
-
// Find matching classes for all SRSets entries. Iterate in SubRegIndex
// numerical order to visit synthetic indices last.
for (const CodeGenSubRegIndex &SubIdx : SubRegIndices) {
@@ -2332,8 +2333,7 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
CodeGenRegisterClass *RC,
std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
DenseSet<const CodeGenSubRegIndex *> ImpliedSubRegIndices;
- std::vector<std::pair<const CodeGenRegister *, const CodeGenRegister *>>
- SubToSuperRegs;
+ std::vector<const CodeGenRegister *> SubRegs;
BitVector TopoSigs(getNumTopoSigs());
// Iterate subregister indices in topological order to visit larger indices
@@ -2351,15 +2351,14 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
// Build list of (Sub, Super) pairs for this SubIdx, sorted by Sub. Note
// that the list may contain entries with the same Sub but different Supers.
- SubToSuperRegs.clear();
+ SubRegs.clear();
TopoSigs.reset();
for (const CodeGenRegister *Super : RC->getMembers()) {
const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
assert(Sub && "Missing sub-register");
- SubToSuperRegs.emplace_back(Sub, Super);
+ SubRegs.push_back(Sub);
TopoSigs.set(Sub->getTopoSig());
}
- sort(SubToSuperRegs, on_first<deref<std::less<>>>());
// Iterate over sub-register class candidates. Ignore classes created by
// this loop. They will never be useful.
@@ -2374,16 +2373,10 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
// Topological shortcut: SubRC members have the wrong shape.
if (!TopoSigs.anyCommon(SubRC.getRegsWithSuperRegsTopoSigs()))
continue;
- // Compute the subset of RC that maps into SubRC with a single linear scan
- // through SubToSuperRegs and the members of SubRC.
+ // Compute the subset of RC that maps into SubRC.
CodeGenRegister::Vec SubSetVec;
- auto SubI = SubRC.getMembers().begin(), SubE = SubRC.getMembers().end();
- for (auto &[Sub, Super] : SubToSuperRegs) {
- while (SubI != SubE && **SubI < *Sub)
- ++SubI;
- if (SubI == SubE)
- break;
- if (**SubI == *Sub)
+ for (const auto &[Sub, Super] : zip_equal(SubRegs, RC->getMembers())) {
+ if (SubRC.contains(Sub))
SubSetVec.push_back(Super);
}
@@ -2391,7 +2384,6 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
continue;
// RC injects completely into SubRC.
- sortAndUniqueRegisters(SubSetVec);
if (SubSetVec.size() == RC->getMembers().size()) {
SubRC.addSuperRegClass(SubIdx, RC);
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index bbcd44c..5e6fff0 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -315,6 +315,8 @@ inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
class CodeGenRegisterClass {
CodeGenRegister::Vec Members;
+ // Bit mask of members, indexed by getRegIndex.
+ BitVector MemberBV;
// Allocation orders. Order[0] always contains all registers in Members.
std::vector<SmallVector<const Record *, 16>> Orders;
// Bit mask of sub-classes including this, indexed by their EnumValue.
@@ -752,7 +754,7 @@ public:
CodeGenRegister *getReg(const Record *);
// Get a Register's index into the Registers array.
- unsigned getRegIndex(const CodeGenRegister *Reg) const {
+ static unsigned getRegIndex(const CodeGenRegister *Reg) {
return Reg->EnumValue - 1;
}
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 7d24c0f..2a311b7 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1644,7 +1644,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
for (const CodeGenRegister &Reg : Regs) {
const CodeGenRegisterClass *BaseRC = nullptr;
for (const CodeGenRegisterClass *RC : BaseClasses) {
- if (is_contained(RC->getMembers(), &Reg)) {
+ if (RC->contains(&Reg)) {
BaseRC = RC;
break;
}
generated by cgit v1.1 at 2025-07-17 21:19:07 +0000