diff options
Diffstat (limited to 'llvm/utils/TableGen')
-rw-r--r-- | llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp | 13 | ||||
-rw-r--r-- | llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 11 | ||||
-rw-r--r-- | llvm/utils/TableGen/Common/CodeGenRegisters.h | 2 | ||||
-rw-r--r-- | llvm/utils/TableGen/Common/CodeGenSchedule.cpp | 6 |
4 files changed, 28 insertions, 4 deletions
diff --git a/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp b/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp index 652bea9..7f90d6b 100644 --- a/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp +++ b/llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp @@ -236,8 +236,19 @@ public: for (RuntimeLibcall &LibCall : RuntimeLibcallDefList) Def2RuntimeLibcall[LibCall.getDef()] = &LibCall; - ArrayRef<const Record *> AllRuntimeLibcallImpls = + ArrayRef<const Record *> AllRuntimeLibcallImplsRaw = Records.getAllDerivedDefinitions("RuntimeLibcallImpl"); + + SmallVector<const Record *, 1024> AllRuntimeLibcallImpls( + AllRuntimeLibcallImplsRaw); + + // Sort by libcall impl name, not the enum name. This keeps the order + // suitable for using the name table for libcall recognition binary search. + llvm::sort(AllRuntimeLibcallImpls, [](const Record *A, const Record *B) { + return A->getValueAsString("LibCallFuncName") < + B->getValueAsString("LibCallFuncName"); + }); + RuntimeLibcallImplDefList.reserve(AllRuntimeLibcallImpls.size()); size_t LibCallImplEnumVal = 1; diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index 28b542f..f784279 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -30,6 +30,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TGTimer.h" #include <algorithm> #include <cassert> #include <cstdint> @@ -1130,7 +1131,7 @@ CodeGenRegisterCategory::CodeGenRegisterCategory(CodeGenRegBank &RegBank, CodeGenRegBank::CodeGenRegBank(const RecordKeeper &Records, const CodeGenHwModes &Modes) - : CGH(Modes) { + : Records(Records), CGH(Modes) { // Configure register Sets to understand register classes and tuples. Sets.addFieldExpander("RegisterClass", "MemberList"); Sets.addFieldExpander("CalleeSavedRegs", "SaveList"); @@ -2202,7 +2203,9 @@ void CodeGenRegBank::computeDerivedInfo() { // Compute a weight for each register unit created during getSubRegs. // This may create adopted register units (with unit # >= NumNativeRegUnits). + Records.getTimer().startTimer("Compute reg unit weights"); computeRegUnitWeights(); + Records.getTimer().stopTimer(); // Compute a unique set of RegUnitSets. One for each RegClass and inferred // supersets for the union of overlapping sets. @@ -2446,6 +2449,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() { // and assigned EnumValues yet. That means getSubClasses(), // getSuperClasses(), and hasSubClass() functions are defunct. + Records.getTimer().startTimer("Compute inferred register classes"); + // Use one-before-the-end so it doesn't move forward when new elements are // added. auto FirstNewRC = std::prev(RegClasses.end()); @@ -2481,6 +2486,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() { } } + Records.getTimer().startTimer("Extend super-register classes"); + // Compute the transitive closure for super-register classes. // // By iterating over sub-register indices in topological order, we only ever @@ -2491,6 +2498,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() { for (CodeGenRegisterClass &SubRC : RegClasses) SubRC.extendSuperRegClasses(SubIdx); } + + Records.getTimer().stopTimer(); } /// getRegisterClassForRegister - Find the register class that contains the diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h index 5e6fff0..81aa663 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.h +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h @@ -607,6 +607,8 @@ typedef SmallVector<unsigned, 16> TopoSigId; // CodeGenRegBank - Represent a target's registers and the relations between // them. class CodeGenRegBank { + const RecordKeeper &Records; + SetTheory Sets; const CodeGenHwModes &CGH; diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp index 50346c2..b07ea9e9 100644 --- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp @@ -2114,7 +2114,8 @@ void CodeGenSchedModels::addWriteRes(const Record *ProcWriteResDef, const Record *WRDef = ProcWriteResDef->getValueAsDef("WriteType"); if (!WRMap.try_emplace(WRDef, ProcWriteResDef).second) PrintFatalError(ProcWriteResDef->getLoc(), - "WriteType already used in another WriteRes"); + "WriteType of " + WRDef->getName() + + " already used in another WriteRes"); } // Visit ProcResourceKinds referenced by the newly discovered WriteRes. @@ -2148,7 +2149,8 @@ void CodeGenSchedModels::addReadAdvance(const Record *ProcReadAdvanceDef, const Record *RADef = ProcReadAdvanceDef->getValueAsDef("ReadType"); if (!RAMap.try_emplace(RADef, ProcReadAdvanceDef).second) PrintFatalError(ProcReadAdvanceDef->getLoc(), - "ReadType already used in another ReadAdvance"); + "ReadType of " + RADef->getName() + + " already used in another ReadAdvance"); } } |