diff options
Diffstat (limited to 'llvm/unittests/Target/AArch64')
4 files changed, 411 insertions, 9 deletions
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp index 28d69f3..c4cbd4f 100644 --- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp +++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp @@ -8,7 +8,6 @@ #include "AArch64SelectionDAGInfo.h" #include "llvm/Analysis/MemoryLocation.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" -#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/AsmParser/Parser.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/SelectionDAG.h" @@ -63,12 +62,8 @@ protected: if (!DAG) report_fatal_error("DAG?"); OptimizationRemarkEmitter ORE(F); - FunctionAnalysisManager FAM; - FAM.registerPass([&] { return TM->getTargetIRAnalysis(); }); - - TargetTransformInfo TTI = TM->getTargetIRAnalysis().run(*F, FAM); DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr, MMI, - nullptr, TTI.hasBranchDivergence(F)); + nullptr); } TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) { @@ -324,6 +319,161 @@ TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_UADDO_CARRY) { } // Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits. +// Attempt to FREEZE the MOV/MVN nodes to show that they can still be analysed. +TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_MOVI) { + SDLoc Loc; + auto IntSca32VT = MVT::i32; + auto Int8Vec8VT = MVT::v8i8; + auto Int16Vec8VT = MVT::v16i8; + auto Int4Vec16VT = MVT::v4i16; + auto Int8Vec16VT = MVT::v8i16; + auto Int2Vec32VT = MVT::v2i32; + auto Int4Vec32VT = MVT::v4i32; + auto IntVec64VT = MVT::v1i64; + auto Int2Vec64VT = MVT::v2i64; + auto N165 = DAG->getConstant(0x000000A5, Loc, IntSca32VT); + KnownBits Known; + + auto OpMOVIedit64 = DAG->getNode(AArch64ISD::MOVIedit, Loc, IntVec64VT, N165); + Known = DAG->computeKnownBits(OpMOVIedit64); + EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00)); + EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF)); + + auto OpMOVIedit128 = + DAG->getNode(AArch64ISD::MOVIedit, Loc, Int2Vec64VT, N165); + Known = DAG->computeKnownBits(OpMOVIedit128); + EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00)); + EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF)); + + auto FrMOVIedit128 = DAG->getFreeze(OpMOVIedit128); + Known = DAG->computeKnownBits(FrMOVIedit128); + EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00)); + EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF)); + + auto N264 = DAG->getConstant(264, Loc, IntSca32VT); + auto OpMOVImsl64 = + DAG->getNode(AArch64ISD::MOVImsl, Loc, Int2Vec32VT, N165, N264); + Known = DAG->computeKnownBits(OpMOVImsl64); + EXPECT_EQ(Known.Zero, APInt(32, 0xFFFF5A00)); + EXPECT_EQ(Known.One, APInt(32, 0x0000A5FF)); + + auto N272 = DAG->getConstant(272, Loc, IntSca32VT); + auto OpMOVImsl128 = + DAG->getNode(AArch64ISD::MOVImsl, Loc, Int4Vec32VT, N165, N272); + Known = DAG->computeKnownBits(OpMOVImsl128); + EXPECT_EQ(Known.Zero, APInt(32, 0xFF5A0000)); + EXPECT_EQ(Known.One, APInt(32, 0x00A5FFFF)); + + auto FrMOVImsl128 = DAG->getFreeze(OpMOVImsl128); + Known = DAG->computeKnownBits(FrMOVImsl128); + EXPECT_EQ(Known.Zero, APInt(32, 0xFF5A0000)); + EXPECT_EQ(Known.One, APInt(32, 0x00A5FFFF)); + + auto OpMVNImsl64 = + DAG->getNode(AArch64ISD::MVNImsl, Loc, Int2Vec32VT, N165, N272); + Known = DAG->computeKnownBits(OpMVNImsl64); + EXPECT_EQ(Known.Zero, APInt(32, 0x00A5FFFF)); + EXPECT_EQ(Known.One, APInt(32, 0xFF5A0000)); + + auto OpMVNImsl128 = + DAG->getNode(AArch64ISD::MVNImsl, Loc, Int4Vec32VT, N165, N264); + Known = DAG->computeKnownBits(OpMVNImsl128); + EXPECT_EQ(Known.Zero, APInt(32, 0x0000A5FF)); + EXPECT_EQ(Known.One, APInt(32, 0xFFFF5A00)); + + auto FrMVNImsl128 = DAG->getFreeze(OpMVNImsl128); + Known = DAG->computeKnownBits(FrMVNImsl128); + EXPECT_EQ(Known.Zero, APInt(32, 0x0000A5FF)); + EXPECT_EQ(Known.One, APInt(32, 0xFFFF5A00)); + + auto N0 = DAG->getConstant(0, Loc, IntSca32VT); + auto OpMOVIshift2Vec32 = + DAG->getNode(AArch64ISD::MOVIshift, Loc, Int2Vec32VT, N165, N0); + Known = DAG->computeKnownBits(OpMOVIshift2Vec32); + EXPECT_EQ(Known.Zero, APInt(32, 0xFFFFFF5A)); + EXPECT_EQ(Known.One, APInt(32, 0x000000A5)); + + auto N24 = DAG->getConstant(24, Loc, IntSca32VT); + auto OpMOVIshift4Vec32 = + DAG->getNode(AArch64ISD::MOVIshift, Loc, Int4Vec32VT, N165, N24); + Known = DAG->computeKnownBits(OpMOVIshift4Vec32); + EXPECT_EQ(Known.Zero, APInt(32, 0x5AFFFFFF)); + EXPECT_EQ(Known.One, APInt(32, 0xA5000000)); + + auto FrMOVIshift4Vec32 = DAG->getFreeze(OpMOVIshift4Vec32); + Known = DAG->computeKnownBits(FrMOVIshift4Vec32); + EXPECT_EQ(Known.Zero, APInt(32, 0x5AFFFFFF)); + EXPECT_EQ(Known.One, APInt(32, 0xA5000000)); + + auto OpMVNIshift2Vec32 = + DAG->getNode(AArch64ISD::MVNIshift, Loc, Int2Vec32VT, N165, N24); + Known = DAG->computeKnownBits(OpMVNIshift2Vec32); + EXPECT_EQ(Known.Zero, APInt(32, 0xA5000000)); + EXPECT_EQ(Known.One, APInt(32, 0x5AFFFFFF)); + + auto OpMVNIshift4Vec32 = + DAG->getNode(AArch64ISD::MVNIshift, Loc, Int4Vec32VT, N165, N0); + Known = DAG->computeKnownBits(OpMVNIshift4Vec32); + EXPECT_EQ(Known.Zero, APInt(32, 0x000000A5)); + EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF5A)); + + auto FrMVNIshift4Vec32 = DAG->getFreeze(OpMVNIshift4Vec32); + Known = DAG->computeKnownBits(FrMVNIshift4Vec32); + EXPECT_EQ(Known.Zero, APInt(32, 0x000000A5)); + EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF5A)); + + auto N8 = DAG->getConstant(8, Loc, IntSca32VT); + auto OpMOVIshift4Vec16 = + DAG->getNode(AArch64ISD::MOVIshift, Loc, Int4Vec16VT, N165, N0); + Known = DAG->computeKnownBits(OpMOVIshift4Vec16); + EXPECT_EQ(Known.Zero, APInt(16, 0xFF5A)); + EXPECT_EQ(Known.One, APInt(16, 0x00A5)); + + auto OpMOVIshift8Vec16 = + DAG->getNode(AArch64ISD::MOVIshift, Loc, Int8Vec16VT, N165, N8); + Known = DAG->computeKnownBits(OpMOVIshift8Vec16); + EXPECT_EQ(Known.Zero, APInt(16, 0x5AFF)); + EXPECT_EQ(Known.One, APInt(16, 0xA500)); + + auto FrMOVIshift8Vec16 = DAG->getFreeze(OpMOVIshift8Vec16); + Known = DAG->computeKnownBits(FrMOVIshift8Vec16); + EXPECT_EQ(Known.Zero, APInt(16, 0x5AFF)); + EXPECT_EQ(Known.One, APInt(16, 0xA500)); + + auto OpMVNIshift4Vec16 = + DAG->getNode(AArch64ISD::MVNIshift, Loc, Int4Vec16VT, N165, N8); + Known = DAG->computeKnownBits(OpMVNIshift4Vec16); + EXPECT_EQ(Known.Zero, APInt(16, 0xA500)); + EXPECT_EQ(Known.One, APInt(16, 0x5AFF)); + + auto OpMVNIshift8Vec16 = + DAG->getNode(AArch64ISD::MVNIshift, Loc, Int8Vec16VT, N165, N0); + Known = DAG->computeKnownBits(OpMVNIshift8Vec16); + EXPECT_EQ(Known.Zero, APInt(16, 0x00A5)); + EXPECT_EQ(Known.One, APInt(16, 0xFF5A)); + + auto FrMVNIshift8Vec16 = DAG->getFreeze(OpMVNIshift8Vec16); + Known = DAG->computeKnownBits(FrMVNIshift8Vec16); + EXPECT_EQ(Known.Zero, APInt(16, 0x00A5)); + EXPECT_EQ(Known.One, APInt(16, 0xFF5A)); + + auto OpMOVI8Vec8 = DAG->getNode(AArch64ISD::MOVI, Loc, Int8Vec8VT, N165); + Known = DAG->computeKnownBits(OpMOVI8Vec8); + EXPECT_EQ(Known.Zero, APInt(8, 0x5A)); + EXPECT_EQ(Known.One, APInt(8, 0xA5)); + + auto OpMOVI16Vec8 = DAG->getNode(AArch64ISD::MOVI, Loc, Int16Vec8VT, N165); + Known = DAG->computeKnownBits(OpMOVI16Vec8); + EXPECT_EQ(Known.Zero, APInt(8, 0x5A)); + EXPECT_EQ(Known.One, APInt(8, 0xA5)); + + auto FrMOVI16Vec8 = DAG->getFreeze(OpMOVI16Vec8); + Known = DAG->computeKnownBits(FrMOVI16Vec8); + EXPECT_EQ(Known.Zero, APInt(8, 0x5A)); + EXPECT_EQ(Known.One, APInt(8, 0xA5)); +} + +// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits. TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) { SDLoc Loc; auto IntVT = EVT::getIntegerVT(Context, 8); @@ -396,6 +546,66 @@ TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_USUBO_CARRY) { EXPECT_EQ(Known.One, APInt(8, 0x31)); } +// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits. +TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_VASHR) { + SDLoc Loc; + KnownBits Known; + auto VecVT = MVT::v8i8; + auto Shift0 = DAG->getConstant(4, Loc, MVT::i32); + auto Vec0 = DAG->getConstant(0x80, Loc, VecVT); + auto Op0 = DAG->getNode(AArch64ISD::VASHR, Loc, VecVT, Vec0, Shift0); + Known = DAG->computeKnownBits(Op0); + EXPECT_EQ(Known.Zero, APInt(8, 0x07)); + EXPECT_EQ(Known.One, APInt(8, 0xF8)); + + auto Shift1 = DAG->getConstant(7, Loc, MVT::i32); + auto Vec1 = DAG->getConstant(0xF7, Loc, VecVT); + auto Op1 = DAG->getNode(AArch64ISD::VASHR, Loc, VecVT, Vec1, Shift1); + Known = DAG->computeKnownBits(Op1); + EXPECT_EQ(Known.Zero, APInt(8, 0x00)); + EXPECT_EQ(Known.One, APInt(8, 0xFF)); +} + +// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits. +TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_VLSHR) { + SDLoc Loc; + KnownBits Known; + auto VecVT = MVT::v8i8; + auto Shift0 = DAG->getConstant(4, Loc, MVT::i32); + auto Vec0 = DAG->getConstant(0x80, Loc, VecVT); + auto Op0 = DAG->getNode(AArch64ISD::VLSHR, Loc, VecVT, Vec0, Shift0); + Known = DAG->computeKnownBits(Op0); + EXPECT_EQ(Known.Zero, APInt(8, 0xF7)); + EXPECT_EQ(Known.One, APInt(8, 0x08)); + + auto Shift1 = DAG->getConstant(7, Loc, MVT::i32); + auto Vec1 = DAG->getConstant(0xF7, Loc, VecVT); + auto Op1 = DAG->getNode(AArch64ISD::VLSHR, Loc, VecVT, Vec1, Shift1); + Known = DAG->computeKnownBits(Op1); + EXPECT_EQ(Known.Zero, APInt(8, 0xFE)); + EXPECT_EQ(Known.One, APInt(8, 0x1)); +} + +// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits. +TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_VSHL) { + SDLoc Loc; + KnownBits Known; + auto VecVT = MVT::v8i8; + auto Shift0 = DAG->getConstant(4, Loc, MVT::i32); + auto Vec0 = DAG->getConstant(0x02, Loc, VecVT); + auto Op0 = DAG->getNode(AArch64ISD::VSHL, Loc, VecVT, Vec0, Shift0); + Known = DAG->computeKnownBits(Op0); + EXPECT_EQ(Known.Zero, APInt(8, 0xDF)); + EXPECT_EQ(Known.One, APInt(8, 0x20)); + + auto Shift1 = DAG->getConstant(7, Loc, MVT::i32); + auto Vec1 = DAG->getConstant(0xF7, Loc, VecVT); + auto Op1 = DAG->getNode(AArch64ISD::VSHL, Loc, VecVT, Vec1, Shift1); + Known = DAG->computeKnownBits(Op1); + EXPECT_EQ(Known.Zero, APInt(8, 0x7F)); + EXPECT_EQ(Known.One, APInt(8, 0x80)); +} + TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) { TargetLowering TL(*TM); diff --git a/llvm/unittests/Target/AArch64/CMakeLists.txt b/llvm/unittests/Target/AArch64/CMakeLists.txt index 9387ca9..3875163 100644 --- a/llvm/unittests/Target/AArch64/CMakeLists.txt +++ b/llvm/unittests/Target/AArch64/CMakeLists.txt @@ -34,4 +34,5 @@ add_llvm_target_unittest(AArch64Tests AArch64SVESchedPseudoTest.cpp AArch64SelectionDAGTest.cpp Immediates.cpp + MCInstrAnalysisTest.cpp ) diff --git a/llvm/unittests/Target/AArch64/MCInstrAnalysisTest.cpp b/llvm/unittests/Target/AArch64/MCInstrAnalysisTest.cpp new file mode 100644 index 0000000..271d19e --- /dev/null +++ b/llvm/unittests/Target/AArch64/MCInstrAnalysisTest.cpp @@ -0,0 +1,191 @@ +//===- MCInstrAnalysisTest.cpp - AArch64MCInstrAnalysis unit tests --------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCInstrAnalysis.h" +#include "MCTargetDesc/AArch64MCTargetDesc.h" +#include "Utils/AArch64BaseInfo.h" +#include "llvm/MC/MCInstBuilder.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" + +#include "gtest/gtest.h" + +#include <memory> + +using namespace llvm; + +namespace { + +class InstrAnalysisTest : public testing::TestWithParam<const char *> { +protected: + std::unique_ptr<const MCInstrInfo> Info; + std::unique_ptr<const MCInstrAnalysis> Analysis; + + static void SetUpTestSuite() { + LLVMInitializeAArch64TargetInfo(); + LLVMInitializeAArch64Target(); + LLVMInitializeAArch64TargetMC(); + } + + InstrAnalysisTest() { + std::string Error; + const Target *TheTarget = + TargetRegistry::lookupTarget(Triple::normalize(GetParam()), Error); + Info = std::unique_ptr<const MCInstrInfo>(TheTarget->createMCInstrInfo()); + Analysis = std::unique_ptr<const MCInstrAnalysis>( + TheTarget->createMCInstrAnalysis(Info.get())); + } +}; + +} // namespace + +static MCInst beq() { + return MCInstBuilder(AArch64::Bcc).addImm(AArch64CC::EQ).addReg(AArch64::X0); +} +static MCInst tbz(unsigned Rt = AArch64::X0, unsigned Imm = 0, + unsigned Label = 32) { + return MCInstBuilder(AArch64::TBZX).addReg(Rt).addImm(Imm).addImm(Label); +} +static MCInst cbz(unsigned Rt = AArch64::X0, unsigned Label = 32) { + return MCInstBuilder(AArch64::CBZX).addReg(Rt).addImm(Label); +} +static MCInst b() { return MCInstBuilder(AArch64::B).addImm(32); } +static MCInst bl() { return MCInstBuilder(AArch64::BL).addImm(32); } +static MCInst br(unsigned Rn = AArch64::X0) { + return MCInstBuilder(AArch64::BR).addReg(Rn); +} +static MCInst blr(unsigned Rn = AArch64::X0) { + return MCInstBuilder(AArch64::BLR).addReg(Rn); +} +static MCInst ret(unsigned Rn = AArch64::LR) { + return MCInstBuilder(AArch64::RET).addReg(Rn); +} +static MCInst retaa() { return MCInstBuilder(AArch64::RETAA); } +static MCInst eret() { return MCInstBuilder(AArch64::ERET); } +static MCInst hlt() { return MCInstBuilder(AArch64::HLT); } +static MCInst brk() { return MCInstBuilder(AArch64::BRK); } +static MCInst svc() { return MCInstBuilder(AArch64::SVC); } +static MCInst hvc() { return MCInstBuilder(AArch64::HVC); } +static MCInst smc() { return MCInstBuilder(AArch64::SMC); } + +TEST_P(InstrAnalysisTest, IsTerminator) { + EXPECT_TRUE(Analysis->isTerminator(beq())); + EXPECT_TRUE(Analysis->isTerminator(tbz())); + EXPECT_TRUE(Analysis->isTerminator(cbz())); + EXPECT_TRUE(Analysis->isTerminator(b())); + EXPECT_FALSE(Analysis->isTerminator(bl())); + EXPECT_FALSE(Analysis->isTerminator(blr())); + EXPECT_TRUE(Analysis->isTerminator(br())); + EXPECT_TRUE(Analysis->isTerminator(ret())); + EXPECT_TRUE(Analysis->isTerminator(retaa())); + EXPECT_TRUE(Analysis->isTerminator(eret())); + EXPECT_FALSE(Analysis->isTerminator(hlt())); + EXPECT_FALSE(Analysis->isTerminator(brk())); + EXPECT_FALSE(Analysis->isTerminator(svc())); + EXPECT_FALSE(Analysis->isTerminator(hvc())); + EXPECT_FALSE(Analysis->isTerminator(smc())); +} + +TEST_P(InstrAnalysisTest, IsBarrier) { + EXPECT_FALSE(Analysis->isBarrier(beq())); + EXPECT_FALSE(Analysis->isBarrier(tbz())); + EXPECT_FALSE(Analysis->isBarrier(cbz())); + EXPECT_TRUE(Analysis->isBarrier(b())); + EXPECT_FALSE(Analysis->isBarrier(bl())); + EXPECT_FALSE(Analysis->isBarrier(blr())); + EXPECT_TRUE(Analysis->isBarrier(br())); + EXPECT_TRUE(Analysis->isBarrier(ret())); + EXPECT_TRUE(Analysis->isBarrier(retaa())); + EXPECT_TRUE(Analysis->isBarrier(eret())); + EXPECT_FALSE(Analysis->isBarrier(hlt())); + EXPECT_FALSE(Analysis->isBarrier(brk())); + EXPECT_FALSE(Analysis->isBarrier(svc())); + EXPECT_FALSE(Analysis->isBarrier(hvc())); + EXPECT_FALSE(Analysis->isBarrier(smc())); +} + +TEST_P(InstrAnalysisTest, IsCall) { + EXPECT_FALSE(Analysis->isCall(beq())); + EXPECT_FALSE(Analysis->isCall(tbz())); + EXPECT_FALSE(Analysis->isCall(cbz())); + EXPECT_FALSE(Analysis->isCall(b())); + EXPECT_TRUE(Analysis->isCall(bl())); + EXPECT_TRUE(Analysis->isCall(blr())); + EXPECT_FALSE(Analysis->isCall(br())); + EXPECT_FALSE(Analysis->isCall(ret())); + EXPECT_FALSE(Analysis->isCall(retaa())); + EXPECT_FALSE(Analysis->isCall(eret())); +} + +TEST_P(InstrAnalysisTest, IsReturn) { + EXPECT_FALSE(Analysis->isReturn(beq())); + EXPECT_FALSE(Analysis->isReturn(tbz())); + EXPECT_FALSE(Analysis->isReturn(cbz())); + EXPECT_FALSE(Analysis->isReturn(b())); + EXPECT_FALSE(Analysis->isReturn(bl())); + EXPECT_FALSE(Analysis->isReturn(br())); + EXPECT_FALSE(Analysis->isReturn(blr())); + EXPECT_FALSE(Analysis->isReturn(br(AArch64::LR))); + EXPECT_TRUE(Analysis->isReturn(ret())); + EXPECT_TRUE(Analysis->isReturn(retaa())); + EXPECT_TRUE(Analysis->isReturn(eret())); +} + +TEST_P(InstrAnalysisTest, IsBranch) { + EXPECT_TRUE(Analysis->isBranch(beq())); + EXPECT_TRUE(Analysis->isBranch(tbz())); + EXPECT_TRUE(Analysis->isBranch(cbz())); + EXPECT_TRUE(Analysis->isBranch(b())); + EXPECT_FALSE(Analysis->isBranch(bl())); + EXPECT_FALSE(Analysis->isBranch(blr())); + EXPECT_TRUE(Analysis->isBranch(br())); + EXPECT_FALSE(Analysis->isBranch(ret())); + EXPECT_FALSE(Analysis->isBranch(retaa())); + EXPECT_FALSE(Analysis->isBranch(eret())); +} + +TEST_P(InstrAnalysisTest, IsConditionalBranch) { + EXPECT_TRUE(Analysis->isConditionalBranch(beq())); + EXPECT_TRUE(Analysis->isConditionalBranch(tbz())); + EXPECT_TRUE(Analysis->isConditionalBranch(cbz())); + EXPECT_FALSE(Analysis->isConditionalBranch(b())); + EXPECT_FALSE(Analysis->isConditionalBranch(bl())); + EXPECT_FALSE(Analysis->isConditionalBranch(blr())); + EXPECT_FALSE(Analysis->isConditionalBranch(ret())); + EXPECT_FALSE(Analysis->isConditionalBranch(retaa())); + EXPECT_FALSE(Analysis->isConditionalBranch(eret())); +} + +TEST_P(InstrAnalysisTest, IsUnconditionalBranch) { + EXPECT_FALSE(Analysis->isUnconditionalBranch(beq())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(tbz())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(cbz())); + EXPECT_TRUE(Analysis->isUnconditionalBranch(b())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(bl())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(blr())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(br())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(ret())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(retaa())); + EXPECT_FALSE(Analysis->isUnconditionalBranch(eret())); +} + +TEST_P(InstrAnalysisTest, IsIndirectBranch) { + EXPECT_FALSE(Analysis->isIndirectBranch(beq())); + EXPECT_FALSE(Analysis->isIndirectBranch(tbz())); + EXPECT_FALSE(Analysis->isIndirectBranch(cbz())); + EXPECT_FALSE(Analysis->isIndirectBranch(b())); + EXPECT_FALSE(Analysis->isIndirectBranch(bl())); + EXPECT_FALSE(Analysis->isIndirectBranch(blr())); + EXPECT_TRUE(Analysis->isIndirectBranch(br())); + EXPECT_FALSE(Analysis->isIndirectBranch(ret())); + EXPECT_FALSE(Analysis->isIndirectBranch(retaa())); + EXPECT_FALSE(Analysis->isIndirectBranch(eret())); +} + +INSTANTIATE_TEST_SUITE_P(AArch64, InstrAnalysisTest, + testing::Values("aarch64")); diff --git a/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp b/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp index f13252f..bd0e53c 100644 --- a/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp +++ b/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp @@ -78,7 +78,7 @@ TEST(SMEAttributes, Constructors) { "ret void\n}"); CallBase &Call = cast<CallBase>((CallModule->getFunction("foo")->begin()->front())); - ASSERT_TRUE(SMECallAttrs(Call).callsite().hasUndefZT0()); + ASSERT_TRUE(SMECallAttrs(Call, nullptr).callsite().hasUndefZT0()); // Invalid combinations. EXPECT_DEBUG_DEATH(SA(SA::SM_Enabled | SA::SM_Compatible), @@ -309,7 +309,7 @@ TEST(SMEAttributes, Transitions) { // Shared ZA -> Private ZA Interface ASSERT_FALSE(CA(ZA_Shared, Private_ZA).requiresDisablingZABeforeCall()); - ASSERT_TRUE(CA(ZA_Shared, Private_ZA).requiresEnablingZAAfterCall()); + ASSERT_FALSE(CA(ZA_Shared, Private_ZA).requiresEnablingZAAfterCall()); // Shared ZT0 -> Private ZA Interface ASSERT_TRUE(CA(ZT0_Shared, Private_ZA).requiresDisablingZABeforeCall()); @@ -328,7 +328,7 @@ TEST(SMEAttributes, Transitions) { // Shared ZA & ZT0 -> Private ZA Interface ASSERT_FALSE(CA(ZA_ZT0_Shared, Private_ZA).requiresDisablingZABeforeCall()); ASSERT_TRUE(CA(ZA_ZT0_Shared, Private_ZA).requiresPreservingZT0()); - ASSERT_TRUE(CA(ZA_ZT0_Shared, Private_ZA).requiresEnablingZAAfterCall()); + ASSERT_FALSE(CA(ZA_ZT0_Shared, Private_ZA).requiresEnablingZAAfterCall()); // Shared ZA -> Shared ZA Interface ASSERT_FALSE(CA(ZA_Shared, ZT0_Shared).requiresDisablingZABeforeCall()); |