diff options
Diffstat (limited to 'llvm/test/tools')
87 files changed, 5875 insertions, 1641 deletions
diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected index 5751738..65904d1 100644 --- a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected @@ -72,12 +72,12 @@ define void @ldist(i1 %cond, ptr %A, ptr %B, ptr %C) { ; CHECK-NEXT: LDist: Partition 0: ; CHECK-NEXT: for.body.ldist1: ; preds = %if.end.ldist1, %for.body.ph.ldist1 ; CHECK-NEXT: %iv.ldist1 = phi i16 [ 0, %for.body.ph.ldist1 ], [ %iv.next.ldist1, %if.end.ldist1 ] -; CHECK-NEXT: %lv.ldist1 = load i16, ptr %A, align 1, !alias.scope !0, !noalias !3 -; CHECK-NEXT: store i16 %lv.ldist1, ptr %A, align 1, !alias.scope !0, !noalias !3 +; CHECK-NEXT: %lv.ldist1 = load i16, ptr %A, align 1, !alias.scope !2, !noalias !5 +; CHECK-NEXT: store i16 %lv.ldist1, ptr %A, align 1, !alias.scope !2, !noalias !5 ; CHECK-NEXT: br i1 %cond, label %if.then.ldist1, label %if.end.ldist1 ; CHECK-EMPTY: ; CHECK-NEXT: if.then.ldist1: ; preds = %for.body.ldist1 -; CHECK-NEXT: %lv2.ldist1 = load i16, ptr %A, align 1, !alias.scope !0, !noalias !3 +; CHECK-NEXT: %lv2.ldist1 = load i16, ptr %A, align 1, !alias.scope !2, !noalias !5 ; CHECK-NEXT: br label %if.end.ldist1 ; CHECK-EMPTY: ; CHECK-NEXT: if.end.ldist1: ; preds = %if.then.ldist1, %for.body.ldist1 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected index e1da112..c368a1c 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected @@ -6,8 +6,8 @@ define dso_local void @caller_St8x4(ptr nocapture noundef readonly byval(%struct.St8x4) align 8 %in, ptr nocapture noundef writeonly %ret) { ; CHECK-LABEL: caller_St8x4( ; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<13>; +; CHECK-NEXT: .reg .b32 %r<2>; +; CHECK-NEXT: .reg .b64 %rd<9>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: { // callseq 0, 0 @@ -23,11 +23,11 @@ define dso_local void @caller_St8x4(ptr nocapture noundef readonly byval(%struct ; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [retval0]; ; CHECK-NEXT: ld.param.v2.b64 {%rd7, %rd8}, [retval0+16]; ; CHECK-NEXT: } // callseq 0 -; CHECK-NEXT: ld.param.b32 %r2, [caller_St8x4_param_1]; -; CHECK-NEXT: st.b64 [%r2], %rd5; -; CHECK-NEXT: st.b64 [%r2+8], %rd6; -; CHECK-NEXT: st.b64 [%r2+16], %rd7; -; CHECK-NEXT: st.b64 [%r2+24], %rd8; +; CHECK-NEXT: ld.param.b32 %r1, [caller_St8x4_param_1]; +; CHECK-NEXT: st.b64 [%r1], %rd5; +; CHECK-NEXT: st.b64 [%r1+8], %rd6; +; CHECK-NEXT: st.b64 [%r1+16], %rd7; +; CHECK-NEXT: st.b64 [%r1+24], %rd8; ; CHECK-NEXT: ret; %call = tail call fastcc [4 x i64] @callee_St8x4(ptr noundef nonnull byval(%struct.St8x4) align 8 %in) #2 %.fca.0.extract = extractvalue [4 x i64] %call, 0 @@ -48,7 +48,6 @@ define internal fastcc [4 x i64] @callee_St8x4(ptr nocapture noundef readonly by ; CHECK-LABEL: callee_St8x4( ; CHECK: // @callee_St8x4 ; CHECK-NEXT: { -; CHECK-NEXT: .reg .b32 %r<2>; ; CHECK-NEXT: .reg .b64 %rd<5>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/target-triple-mismatch.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/target-triple-mismatch.ll new file mode 100644 index 0000000..3da27cb --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/target-triple-mismatch.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s + +define i64 @foo(i64 %a) { +entry: + %b = add i64 %a, 1 + ret i64 %b +} diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/target-triple-mismatch.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/target-triple-mismatch.test new file mode 100644 index 0000000..3bbf14d --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/target-triple-mismatch.test @@ -0,0 +1,11 @@ +# REQUIRES: aarch64-registered-target +## Check that arm64-apple-darwin target triple is wrongly captured as arm64 (non-Apple) + +# RUN: cp -f %S/Inputs/target-triple-mismatch.ll %t.ll +# RUN: %update_llc_test_checks %t.ll 2>&1 | FileCheck %s --check-prefix=LOG +# RUN: FileCheck --input-file=%t.ll %s --check-prefix=AUTOGEN + +# LOG: WARNING: Couldn't match any function. Possibly the wrong target triple has been provided + +# AUTOGEN: ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +# AUTOGEN-NEXT: ; CHECK: {{.*}} diff --git a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir index ef66327..3b03b13 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir +++ b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir @@ -51,8 +51,8 @@ frameInfo: hasMustTailInVarArgFunc: false hasTailCall: false localFrameSize: 0 - savePoint: '' - restorePoint: '' + savePoint: [] + restorePoint: [] fixedStack: [] stack: [] callSites: [] diff --git a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected index f4027c1..4b7a710 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected @@ -52,8 +52,8 @@ frameInfo: hasMustTailInVarArgFunc: false hasTailCall: false localFrameSize: 0 - savePoint: '' - restorePoint: '' + savePoint: [] + restorePoint: [] fixedStack: [] stack: [] callSites: [] diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll index 96ff2d7..ef60118 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll @@ -14,7 +14,7 @@ entry: #dbg_assign(i1 undef, !13, !DIExpression(), !16, ptr %A.addr, !DIExpression(), !17) store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !13, !DIExpression(), !17) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !22 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !22 #dbg_declare(ptr %i, !14, !DIExpression(), !23) store i32 0, ptr %i, align 4, !dbg !23, !tbaa !24 br label %for.cond, !dbg !22 @@ -27,7 +27,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !31, !prof !32 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !33 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !33 br label %for.end for.body: ; preds = %for.cond @@ -49,10 +49,10 @@ for.end: ; preds = %for.cond.cleanup } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.start.p0(ptr nocapture) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.end.p0(ptr nocapture) #1 ; Function Attrs: nounwind uwtable define dso_local void @bar(ptr %A) #0 !dbg !41 { @@ -61,7 +61,7 @@ entry: %i = alloca i32, align 4 store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !43, !DIExpression(), !46) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !47 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !47 #dbg_declare(ptr %i, !44, !DIExpression(), !48) store i32 0, ptr %i, align 4, !dbg !48, !tbaa !24 br label %for.cond, !dbg !47 @@ -74,7 +74,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !54 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !55 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !55 br label %for.end for.body: ; preds = %for.cond diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected index 6504830..4bae52e 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected @@ -16,7 +16,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: #dbg_assign(i1 undef, [[META13:![0-9]+]], !DIExpression(), [[DIASSIGNID16]], ptr [[A_ADDR]], !DIExpression(), [[META17:![0-9]+]]) ; CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META13]], !DIExpression(), [[META17]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META14:![0-9]+]], !DIExpression(), [[META23:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META23]], !tbaa [[TBAA24:![0-9]+]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG22]] @@ -27,7 +27,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG30:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG31:![0-9]+]], !prof [[PROF32:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]], !tbaa [[TBAA18]] @@ -50,7 +50,7 @@ entry: #dbg_assign(i1 undef, !13, !DIExpression(), !16, ptr %A.addr, !DIExpression(), !17) store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !13, !DIExpression(), !17) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !22 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !22 #dbg_declare(ptr %i, !14, !DIExpression(), !23) store i32 0, ptr %i, align 4, !dbg !23, !tbaa !24 br label %for.cond, !dbg !22 @@ -63,7 +63,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !31, !prof !32 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !33 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !33 br label %for.end for.body: ; preds = %for.cond @@ -85,10 +85,10 @@ for.end: ; preds = %for.cond.cleanup } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.start.p0(ptr nocapture) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.end.p0(ptr nocapture) #1 ; Function Attrs: nounwind uwtable define dso_local void @bar(ptr %A) #0 !dbg !41 { @@ -98,7 +98,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 ; CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META43:![0-9]+]], !DIExpression(), [[META46:![0-9]+]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META44:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META48]], !tbaa [[TBAA24]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47]] @@ -109,7 +109,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG53:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG54:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG56:![0-9]+]], !tbaa [[TBAA18]] @@ -131,7 +131,7 @@ entry: %i = alloca i32, align 4 store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !43, !DIExpression(), !46) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !47 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !47 #dbg_declare(ptr %i, !44, !DIExpression(), !48) store i32 0, ptr %i, align 4, !dbg !48, !tbaa !24 br label %for.cond, !dbg !47 @@ -144,7 +144,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !54 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !55 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !55 br label %for.end for.body: ; preds = %for.cond diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected index 7c1ea5e..12c6e4e 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected @@ -17,7 +17,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: #dbg_assign(i1 undef, [[META13:![0-9]+]], !DIExpression(), [[DIASSIGNID16]], ptr [[A_ADDR]], !DIExpression(), [[META17:![0-9]+]]) ; CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META13]], !DIExpression(), [[META17]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META14:![0-9]+]], !DIExpression(), [[META23:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META23]], !tbaa [[TBAA24:![0-9]+]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG22]] @@ -28,7 +28,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG30:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG31:![0-9]+]], !prof [[PROF32:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]], !tbaa [[TBAA18]] @@ -51,7 +51,7 @@ entry: #dbg_assign(i1 undef, !13, !DIExpression(), !16, ptr %A.addr, !DIExpression(), !17) store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !13, !DIExpression(), !17) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !22 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !22 #dbg_declare(ptr %i, !14, !DIExpression(), !23) store i32 0, ptr %i, align 4, !dbg !23, !tbaa !24 br label %for.cond, !dbg !22 @@ -64,7 +64,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !31, !prof !32 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !33 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !33 br label %for.end for.body: ; preds = %for.cond @@ -86,10 +86,10 @@ for.end: ; preds = %for.cond.cleanup } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.start.p0(ptr nocapture) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.end.p0(ptr nocapture) #1 ; Function Attrs: nounwind uwtable define dso_local void @bar(ptr %A) #0 !dbg !41 { @@ -100,7 +100,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 ; CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META43:![0-9]+]], !DIExpression(), [[META46:![0-9]+]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META44:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META48]], !tbaa [[TBAA24]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47]] @@ -111,7 +111,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG53:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG54:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG56:![0-9]+]], !tbaa [[TBAA18]] @@ -133,7 +133,7 @@ entry: %i = alloca i32, align 4 store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !43, !DIExpression(), !46) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !47 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !47 #dbg_declare(ptr %i, !44, !DIExpression(), !48) store i32 0, ptr %i, align 4, !dbg !48, !tbaa !24 br label %for.cond, !dbg !47 @@ -146,7 +146,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !54 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !55 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !55 br label %for.end for.body: ; preds = %for.cond diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected index 94af952..d67a303 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected @@ -17,7 +17,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: #dbg_assign(i1 undef, [[META13:![0-9]+]], !DIExpression(), [[DIASSIGNID16]], ptr [[A_ADDR]], !DIExpression(), [[META17:![0-9]+]]) ; CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META13]], !DIExpression(), [[META17]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META14:![0-9]+]], !DIExpression(), [[META23:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META23]], !tbaa [[TBAA24:![0-9]+]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG22]] @@ -28,7 +28,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG30:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG31:![0-9]+]], !prof [[PROF32:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]], !tbaa [[TBAA18]] @@ -51,7 +51,7 @@ entry: #dbg_assign(i1 undef, !13, !DIExpression(), !16, ptr %A.addr, !DIExpression(), !17) store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !13, !DIExpression(), !17) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !22 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !22 #dbg_declare(ptr %i, !14, !DIExpression(), !23) store i32 0, ptr %i, align 4, !dbg !23, !tbaa !24 br label %for.cond, !dbg !22 @@ -64,7 +64,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !31, !prof !32 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !33 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !33 br label %for.end for.body: ; preds = %for.cond @@ -86,10 +86,10 @@ for.end: ; preds = %for.cond.cleanup } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.start.p0(ptr nocapture) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.end.p0(ptr nocapture) #1 ; Function Attrs: nounwind uwtable define dso_local void @bar(ptr %A) #0 !dbg !41 { @@ -100,7 +100,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 ; CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META43:![0-9]+]], !DIExpression(), [[META46:![0-9]+]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META44:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META48]], !tbaa [[TBAA24]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47]] @@ -111,7 +111,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG53:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG54:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG56:![0-9]+]], !tbaa [[TBAA18]] @@ -133,7 +133,7 @@ entry: %i = alloca i32, align 4 store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !43, !DIExpression(), !46) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !47 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !47 #dbg_declare(ptr %i, !44, !DIExpression(), !48) store i32 0, ptr %i, align 4, !dbg !48, !tbaa !24 br label %for.cond, !dbg !47 @@ -146,7 +146,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !54 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !55 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !55 br label %for.end for.body: ; preds = %for.cond diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected index 6504830..4bae52e 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected @@ -16,7 +16,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: #dbg_assign(i1 undef, [[META13:![0-9]+]], !DIExpression(), [[DIASSIGNID16]], ptr [[A_ADDR]], !DIExpression(), [[META17:![0-9]+]]) ; CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META13]], !DIExpression(), [[META17]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META14:![0-9]+]], !DIExpression(), [[META23:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META23]], !tbaa [[TBAA24:![0-9]+]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG22]] @@ -27,7 +27,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG30:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG31:![0-9]+]], !prof [[PROF32:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]], !tbaa [[TBAA18]] @@ -50,7 +50,7 @@ entry: #dbg_assign(i1 undef, !13, !DIExpression(), !16, ptr %A.addr, !DIExpression(), !17) store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !13, !DIExpression(), !17) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !22 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !22 #dbg_declare(ptr %i, !14, !DIExpression(), !23) store i32 0, ptr %i, align 4, !dbg !23, !tbaa !24 br label %for.cond, !dbg !22 @@ -63,7 +63,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !31, !prof !32 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !33 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !33 br label %for.end for.body: ; preds = %for.cond @@ -85,10 +85,10 @@ for.end: ; preds = %for.cond.cleanup } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.start.p0(ptr nocapture) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.end.p0(ptr nocapture) #1 ; Function Attrs: nounwind uwtable define dso_local void @bar(ptr %A) #0 !dbg !41 { @@ -98,7 +98,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 ; CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META43:![0-9]+]], !DIExpression(), [[META46:![0-9]+]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META44:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META48]], !tbaa [[TBAA24]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47]] @@ -109,7 +109,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG53:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG54:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG56:![0-9]+]], !tbaa [[TBAA18]] @@ -131,7 +131,7 @@ entry: %i = alloca i32, align 4 store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !43, !DIExpression(), !46) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !47 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !47 #dbg_declare(ptr %i, !44, !DIExpression(), !48) store i32 0, ptr %i, align 4, !dbg !48, !tbaa !24 br label %for.cond, !dbg !47 @@ -144,7 +144,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !54 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !55 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !55 br label %for.end for.body: ; preds = %for.cond diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected index a656c4ae..fb3a76f 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected @@ -16,7 +16,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: #dbg_assign(i1 undef, [[META13:![0-9]+]], !DIExpression(), [[DIASSIGNID16]], ptr [[A_ADDR]], !DIExpression(), [[META17:![0-9]+]]) ; CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META13]], !DIExpression(), [[META17]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2:[0-9]+]], !dbg [[DBG22:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META14:![0-9]+]], !DIExpression(), [[META23:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META23]], !tbaa [[TBAA24:![0-9]+]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG22]] @@ -27,7 +27,7 @@ define dso_local void @foo(ptr %A) #0 !dbg !7 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG30:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG31:![0-9]+]], !prof [[PROF32:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG33:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]], !tbaa [[TBAA18]] @@ -50,7 +50,7 @@ entry: #dbg_assign(i1 undef, !13, !DIExpression(), !16, ptr %A.addr, !DIExpression(), !17) store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !13, !DIExpression(), !17) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !22 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !22 #dbg_declare(ptr %i, !14, !DIExpression(), !23) store i32 0, ptr %i, align 4, !dbg !23, !tbaa !24 br label %for.cond, !dbg !22 @@ -63,7 +63,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !31, !prof !32 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !33 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !33 br label %for.end for.body: ; preds = %for.cond @@ -85,10 +85,10 @@ for.end: ; preds = %for.cond.cleanup } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.start.p0(ptr nocapture) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.lifetime.end.p0(ptr nocapture) #1 ; Function Attrs: nounwind uwtable define dso_local void @bar(ptr %A) #0 !dbg !41 { @@ -98,7 +98,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 ; CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8, !tbaa [[TBAA18]] ; CHECK-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META43:![0-9]+]], !DIExpression(), [[META46:![0-9]+]]) -; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG47:![0-9]+]] ; CHECK-NEXT: #dbg_declare(ptr [[I]], [[META44:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) ; CHECK-NEXT: store i32 0, ptr [[I]], align 4, !dbg [[META48]], !tbaa [[TBAA24]] ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47]] @@ -109,7 +109,7 @@ define dso_local void @bar(ptr %A) #0 !dbg !41 { ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP2]], !dbg [[DBG53:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]], !dbg [[DBG54:![0-9]+]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[I]]) #[[ATTR2]], !dbg [[DBG55:![0-9]+]] ; CHECK-NEXT: br label [[FOR_END:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG56:![0-9]+]], !tbaa [[TBAA18]] @@ -131,7 +131,7 @@ entry: %i = alloca i32, align 4 store ptr %A, ptr %A.addr, align 8, !tbaa !18 #dbg_declare(ptr %A.addr, !43, !DIExpression(), !46) - call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2, !dbg !47 + call void @llvm.lifetime.start.p0(ptr %i) #2, !dbg !47 #dbg_declare(ptr %i, !44, !DIExpression(), !48) store i32 0, ptr %i, align 4, !dbg !48, !tbaa !24 br label %for.cond, !dbg !47 @@ -144,7 +144,7 @@ for.cond: ; preds = %for.inc, %entry br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !54 for.cond.cleanup: ; preds = %for.cond - call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2, !dbg !55 + call void @llvm.lifetime.end.p0(ptr %i) #2, !dbg !55 br label %for.end for.body: ; preds = %for.cond diff --git a/llvm/test/tools/dxil-dis/constantexpr-gep.ll b/llvm/test/tools/dxil-dis/constantexpr-gep.ll new file mode 100644 index 0000000..5925147 --- /dev/null +++ b/llvm/test/tools/dxil-dis/constantexpr-gep.ll @@ -0,0 +1,35 @@ +; RUN: llc --filetype=obj %s -o - | dxil-dis -o - | FileCheck %s +target triple = "dxil-unknown-shadermodel6.7-library" + +; CHECK: [[GLOBAL:@.*]] = unnamed_addr addrspace(3) global [10 x i32] zeroinitializer, align 4 +@g = local_unnamed_addr addrspace(3) global [10 x i32] zeroinitializer, align 4 + +define i32 @fn() #0 { +; CHECK-LABEL: define i32 @fn() +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([10 x i32], [10 x i32] addrspace(3)* [[GLOBAL]], i32 0, i32 1), align 4 +; CHECK-NEXT: ret i32 [[LOAD]] +; + %gep = getelementptr [10 x i32], ptr addrspace(3) @g, i32 0, i32 1 + %ld = load i32, ptr addrspace(3) %gep, align 4 + ret i32 %ld +} + +define i32 @fn2() #0 { +; CHECK-LABEL: define i32 @fn2() +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([10 x i32], [10 x i32] addrspace(3)* [[GLOBAL]], i32 0, i32 2), align 4 +; CHECK-NEXT: ret i32 [[LOAD]] +; + %ld = load i32, ptr addrspace(3) getelementptr ([10 x i32], ptr addrspace(3) @g, i32 0, i32 2), align 4 + ret i32 %ld +} + +define i32 @fn3() #0 { +; CHECK-LABEL: define i32 @fn3() +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([10 x i32], [10 x i32] addrspace(3)* [[GLOBAL]], i32 0, i32 3), align 4 +; CHECK-NEXT: ret i32 [[LOAD]] +; + %ld = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @g, i32 12), align 4 + ret i32 %ld +} + +attributes #0 = { "hlsl.export" } diff --git a/llvm/test/tools/dxil-dis/lifetimes.ll b/llvm/test/tools/dxil-dis/lifetimes.ll index cb3e629..af7a19a 100644 --- a/llvm/test/tools/dxil-dis/lifetimes.ll +++ b/llvm/test/tools/dxil-dis/lifetimes.ll @@ -4,19 +4,17 @@ target triple = "dxil-unknown-shadermodel6.7-library" define void @test_lifetimes() { ; CHECK-LABEL: test_lifetimes ; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [2 x i32], align 4 -; CHECK-NEXT: [[GEP:%.*]] = getelementptr [2 x i32], [2 x i32]* [[ALLOCA]], i32 0, i32 0 ; CHECK-NEXT: [[BITCAST:%.*]] = bitcast [2 x i32]* [[ALLOCA]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start(i64 4, i8* nonnull [[BITCAST]]) -; CHECK-NEXT: store i32 0, i32* [[GEP]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start(i64 8, i8* nonnull [[BITCAST]]) ; CHECK-NEXT: [[BITCAST:%.*]] = bitcast [2 x i32]* [[ALLOCA]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.end(i64 4, i8* nonnull [[BITCAST]]) +; CHECK-NEXT: call void @llvm.lifetime.end(i64 8, i8* nonnull [[BITCAST]]) ; CHECK-NEXT: ret void ; %a = alloca [2 x i32], align 4 %gep = getelementptr [2 x i32], ptr %a, i32 0, i32 0 - call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %a) + call void @llvm.lifetime.start.p0(ptr nonnull %a) store i32 0, ptr %gep, align 4 - call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %a) + call void @llvm.lifetime.end.p0(ptr nonnull %a) ret void } @@ -29,10 +27,10 @@ define void @test_lifetimes() { ; CHECK-DAG: declare void @llvm.lifetime.end(i64, i8* nocapture) [[LIFETIME_ATTRS]] ; Function Attrs: nounwind memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64, ptr) #0 +declare void @llvm.lifetime.end.p0(ptr) #0 ; Function Attrs: nounwind memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64, ptr) #0 +declare void @llvm.lifetime.start.p0(ptr) #0 attributes #0 = { nounwind memory(argmem: readwrite) } diff --git a/llvm/test/tools/dxil-dis/opaque-value_as_metadata.ll b/llvm/test/tools/dxil-dis/opaque-value_as_metadata.ll index 165d5d2..c53bb21 100644 --- a/llvm/test/tools/dxil-dis/opaque-value_as_metadata.ll +++ b/llvm/test/tools/dxil-dis/opaque-value_as_metadata.ll @@ -7,6 +7,7 @@ target triple = "dxil-unknown-shadermodel6.7-library" @CBV = external constant %"$Globals" define void @main() #0 { + %1 = load float, ptr @CBV, align 4 ret void } diff --git a/llvm/test/tools/llvm-cgdata/empty.test b/llvm/test/tools/llvm-cgdata/empty.test index 0d2b0e8..2082eca 100644 --- a/llvm/test/tools/llvm-cgdata/empty.test +++ b/llvm/test/tools/llvm-cgdata/empty.test @@ -16,7 +16,7 @@ RUN: llvm-cgdata --show %t_emptyheader.cgdata | count 0 # The version number appears when asked, as it's in the header RUN: llvm-cgdata --show --cgdata-version %t_emptyheader.cgdata | FileCheck %s --check-prefix=VERSION -VERSION: Version: 3 +VERSION: Version: 4 # When converting a binary file (w/ the header only) to a text file, it's an empty file as the text format does not have an explicit header. RUN: llvm-cgdata --convert %t_emptyheader.cgdata --format text | count 0 @@ -30,7 +30,7 @@ RUN: llvm-cgdata --convert %t_emptyheader.cgdata --format text | count 0 # uint64_t StableFunctionMapOffset; # } RUN: printf '\xffcgdata\x81' > %t_header.cgdata -RUN: printf '\x03\x00\x00\x00' >> %t_header.cgdata +RUN: printf '\x04\x00\x00\x00' >> %t_header.cgdata RUN: printf '\x00\x00\x00\x00' >> %t_header.cgdata RUN: printf '\x20\x00\x00\x00\x00\x00\x00\x00' >> %t_header.cgdata RUN: printf '\x20\x00\x00\x00\x00\x00\x00\x00' >> %t_header.cgdata diff --git a/llvm/test/tools/llvm-cgdata/error.test b/llvm/test/tools/llvm-cgdata/error.test index 92ff484..9484371 100644 --- a/llvm/test/tools/llvm-cgdata/error.test +++ b/llvm/test/tools/llvm-cgdata/error.test @@ -22,9 +22,9 @@ RUN: printf '\xffcgdata\x81' > %t_corrupt.cgdata RUN: not llvm-cgdata --show %t_corrupt.cgdata 2>&1 | FileCheck %s --check-prefix=CORRUPT CORRUPT: {{.}}cgdata: invalid codegen data (file header is corrupt) -# The current version 3 while the header says 4. +# The current version 4 while the header says 5. RUN: printf '\xffcgdata\x81' > %t_version.cgdata -RUN: printf '\x04\x00\x00\x00' >> %t_version.cgdata +RUN: printf '\x05\x00\x00\x00' >> %t_version.cgdata RUN: printf '\x00\x00\x00\x00' >> %t_version.cgdata RUN: printf '\x20\x00\x00\x00\x00\x00\x00\x00' >> %t_version.cgdata RUN: printf '\x20\x00\x00\x00\x00\x00\x00\x00' >> %t_version.cgdata diff --git a/llvm/test/tools/llvm-cgdata/merge-combined-funcmap-hashtree.test b/llvm/test/tools/llvm-cgdata/merge-combined-funcmap-hashtree.test index b060872..70b83af 100644 --- a/llvm/test/tools/llvm-cgdata/merge-combined-funcmap-hashtree.test +++ b/llvm/test/tools/llvm-cgdata/merge-combined-funcmap-hashtree.test @@ -23,6 +23,8 @@ RUN: llc -filetype=obj -mtriple arm64-apple-darwin %t/merge-both-hashtree-funcma # Merge an object file having cgdata (__llvm_outline and __llvm_merge) RUN: llvm-cgdata -m --skip-trim %t/merge-both-hashtree-funcmap.o -o %t/merge-both-hashtree-funcmap.cgdata RUN: llvm-cgdata -s %t/merge-both-hashtree-funcmap.cgdata | FileCheck %s +RUN: llvm-cgdata -m --skip-trim %t/merge-both-hashtree-funcmap.o -o %t/merge-both-hashtree-funcmap-lazy.cgdata -indexed-codegen-data-lazy-loading +RUN: llvm-cgdata -s %t/merge-both-hashtree-funcmap-lazy.cgdata -indexed-codegen-data-lazy-loading | FileCheck %s CHECK: Outlined hash tree: CHECK-NEXT: Total Node Count: 3 @@ -63,4 +65,4 @@ CHECK-NEXT: Mergeable function Count: 0 ;--- merge-both-template.ll @.data1 = private unnamed_addr constant [72 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_outline" -@.data2 = private unnamed_addr constant [68 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" +@.data2 = private unnamed_addr constant [84 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" diff --git a/llvm/test/tools/llvm-cgdata/merge-funcmap-archive.test b/llvm/test/tools/llvm-cgdata/merge-funcmap-archive.test index 2936086..c088ffb 100644 --- a/llvm/test/tools/llvm-cgdata/merge-funcmap-archive.test +++ b/llvm/test/tools/llvm-cgdata/merge-funcmap-archive.test @@ -23,8 +23,8 @@ RUN: llvm-ar rcs %t/merge-archive.a %t/merge-1.o %t/merge-2.o # Merge the archive into the codegen data file. RUN: llvm-cgdata --merge --skip-trim %t/merge-archive.a -o %t/merge-archive.cgdata RUN: llvm-cgdata --show %t/merge-archive.cgdata | FileCheck %s - -RUN: llvm-cgdata --show %t/merge-archive.cgdata| FileCheck %s +RUN: llvm-cgdata --merge --skip-trim %t/merge-archive.a -o %t/merge-archive-lazy.cgdata -indexed-codegen-data-lazy-loading +RUN: llvm-cgdata --show %t/merge-archive-lazy.cgdata -indexed-codegen-data-lazy-loading | FileCheck %s CHECK: Stable function map: CHECK-NEXT: Unique hash Count: 1 CHECK-NEXT: Total function Count: 2 @@ -65,7 +65,7 @@ MAP-NEXT: ... ... ;--- merge-1-template.ll -@.data = private unnamed_addr constant [68 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" +@.data = private unnamed_addr constant [84 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" ;--- raw-2.cgtext :stable_function_map @@ -80,4 +80,4 @@ MAP-NEXT: ... ... ;--- merge-2-template.ll -@.data = private unnamed_addr constant [68 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" +@.data = private unnamed_addr constant [84 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" diff --git a/llvm/test/tools/llvm-cgdata/merge-funcmap-concat.test b/llvm/test/tools/llvm-cgdata/merge-funcmap-concat.test index d296545..90b5992 100644 --- a/llvm/test/tools/llvm-cgdata/merge-funcmap-concat.test +++ b/llvm/test/tools/llvm-cgdata/merge-funcmap-concat.test @@ -17,6 +17,8 @@ RUN: sed "s/<RAW_2_BYTES>/$(cat %t/raw-2-bytes.txt)/g" %t/merge-concat-template- RUN: llc -filetype=obj -mtriple arm64-apple-darwin %t/merge-concat.ll -o %t/merge-concat.o RUN: llvm-cgdata --merge --skip-trim %t/merge-concat.o -o %t/merge-concat.cgdata RUN: llvm-cgdata --show %t/merge-concat.cgdata | FileCheck %s +RUN: llvm-cgdata --merge --skip-trim %t/merge-concat.o -o %t/merge-concat-lazy.cgdata -indexed-codegen-data-lazy-loading +RUN: llvm-cgdata --show %t/merge-concat-lazy.cgdata -indexed-codegen-data-lazy-loading | FileCheck %s CHECK: Stable function map: CHECK-NEXT: Unique hash Count: 1 @@ -74,5 +76,5 @@ MAP-NEXT: ... ; In an linked executable (as opposed to an object file), cgdata in __llvm_merge might be concatenated. ; Although this is not a typical workflow, we simply support this case to parse cgdata that is concatenated. ; In other words, the following two trees are encoded back-to-back in a binary format. -@.data1 = private unnamed_addr constant [68 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" -@.data2 = private unnamed_addr constant [68 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" +@.data1 = private unnamed_addr constant [84 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" +@.data2 = private unnamed_addr constant [84 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" diff --git a/llvm/test/tools/llvm-cgdata/merge-funcmap-double.test b/llvm/test/tools/llvm-cgdata/merge-funcmap-double.test index 8277e32..b986aef 100644 --- a/llvm/test/tools/llvm-cgdata/merge-funcmap-double.test +++ b/llvm/test/tools/llvm-cgdata/merge-funcmap-double.test @@ -19,8 +19,9 @@ RUN: llc -filetype=obj -mtriple arm64-apple-darwin %t/merge-2.ll -o %t/merge-2.o # Merge two object files into the codegen data file. RUN: llvm-cgdata --merge --skip-trim %t/merge-1.o %t/merge-2.o -o %t/merge.cgdata - RUN: llvm-cgdata --show %t/merge.cgdata | FileCheck %s +RUN: llvm-cgdata --merge --skip-trim %t/merge-1.o %t/merge-2.o -o %t/merge-lazy.cgdata -indexed-codegen-data-lazy-loading +RUN: llvm-cgdata --show %t/merge-lazy.cgdata -indexed-codegen-data-lazy-loading | FileCheck %s CHECK: Stable function map: CHECK-NEXT: Unique hash Count: 1 CHECK-NEXT: Total function Count: 2 @@ -61,7 +62,7 @@ MAP-NEXT: ... ... ;--- merge-1-template.ll -@.data = private unnamed_addr constant [68 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" +@.data = private unnamed_addr constant [84 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" ;--- raw-2.cgtext :stable_function_map @@ -76,4 +77,4 @@ MAP-NEXT: ... ... ;--- merge-2-template.ll -@.data = private unnamed_addr constant [68 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" +@.data = private unnamed_addr constant [84 x i8] c"<RAW_2_BYTES>", section "__DATA,__llvm_merge" diff --git a/llvm/test/tools/llvm-cgdata/merge-funcmap-single.test b/llvm/test/tools/llvm-cgdata/merge-funcmap-single.test index 9469f1c..eac852f 100644 --- a/llvm/test/tools/llvm-cgdata/merge-funcmap-single.test +++ b/llvm/test/tools/llvm-cgdata/merge-funcmap-single.test @@ -15,6 +15,8 @@ RUN: llc -filetype=obj -mtriple arm64-apple-darwin %t/merge-single.ll -o %t/merg # Merge an object file having cgdata (__llvm_merge) RUN: llvm-cgdata -m --skip-trim %t/merge-single.o -o %t/merge-single.cgdata RUN: llvm-cgdata -s %t/merge-single.cgdata | FileCheck %s +RUN: llvm-cgdata -m --skip-trim %t/merge-single.o -o %t/merge-single-lazy.cgdata -indexed-codegen-data-lazy-loading +RUN: llvm-cgdata -s %t/merge-single-lazy.cgdata -indexed-codegen-data-lazy-loading | FileCheck %s CHECK: Stable function map: CHECK-NEXT: Unique hash Count: 1 CHECK-NEXT: Total function Count: 1 @@ -33,4 +35,4 @@ CHECK-NEXT: Mergeable function Count: 0 ... ;--- merge-single-template.ll -@.data = private unnamed_addr constant [68 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" +@.data = private unnamed_addr constant [84 x i8] c"<RAW_1_BYTES>", section "__DATA,__llvm_merge" diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-print-basic-details.test b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-print-basic-details.test index 54dbd74..6d767eb 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-print-basic-details.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-print-basic-details.test @@ -45,8 +45,6 @@ ; ONE-NEXT: [004] 6 {Line} ; ONE-NEXT: [004] {Code} 'movl $0x7, -0x4(%rbp)' ; ONE-NEXT: [004] {Code} 'jmp 0x6' -; ONE-NEXT: [004] 8 {Line} -; ONE-NEXT: [004] {Code} 'movl -0x14(%rbp), %eax' ; ONE-NEXT: [003] 4 {TypeAlias} 'INTEGER' -> 'int' ; ONE-NEXT: [003] 2 {Line} ; ONE-NEXT: [003] {Code} 'pushq %rbp' @@ -60,10 +58,12 @@ ; ONE-NEXT: [003] {Code} 'testb $0x1, -0x15(%rbp)' ; ONE-NEXT: [003] {Code} 'je 0x13' ; ONE-NEXT: [003] 8 {Line} +; ONE-NEXT: [003] {Code} 'movl -0x14(%rbp), %eax' +; ONE-NEXT: [003] 8 {Line} ; ONE-NEXT: [003] {Code} 'movl %eax, -0x4(%rbp)' ; ONE-NEXT: [003] 9 {Line} ; ONE-NEXT: [003] {Code} 'movl -0x4(%rbp), %eax' ; ONE-NEXT: [003] {Code} 'popq %rbp' ; ONE-NEXT: [003] {Code} 'retq' -; ONE-NEXT: [003] 9 {Line} ; ONE-NEXT: [002] 1 {TypeAlias} 'INTPTR' -> '* const int' +; ONE-NEXT: [002] 9 {Line} diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-select-logical-elements.test b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-select-logical-elements.test index f84e920..5690cf5 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-select-logical-elements.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/01-dwarf-select-logical-elements.test @@ -34,7 +34,7 @@ ; ONE-NEXT: [004] {Code} 'movl $0x7, -0x4(%rbp)' ; ONE-NEXT: [003] {Code} 'movl %eax, -0x4(%rbp)' ; ONE-NEXT: [003] {Code} 'movl %esi, -0x14(%rbp)' -; ONE-NEXT: [004] {Code} 'movl -0x14(%rbp), %eax' +; ONE-NEXT: [003] {Code} 'movl -0x14(%rbp), %eax' ; ONE-NEXT: [003] {Code} 'movl -0x4(%rbp), %eax' ; ONE-NEXT: [003] 4 {TypeAlias} 'INTEGER' -> 'int' ; ONE-NEXT: [004] 5 {Variable} 'CONSTANT' -> 'const INTEGER' diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/02-dwarf-logical-lines.test b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/02-dwarf-logical-lines.test index 533914f..bff7c94 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/02-dwarf-logical-lines.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/02-dwarf-logical-lines.test @@ -42,7 +42,7 @@ ; ONE-NEXT: [003] {Code} 'addq $0x10, %rsp' ; ONE-NEXT: [003] {Code} 'popq %rbp' ; ONE-NEXT: [003] {Code} 'retq' -; ONE-NEXT: [003] 6 {Line} +; ONE-NEXT: [002] 6 {Line} ; ONE-EMPTY: ; ONE-NEXT: Logical View: ; ONE-NEXT: [000] {File} 'hello-world-dwarf-gcc.o' -> elf64-x86-64 @@ -64,4 +64,4 @@ ; ONE-NEXT: [003] 7 {Line} ; ONE-NEXT: [003] {Code} 'popq %rbp' ; ONE-NEXT: [003] {Code} 'retq' -; ONE-NEXT: [003] 7 {Line} +; ONE-NEXT: [002] 7 {Line} diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/03-dwarf-incorrect-lexical-scope-typedef.test b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/03-dwarf-incorrect-lexical-scope-typedef.test index dc57d01..69b6514 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/03-dwarf-incorrect-lexical-scope-typedef.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/03-dwarf-incorrect-lexical-scope-typedef.test @@ -59,7 +59,6 @@ ; ONE-NEXT: [004] 10 {Line} ; ONE-NEXT: [004] 10 {Line} ; ONE-NEXT: [004] 10 {Line} -; ONE-NEXT: [004] 13 {Line} ; ONE-NEXT: [003] 3 {Parameter} 'Param' -> 'char' ; ONE-NEXT: [003] 7 {TypeAlias} 'FLOAT' -> 'float' ; ONE-NEXT: [003] 4 {TypeAlias} 'INT' -> 'int' @@ -71,6 +70,7 @@ ; ONE-NEXT: [003] 13 {Line} ; ONE-NEXT: [003] 13 {Line} ; ONE-NEXT: [003] 13 {Line} +; ONE-NEXT: [002] 13 {Line} ; ONE-EMPTY: ; ONE-NEXT: Logical View: ; ONE-NEXT: [000] {File} 'pr-44884-dwarf-gcc.o' -> elf64-x86-64 @@ -91,7 +91,6 @@ ; ONE-NEXT: [005] 9 {Line} ; ONE-NEXT: [005] 9 {Line} ; ONE-NEXT: [005] 10 {Line} -; ONE-NEXT: [005] 13 {Line} ; ONE-NEXT: [004] 7 {TypeAlias} 'FLOAT' -> 'float' ; ONE-NEXT: [003] 3 {Parameter} 'Param' -> 'char' ; ONE-NEXT: [003] 4 {TypeAlias} 'INT' -> 'int' @@ -99,8 +98,9 @@ ; ONE-NEXT: [003] 3 {Line} ; ONE-NEXT: [003] 5 {Line} ; ONE-NEXT: [003] 13 {Line} +; ONE-NEXT: [003] 13 {Line} ; ONE-NEXT: [003] 14 {Line} -; ONE-NEXT: [003] 14 {Line} +; ONE-NEXT: [002] 14 {Line} ; Using the selection facilities, we can produce a simple tabular ; output showing just the logical types that are 'Typedef'. diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/06-dwarf-full-logical-view.test b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/06-dwarf-full-logical-view.test index 6616710..a2f05dd 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/06-dwarf-full-logical-view.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/06-dwarf-full-logical-view.test @@ -53,8 +53,6 @@ ; ONE-NEXT: [0x0000000023][004] 6 {Line} {NewStatement} '/data/projects/tests/input/general/test.cpp' ; ONE-NEXT: [0x0000000023][004] {Code} 'movl $0x7, -0x4(%rbp)' ; ONE-NEXT: [0x000000002a][004] {Code} 'jmp 0x6' -; ONE-NEXT: [0x000000002f][004] 8 {Line} {NewStatement} '/data/projects/tests/input/general/test.cpp' -; ONE-NEXT: [0x000000002f][004] {Code} 'movl -0x14(%rbp), %eax' ; ONE-NEXT: [0x0000000063][003] 2 {Parameter} 'ParamBool' -> [0x00000000bc]'bool' ; ONE-NEXT: [0x0000000063][004] {Coverage} 100.00% ; ONE-NEXT: [0x0000000064][004] {Location} @@ -79,13 +77,15 @@ ; ONE-NEXT: [0x0000000012][003] 3 {Line} {NewStatement} {PrologueEnd} '/data/projects/tests/input/general/test.cpp' ; ONE-NEXT: [0x0000000012][003] {Code} 'testb $0x1, -0x15(%rbp)' ; ONE-NEXT: [0x0000000016][003] {Code} 'je 0x13' +; ONE-NEXT: [0x000000002f][003] 8 {Line} {NewStatement} '/data/projects/tests/input/general/test.cpp' +; ONE-NEXT: [0x000000002f][003] {Code} 'movl -0x14(%rbp), %eax' ; ONE-NEXT: [0x0000000032][003] 8 {Line} '/data/projects/tests/input/general/test.cpp' ; ONE-NEXT: [0x0000000032][003] {Code} 'movl %eax, -0x4(%rbp)' ; ONE-NEXT: [0x0000000035][003] 9 {Line} {NewStatement} '/data/projects/tests/input/general/test.cpp' ; ONE-NEXT: [0x0000000035][003] {Code} 'movl -0x4(%rbp), %eax' ; ONE-NEXT: [0x0000000038][003] {Code} 'popq %rbp' ; ONE-NEXT: [0x0000000039][003] {Code} 'retq' -; ONE-NEXT: [0x000000003a][003] 9 {Line} {NewStatement} {EndSequence} '/data/projects/tests/input/general/test.cpp' +; ONE-NEXT: [0x000000003a][002] 9 {Line} {NewStatement} {EndSequence} '/data/projects/tests/input/general/test.cpp' ; ONE-EMPTY: ; ONE-NEXT: ----------------------------- ; ONE-NEXT: Element Total Printed diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_ranges.s b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_ranges.s new file mode 100644 index 0000000..daeda00 --- /dev/null +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_ranges.s @@ -0,0 +1,610 @@ +# Regression test for: +# - DW_AT_ranges not being read properly + +# clang test.cpp --target=i686-pc-linux -g -O2 +# 01 +# 02 float foo(float a) { +# 03 return a+a; +# 04 } +# 05 +# 06 int main(int argc, char **argv) { +# 07 float my_var = argc; +# 08 for (int i = 0; i < 4; i++) { +# 09 float my_local_var = (float)argv[i][0]; +# 10 my_var += foo(my_local_var); +# 11 } +# 12 return (int)my_var; +# 13 } + +# REQUIRES: x86-registered-target + +# RUN: llvm-mc %s -triple=i686-pc-linux -filetype=obj -o - | \ +# RUN: llvm-debuginfo-analyzer --attribute=all \ +# RUN: --print=all \ +# RUN: --output-sort=offset \ +# RUN: - | \ +# RUN: FileCheck %s + +# Make sure these two ranges are present and point to the correct offsets +# CHECK: [006] {Range} Lines 3:10 [0x0000000055:0x0000000058] +# CHECK: [006] {Range} Lines 3:10 [0x0000000088:0x000000008b] + + .file "test.cpp" + .file 0 "F:\\llvm-project" "test.cpp" + .text + .globl _Z3foof # -- Begin function _Z3foof + .p2align 4 + .type _Z3foof,@function +_Z3foof: # @_Z3foof +.Lfunc_begin0: + .loc 0 2 0 + .cfi_startproc +# %bb.0: # %entry + pushl %eax + .cfi_def_cfa_offset 8 +.Ltmp0: + #DEBUG_VALUE: foo:a <- [DW_OP_plus_uconst 8] [$esp+0] + movss 8(%esp), %xmm0 # xmm0 = mem[0],zero,zero,zero +.Ltmp1: + .loc 0 3 11 prologue_end + addss %xmm0, %xmm0 + .loc 0 3 3 is_stmt 0 + movss %xmm0, (%esp) + flds (%esp) + .loc 0 3 3 epilogue_begin + popl %eax + .cfi_def_cfa_offset 4 + retl +.Ltmp2: +.Lfunc_end0: + .size _Z3foof, .Lfunc_end0-_Z3foof + .cfi_endproc + # -- End function + .globl main # -- Begin function main + .p2align 4 + .type main,@function +main: # @main +.Lfunc_begin1: + .loc 0 6 0 is_stmt 1 + .cfi_startproc +# %bb.0: # %entry + #DEBUG_VALUE: main:argc <- [DW_OP_plus_uconst 4] [$esp+0] + #DEBUG_VALUE: main:argv <- [DW_OP_plus_uconst 8] [$esp+0] + movl 8(%esp), %eax +.Ltmp3: + .loc 0 7 18 prologue_end + cvtsi2ssl 4(%esp), %xmm2 +.Ltmp4: + #DEBUG_VALUE: main:my_var <- $xmm2 + #DEBUG_VALUE: i <- 0 + .loc 0 9 33 + movl (%eax), %ecx +.Ltmp5: + #DEBUG_VALUE: i <- 1 + movl 4(%eax), %edx + movzbl (%ecx), %ecx + shll $8, %ecx + pxor %xmm0, %xmm0 + pxor %xmm1, %xmm1 + pinsrw $1, %ecx, %xmm1 + movzbl (%edx), %ecx + shll $8, %ecx + pinsrw $3, %ecx, %xmm1 + psrad $24, %xmm1 + cvtdq2ps %xmm1, %xmm1 +.Ltmp6: + .loc 0 3 11 + addps %xmm1, %xmm1 +.Ltmp7: + .loc 0 10 12 + addss %xmm1, %xmm2 +.Ltmp8: + #DEBUG_VALUE: main:my_var <- $xmm2 + shufps $85, %xmm1, %xmm1 # xmm1 = xmm1[1,1,1,1] + addss %xmm2, %xmm1 +.Ltmp9: + #DEBUG_VALUE: main:my_var <- $xmm1 + #DEBUG_VALUE: i <- 2 + .loc 0 9 33 + movl 8(%eax), %ecx +.Ltmp10: + #DEBUG_VALUE: i <- 3 + movl 12(%eax), %eax + movzbl (%ecx), %ecx + shll $8, %ecx + pinsrw $1, %ecx, %xmm0 + movzbl (%eax), %eax + shll $8, %eax + pinsrw $3, %eax, %xmm0 + psrad $24, %xmm0 + cvtdq2ps %xmm0, %xmm0 +.Ltmp11: + .loc 0 3 11 + addps %xmm0, %xmm0 +.Ltmp12: + .loc 0 10 12 + addss %xmm0, %xmm1 +.Ltmp13: + #DEBUG_VALUE: main:my_var <- $xmm1 + shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1] + addss %xmm1, %xmm0 +.Ltmp14: + #DEBUG_VALUE: main:my_var <- $xmm0 + #DEBUG_VALUE: i <- 4 + .loc 0 12 15 + cvttss2si %xmm0, %eax + .loc 0 12 3 is_stmt 0 + retl +.Ltmp15: +.Lfunc_end1: + .size main, .Lfunc_end1-main + .cfi_endproc + # -- End function + .section .debug_loclists,"",@progbits + .long .Ldebug_list_header_end0-.Ldebug_list_header_start0 # Length +.Ldebug_list_header_start0: + .short 5 # Version + .byte 4 # Address size + .byte 0 # Segment selector size + .long 2 # Offset entry count +.Lloclists_table_base0: + .long .Ldebug_loc0-.Lloclists_table_base0 + .long .Ldebug_loc1-.Lloclists_table_base0 +.Ldebug_loc0: + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp4-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp9-.Lfunc_begin0 # ending offset + .byte 1 # Loc expr size + .byte 103 # DW_OP_reg23 + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp9-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp14-.Lfunc_begin0 # ending offset + .byte 1 # Loc expr size + .byte 102 # DW_OP_reg22 + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp14-.Lfunc_begin0 # starting offset + .uleb128 .Lfunc_end1-.Lfunc_begin0 # ending offset + .byte 1 # Loc expr size + .byte 101 # DW_OP_reg21 + .byte 0 # DW_LLE_end_of_list +.Ldebug_loc1: + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp4-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp5-.Lfunc_begin0 # ending offset + .byte 3 # Loc expr size + .byte 17 # DW_OP_consts + .byte 0 # 0 + .byte 159 # DW_OP_stack_value + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp5-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp9-.Lfunc_begin0 # ending offset + .byte 3 # Loc expr size + .byte 17 # DW_OP_consts + .byte 1 # 1 + .byte 159 # DW_OP_stack_value + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp9-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp10-.Lfunc_begin0 # ending offset + .byte 3 # Loc expr size + .byte 17 # DW_OP_consts + .byte 2 # 2 + .byte 159 # DW_OP_stack_value + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp10-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp14-.Lfunc_begin0 # ending offset + .byte 3 # Loc expr size + .byte 17 # DW_OP_consts + .byte 3 # 3 + .byte 159 # DW_OP_stack_value + .byte 4 # DW_LLE_offset_pair + .uleb128 .Ltmp14-.Lfunc_begin0 # starting offset + .uleb128 .Lfunc_end1-.Lfunc_begin0 # ending offset + .byte 3 # Loc expr size + .byte 17 # DW_OP_consts + .byte 4 # 4 + .byte 159 # DW_OP_stack_value + .byte 0 # DW_LLE_end_of_list +.Ldebug_list_header_end0: + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 1 # DW_CHILDREN_yes + .byte 37 # DW_AT_producer + .byte 37 # DW_FORM_strx1 + .byte 19 # DW_AT_language + .byte 5 # DW_FORM_data2 + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 114 # DW_AT_str_offsets_base + .byte 23 # DW_FORM_sec_offset + .byte 16 # DW_AT_stmt_list + .byte 23 # DW_FORM_sec_offset + .byte 27 # DW_AT_comp_dir + .byte 37 # DW_FORM_strx1 + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 115 # DW_AT_addr_base + .byte 23 # DW_FORM_sec_offset + .byte 116 # DW_AT_rnglists_base + .byte 23 # DW_FORM_sec_offset + .ascii "\214\001" # DW_AT_loclists_base + .byte 23 # DW_FORM_sec_offset + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 2 # Abbreviation Code + .byte 36 # DW_TAG_base_type + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 62 # DW_AT_encoding + .byte 11 # DW_FORM_data1 + .byte 11 # DW_AT_byte_size + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 3 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 1 # DW_CHILDREN_yes + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 64 # DW_AT_frame_base + .byte 24 # DW_FORM_exprloc + .byte 122 # DW_AT_call_all_calls + .byte 25 # DW_FORM_flag_present + .byte 49 # DW_AT_abstract_origin + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 4 # Abbreviation Code + .byte 5 # DW_TAG_formal_parameter + .byte 0 # DW_CHILDREN_no + .byte 2 # DW_AT_location + .byte 24 # DW_FORM_exprloc + .byte 49 # DW_AT_abstract_origin + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 5 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 1 # DW_CHILDREN_yes + .byte 110 # DW_AT_linkage_name + .byte 37 # DW_FORM_strx1 + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 32 # DW_AT_inline + .byte 33 # DW_FORM_implicit_const + .byte 1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 6 # Abbreviation Code + .byte 5 # DW_TAG_formal_parameter + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 7 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 1 # DW_CHILDREN_yes + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 64 # DW_AT_frame_base + .byte 24 # DW_FORM_exprloc + .byte 122 # DW_AT_call_all_calls + .byte 25 # DW_FORM_flag_present + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 8 # Abbreviation Code + .byte 5 # DW_TAG_formal_parameter + .byte 0 # DW_CHILDREN_no + .byte 2 # DW_AT_location + .byte 24 # DW_FORM_exprloc + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 9 # Abbreviation Code + .byte 52 # DW_TAG_variable + .byte 0 # DW_CHILDREN_no + .byte 2 # DW_AT_location + .byte 34 # DW_FORM_loclistx + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 10 # Abbreviation Code + .byte 11 # DW_TAG_lexical_block + .byte 1 # DW_CHILDREN_yes + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 11 # Abbreviation Code + .byte 52 # DW_TAG_variable + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 12 # Abbreviation Code + .byte 29 # DW_TAG_inlined_subroutine + .byte 0 # DW_CHILDREN_no + .byte 49 # DW_AT_abstract_origin + .byte 19 # DW_FORM_ref4 + .byte 85 # DW_AT_ranges + .byte 35 # DW_FORM_rnglistx + .byte 88 # DW_AT_call_file + .byte 11 # DW_FORM_data1 + .byte 89 # DW_AT_call_line + .byte 11 # DW_FORM_data1 + .byte 87 # DW_AT_call_column + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 13 # Abbreviation Code + .byte 15 # DW_TAG_pointer_type + .byte 0 # DW_CHILDREN_no + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + .section .debug_info,"",@progbits +.Lcu_begin0: + .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit +.Ldebug_info_start0: + .short 5 # DWARF version number + .byte 1 # DWARF Unit Type + .byte 4 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + .byte 1 # Abbrev [1] 0xc:0xb4 DW_TAG_compile_unit + .byte 0 # DW_AT_producer + .short 33 # DW_AT_language + .byte 1 # DW_AT_name + .long .Lstr_offsets_base0 # DW_AT_str_offsets_base + .long .Lline_table_start0 # DW_AT_stmt_list + .byte 2 # DW_AT_comp_dir + .byte 0 # DW_AT_low_pc + .long .Lfunc_end1-.Lfunc_begin0 # DW_AT_high_pc + .long .Laddr_table_base0 # DW_AT_addr_base + .long .Lrnglists_table_base0 # DW_AT_rnglists_base + .long .Lloclists_table_base0 # DW_AT_loclists_base + .byte 2 # Abbrev [2] 0x2b:0x4 DW_TAG_base_type + .byte 3 # DW_AT_name + .byte 4 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 2 # Abbrev [2] 0x2f:0x4 DW_TAG_base_type + .byte 4 # DW_AT_name + .byte 5 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 3 # Abbrev [3] 0x33:0x15 DW_TAG_subprogram + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .byte 1 # DW_AT_frame_base + .byte 84 + # DW_AT_call_all_calls + .long 72 # DW_AT_abstract_origin + .byte 4 # Abbrev [4] 0x3f:0x8 DW_TAG_formal_parameter + .byte 2 # DW_AT_location + .byte 145 + .byte 8 + .long 81 # DW_AT_abstract_origin + .byte 0 # End Of Children Mark + .byte 5 # Abbrev [5] 0x48:0x12 DW_TAG_subprogram + .byte 5 # DW_AT_linkage_name + .byte 6 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 2 # DW_AT_decl_line + .long 43 # DW_AT_type + # DW_AT_external + # DW_AT_inline + .byte 6 # Abbrev [6] 0x51:0x8 DW_TAG_formal_parameter + .byte 7 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 2 # DW_AT_decl_line + .long 43 # DW_AT_type + .byte 0 # End Of Children Mark + .byte 7 # Abbrev [7] 0x5a:0x57 DW_TAG_subprogram + .byte 1 # DW_AT_low_pc + .long .Lfunc_end1-.Lfunc_begin1 # DW_AT_high_pc + .byte 1 # DW_AT_frame_base + .byte 84 + # DW_AT_call_all_calls + .byte 8 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 6 # DW_AT_decl_line + .long 47 # DW_AT_type + # DW_AT_external + .byte 8 # Abbrev [8] 0x69:0xb DW_TAG_formal_parameter + .byte 2 # DW_AT_location + .byte 145 + .byte 4 + .byte 9 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 6 # DW_AT_decl_line + .long 47 # DW_AT_type + .byte 8 # Abbrev [8] 0x74:0xb DW_TAG_formal_parameter + .byte 2 # DW_AT_location + .byte 145 + .byte 8 + .byte 10 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 6 # DW_AT_decl_line + .long 177 # DW_AT_type + .byte 9 # Abbrev [9] 0x7f:0x9 DW_TAG_variable + .byte 0 # DW_AT_location + .byte 12 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 7 # DW_AT_decl_line + .long 43 # DW_AT_type + .byte 10 # Abbrev [10] 0x88:0x28 DW_TAG_lexical_block + .byte 2 # DW_AT_low_pc + .long .Ltmp14-.Ltmp4 # DW_AT_high_pc + .byte 9 # Abbrev [9] 0x8e:0x9 DW_TAG_variable + .byte 1 # DW_AT_location + .byte 13 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 8 # DW_AT_decl_line + .long 47 # DW_AT_type + .byte 10 # Abbrev [10] 0x97:0x18 DW_TAG_lexical_block + .byte 2 # DW_AT_low_pc + .long .Ltmp14-.Ltmp4 # DW_AT_high_pc + .byte 11 # Abbrev [11] 0x9d:0x8 DW_TAG_variable + .byte 14 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 9 # DW_AT_decl_line + .long 43 # DW_AT_type + .byte 12 # Abbrev [12] 0xa5:0x9 DW_TAG_inlined_subroutine + .long 72 # DW_AT_abstract_origin + .byte 0 # DW_AT_ranges + .byte 0 # DW_AT_call_file + .byte 10 # DW_AT_call_line + .byte 15 # DW_AT_call_column + .byte 0 # End Of Children Mark + .byte 0 # End Of Children Mark + .byte 0 # End Of Children Mark + .byte 13 # Abbrev [13] 0xb1:0x5 DW_TAG_pointer_type + .long 182 # DW_AT_type + .byte 13 # Abbrev [13] 0xb6:0x5 DW_TAG_pointer_type + .long 187 # DW_AT_type + .byte 2 # Abbrev [2] 0xbb:0x4 DW_TAG_base_type + .byte 11 # DW_AT_name + .byte 6 # DW_AT_encoding + .byte 1 # DW_AT_byte_size + .byte 0 # End Of Children Mark +.Ldebug_info_end0: + .section .debug_rnglists,"",@progbits + .long .Ldebug_list_header_end1-.Ldebug_list_header_start1 # Length +.Ldebug_list_header_start1: + .short 5 # Version + .byte 4 # Address size + .byte 0 # Segment selector size + .long 1 # Offset entry count +.Lrnglists_table_base0: + .long .Ldebug_ranges0-.Lrnglists_table_base0 +.Ldebug_ranges0: + .byte 4 # DW_RLE_offset_pair + .uleb128 .Ltmp6-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp7-.Lfunc_begin0 # ending offset + .byte 4 # DW_RLE_offset_pair + .uleb128 .Ltmp11-.Lfunc_begin0 # starting offset + .uleb128 .Ltmp12-.Lfunc_begin0 # ending offset + .byte 0 # DW_RLE_end_of_list +.Ldebug_list_header_end1: + .section .debug_str_offsets,"",@progbits + .long 64 # Length of String Offsets Set + .short 5 + .short 0 +.Lstr_offsets_base0: + .section .debug_str,"MS",@progbits,1 +.Linfo_string0: + .asciz "clang version 22.0.0" # string offset=0 +.Linfo_string1: + .asciz "test.cpp" # string offset=113 +.Linfo_string2: + .asciz "F:\\llvm-project" # string offset=143 +.Linfo_string3: + .asciz "float" # string offset=159 +.Linfo_string4: + .asciz "int" # string offset=165 +.Linfo_string5: + .asciz "_Z3foof" # string offset=169 +.Linfo_string6: + .asciz "foo" # string offset=177 +.Linfo_string7: + .asciz "a" # string offset=181 +.Linfo_string8: + .asciz "main" # string offset=183 +.Linfo_string9: + .asciz "argc" # string offset=188 +.Linfo_string10: + .asciz "argv" # string offset=193 +.Linfo_string11: + .asciz "char" # string offset=198 +.Linfo_string12: + .asciz "my_var" # string offset=203 +.Linfo_string13: + .asciz "i" # string offset=210 +.Linfo_string14: + .asciz "my_local_var" # string offset=212 + .section .debug_str_offsets,"",@progbits + .long .Linfo_string0 + .long .Linfo_string1 + .long .Linfo_string2 + .long .Linfo_string3 + .long .Linfo_string4 + .long .Linfo_string5 + .long .Linfo_string6 + .long .Linfo_string7 + .long .Linfo_string8 + .long .Linfo_string9 + .long .Linfo_string10 + .long .Linfo_string11 + .long .Linfo_string12 + .long .Linfo_string13 + .long .Linfo_string14 + .section .debug_addr,"",@progbits + .long .Ldebug_addr_end0-.Ldebug_addr_start0 # Length of contribution +.Ldebug_addr_start0: + .short 5 # DWARF version number + .byte 4 # Address size + .byte 0 # Segment selector size +.Laddr_table_base0: + .long .Lfunc_begin0 + .long .Lfunc_begin1 + .long .Ltmp4 +.Ldebug_addr_end0: + .ident "clang version 22.0.0" + .section ".note.GNU-stack","",@progbits + .section .debug_line,"",@progbits +.Lline_table_start0: diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/amdgpu-ranges.s b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/amdgpu-ranges.s new file mode 100644 index 0000000..695c3ce --- /dev/null +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/amdgpu-ranges.s @@ -0,0 +1,654 @@ +# REQUIRES: amdgpu-registered-target + +# Regression test for: +# - DW_AT_ranges not being read properly +# - Instructions at DW_AT_high_pc of a scope incorrectly included in the scope + +# test.hlsl +# 01 RWBuffer<float> u0 : register(u0); +# 02 RWBuffer<float> u1 : register(u1); +# 03 +# 04 [RootSignature("DescriptorTable(UAV(u0,numDescriptors=2))")] +# 05 [numthreads(64,1,1)] +# 06 void main(uint3 dtid : SV_DispatchThreadID) { +# 07 float my_var = u0[dtid.x]; +# 08 [loop] +# 09 for (int i = 0; i < 10; i++) { +# 10 float my_local_var = i*2; +# 11 my_var += my_local_var; +# 12 } +# 13 u1[dtid.x] = my_var; +# 14 } + +# RUN: llvm-mc %s --mcpu=gfx1100 -triple=amdgcn-amd-amdpal -filetype=obj -o - | \ +# RUN: llvm-debuginfo-analyzer --attribute=all \ +# RUN: --print=all \ +# RUN: --output-sort=offset \ +# RUN: - 2>&1 | \ +# RUN: FileCheck %s + +# Make sure these two ranges are present and point to the correct offsets +# CHECK: [005] {Range} Lines 10:9 [0x00000000b0:0x00000000c8] +# CHECK: [005] {Range} Lines 11:13 [0x00000000f4:0x0000000114] + +# Make sure the offset 0x114 does not show up at the scope level 005 and 004 +# CHECK-NOT: [0x0000000114][005] +# CHECK-NOT: [0x0000000114][004] +# CHECK: [0x0000000114][003] + + .file 0 "test.hlsl" + .text + .globl _amdgpu_cs_main + .p2align 8 + .type _amdgpu_cs_main,@function +_amdgpu_cs_main: +.Lfunc_begin0: + .loc 0 6 0 + .cfi_sections .debug_frame + .cfi_startproc + v_writelane_b32 v1, s4, 0 + s_mov_b32 s0, s2 + s_mov_b32 s4, s1 + v_readlane_b32 s1, v1, 0 + s_mov_b32 s8, s0 +.Ltmp0: + .loc 0 6 24 prologue_end + s_getpc_b64 s[2:3] + s_mov_b32 s1, 0x3ff + v_and_b32_e64 v0, v0, s1 + s_mov_b32 s1, 6 + v_lshl_add_u32 v0, s0, s1, v0 + scratch_store_b32 off, v0, off offset:4 +.Ltmp1: + .loc 0 0 24 is_stmt 0 + s_mov_b32 s1, -1 + s_mov_b32 s0, 0 + s_mov_b32 s6, s0 + s_mov_b32 s7, s1 + .loc 0 7 25 is_stmt 1 + s_and_b64 s[2:3], s[2:3], s[6:7] + s_mov_b32 s1, 0 + s_mov_b32 s5, s1 + s_or_b64 s[2:3], s[2:3], s[4:5] + v_writelane_b32 v1, s2, 1 + v_writelane_b32 v1, s3, 2 +.Ltmp2: + s_load_b128 s[4:7], s[2:3], 0x0 + s_waitcnt lgkmcnt(0) + buffer_load_format_x v0, v0, s[4:7], s0 idxen +.Ltmp3: + .loc 0 9 10 + s_waitcnt vmcnt(0) + scratch_store_b32 off, v0, off +.Ltmp4: + v_writelane_b32 v1, s0, 3 +.Ltmp5: +.LBB0_1: + .loc 0 0 10 is_stmt 0 + v_readlane_b32 s0, v1, 3 + scratch_load_b32 v0, off, off +.Ltmp6: + s_mov_b32 s1, 1 +.Ltmp7: + .loc 0 10 34 is_stmt 1 + s_lshl_b32 s2, s0, s1 + .loc 0 10 33 is_stmt 0 + v_cvt_f32_u32_e64 v2, s2 +.Ltmp8: + .loc 0 11 19 is_stmt 1 + s_waitcnt vmcnt(0) + v_add_f32_e64 v0, v0, v2 +.Ltmp9: + .loc 0 9 35 + s_add_i32 s0, s0, s1 +.Ltmp10: + .loc 0 0 35 is_stmt 0 + s_mov_b32 s1, 10 + .loc 0 9 28 + s_cmp_lg_u32 s0, s1 + v_mov_b32_e32 v2, v0 +.Ltmp11: + .loc 0 0 28 + scratch_store_b32 off, v2, off + v_writelane_b32 v1, s0, 3 +.Ltmp12: + .loc 0 9 10 + scratch_store_b32 off, v0, off offset:8 +.Ltmp13: + s_cbranch_scc1 .LBB0_1 +.Ltmp14: + .loc 0 11 19 is_stmt 1 + v_readlane_b32 s0, v1, 1 +.Ltmp15: + v_readlane_b32 s1, v1, 2 + scratch_load_b32 v0, off, off offset:4 + scratch_load_b32 v6, off, off offset:8 +.Ltmp16: + .loc 0 13 21 + s_waitcnt vmcnt(0) + v_mov_b32_e32 v2, v6 + v_mov_b32_e32 v3, v6 + v_mov_b32_e32 v4, v6 + v_mov_b32_e32 v5, v6 + s_load_b128 s[0:3], s[0:1], 0x20 + s_mov_b32 s4, 0 + s_waitcnt lgkmcnt(0) + buffer_store_format_xyzw v[2:5], v0, s[0:3], s4 idxen + .loc 0 14 8 + s_endpgm +.Ltmp17: +.Lfunc_end0: + .size _amdgpu_cs_main, .Lfunc_end0-_amdgpu_cs_main + .cfi_endproc + + .set _amdgpu_cs_main.num_vgpr, 7 + .set _amdgpu_cs_main.num_agpr, 0 + .set _amdgpu_cs_main.numbered_sgpr, 11 + .set _amdgpu_cs_main.num_named_barrier, 0 + .set _amdgpu_cs_main.private_seg_size, 16 + .set _amdgpu_cs_main.uses_vcc, 0 + .set _amdgpu_cs_main.uses_flat_scratch, 0 + .set _amdgpu_cs_main.has_dyn_sized_stack, 0 + .set _amdgpu_cs_main.has_recursion, 0 + .set _amdgpu_cs_main.has_indirect_call, 0 + .set _amdgpu_cs_main.num_vgpr_rank_sum, 0 + .p2alignl 7, 3214868480 + .fill 96, 4, 3214868480 + .section .AMDGPU.gpr_maximums,"",@progbits + .set amdgpu.max_num_vgpr, 0 + .set amdgpu.max_num_agpr, 0 + .set amdgpu.max_num_sgpr, 0 + .text + .section .debug_loclists,"",@progbits + .long .Ldebug_list_header_end0-.Ldebug_list_header_start0 +.Ldebug_list_header_start0: + .short 5 + .byte 8 + .byte 0 + .long 4 +.Lloclists_table_base0: + .long .Ldebug_loc0-.Lloclists_table_base0 + .long .Ldebug_loc1-.Lloclists_table_base0 + .long .Ldebug_loc2-.Lloclists_table_base0 + .long .Ldebug_loc3-.Lloclists_table_base0 +.Ldebug_loc0: + .byte 4 + .uleb128 .Ltmp1-.Lfunc_begin0 + .uleb128 .Ltmp3-.Lfunc_begin0 + .byte 5 + .byte 144 + .byte 128 + .byte 20 + .byte 147 + .byte 4 + .byte 0 +.Ldebug_loc1: + .byte 4 + .uleb128 .Ltmp3-.Lfunc_begin0 + .uleb128 .Ltmp4-.Lfunc_begin0 + .byte 3 + .byte 144 + .byte 128 + .byte 20 + .byte 4 + .uleb128 .Ltmp6-.Lfunc_begin0 + .uleb128 .Ltmp13-.Lfunc_begin0 + .byte 3 + .byte 144 + .byte 128 + .byte 20 + .byte 4 + .uleb128 .Ltmp16-.Lfunc_begin0 + .uleb128 .Lfunc_end0-.Lfunc_begin0 + .byte 3 + .byte 144 + .byte 134 + .byte 20 + .byte 0 +.Ldebug_loc2: + .byte 4 + .uleb128 .Ltmp2-.Lfunc_begin0 + .uleb128 .Ltmp5-.Lfunc_begin0 + .byte 3 + .byte 17 + .byte 0 + .byte 159 + .byte 4 + .uleb128 .Ltmp6-.Lfunc_begin0 + .uleb128 .Ltmp15-.Lfunc_begin0 + .byte 2 + .byte 144 + .byte 32 + .byte 0 +.Ldebug_loc3: + .byte 4 + .uleb128 .Ltmp8-.Lfunc_begin0 + .uleb128 .Ltmp11-.Lfunc_begin0 + .byte 3 + .byte 144 + .byte 130 + .byte 20 + .byte 0 +.Ldebug_list_header_end0: + .section .debug_abbrev,"",@progbits + .byte 1 + .byte 17 + .byte 1 + .byte 37 + .byte 37 + .byte 19 + .byte 5 + .byte 3 + .byte 37 + .byte 114 + .byte 23 + .byte 16 + .byte 23 + .byte 17 + .byte 27 + .byte 18 + .byte 6 + .byte 115 + .byte 23 + .byte 116 + .byte 23 + .ascii "\214\001" + .byte 23 + .byte 0 + .byte 0 + .byte 2 + .byte 52 + .byte 0 + .byte 3 + .byte 37 + .byte 73 + .byte 19 + .byte 63 + .byte 25 + .byte 58 + .byte 11 + .byte 59 + .byte 11 + .byte 110 + .byte 37 + .byte 0 + .byte 0 + .byte 3 + .byte 2 + .byte 1 + .byte 3 + .byte 37 + .byte 11 + .byte 11 + .byte 58 + .byte 11 + .byte 59 + .byte 11 + .ascii "\210\001" + .byte 15 + .byte 0 + .byte 0 + .byte 4 + .byte 47 + .byte 0 + .byte 73 + .byte 19 + .byte 3 + .byte 37 + .byte 0 + .byte 0 + .byte 5 + .byte 36 + .byte 0 + .byte 3 + .byte 37 + .byte 62 + .byte 11 + .byte 11 + .byte 11 + .byte 0 + .byte 0 + .byte 6 + .byte 46 + .byte 1 + .byte 17 + .byte 27 + .byte 18 + .byte 6 + .byte 3 + .byte 37 + .byte 58 + .byte 11 + .byte 59 + .byte 11 + .byte 63 + .byte 25 + .byte 0 + .byte 0 + .byte 7 + .byte 5 + .byte 0 + .byte 2 + .byte 34 + .byte 3 + .byte 37 + .byte 58 + .byte 11 + .byte 59 + .byte 11 + .byte 73 + .byte 19 + .byte 0 + .byte 0 + .byte 8 + .byte 52 + .byte 0 + .byte 2 + .byte 34 + .byte 3 + .byte 37 + .byte 58 + .byte 11 + .byte 59 + .byte 11 + .byte 73 + .byte 19 + .byte 0 + .byte 0 + .byte 9 + .byte 11 + .byte 1 + .byte 17 + .byte 27 + .byte 18 + .byte 6 + .byte 0 + .byte 0 + .byte 10 + .byte 11 + .byte 1 + .byte 85 + .byte 35 + .byte 0 + .byte 0 + .byte 11 + .byte 22 + .byte 0 + .byte 73 + .byte 19 + .byte 3 + .byte 37 + .byte 0 + .byte 0 + .byte 12 + .byte 2 + .byte 1 + .byte 3 + .byte 37 + .byte 11 + .byte 11 + .ascii "\210\001" + .byte 15 + .byte 0 + .byte 0 + .byte 13 + .byte 48 + .byte 0 + .byte 73 + .byte 19 + .byte 3 + .byte 37 + .byte 28 + .byte 13 + .byte 0 + .byte 0 + .byte 14 + .byte 13 + .byte 0 + .byte 3 + .byte 37 + .byte 73 + .byte 19 + .ascii "\210\001" + .byte 15 + .byte 56 + .byte 11 + .byte 50 + .byte 11 + .byte 0 + .byte 0 + .byte 0 + .section .debug_info,"",@progbits +.Lcu_begin0: + .long .Ldebug_info_end0-.Ldebug_info_start0 +.Ldebug_info_start0: + .short 5 + .byte 1 + .byte 8 + .long .debug_abbrev + .byte 1 + .byte 0 + .short 4 + .byte 1 + .long .Lstr_offsets_base0 + .long .Lline_table_start0 + .byte 0 + .long .Lfunc_end0-.Lfunc_begin0 + .long .Laddr_table_base0 + .long .Lrnglists_table_base0 + .long .Lloclists_table_base0 + .byte 2 + .byte 2 + .long 51 + + .byte 0 + .byte 1 + .byte 6 + .byte 3 + .byte 5 + .byte 4 + .byte 0 + .byte 1 + .byte 4 + .byte 4 + .long 64 + .byte 4 + .byte 0 + .byte 5 + .byte 3 + .byte 4 + .byte 4 + .byte 2 + .byte 7 + .long 51 + + .byte 0 + .byte 2 + .byte 8 + .byte 6 + .byte 0 + .long .Lfunc_end0-.Lfunc_begin0 + .byte 9 + .byte 0 + .byte 6 + + .byte 7 + .byte 0 + .byte 10 + .byte 0 + .byte 6 + .long 133 + .byte 8 + .byte 1 + .byte 19 + .byte 0 + .byte 7 + .long 64 + .byte 9 + .byte 1 + .long .Ltmp16-.Ltmp3 + .byte 8 + .byte 2 + .byte 20 + .byte 0 + .byte 9 + .long 188 + .byte 10 + .byte 0 + .byte 8 + .byte 3 + .byte 21 + .byte 0 + .byte 10 + .long 64 + .byte 0 + .byte 0 + .byte 0 + .byte 11 + .long 139 + .byte 18 + .byte 12 + .byte 17 + .byte 12 + .byte 4 + .byte 4 + .long 184 + .byte 4 + .byte 13 + .long 188 + .byte 13 + .byte 3 + .byte 14 + .byte 14 + .long 184 + .byte 4 + .byte 0 + .byte 1 + .byte 14 + .byte 15 + .long 184 + .byte 4 + .byte 4 + .byte 1 + .byte 14 + .byte 16 + .long 184 + .byte 4 + .byte 8 + .byte 1 + .byte 0 + .byte 5 + .byte 11 + .byte 7 + .byte 4 + .byte 5 + .byte 12 + .byte 5 + .byte 4 + .byte 0 +.Ldebug_info_end0: + .section .debug_rnglists,"",@progbits + .long .Ldebug_list_header_end1-.Ldebug_list_header_start1 +.Ldebug_list_header_start1: + .short 5 + .byte 8 + .byte 0 + .long 1 +.Lrnglists_table_base0: + .long .Ldebug_ranges0-.Lrnglists_table_base0 +.Ldebug_ranges0: + .byte 4 + .uleb128 .Ltmp7-.Lfunc_begin0 + .uleb128 .Ltmp9-.Lfunc_begin0 + .byte 4 + .uleb128 .Ltmp14-.Lfunc_begin0 + .uleb128 .Ltmp16-.Lfunc_begin0 + .byte 0 +.Ldebug_list_header_end1: + .section .debug_str_offsets,"",@progbits + .long 92 + .short 5 + .short 0 +.Lstr_offsets_base0: + .section .debug_str,"MS",@progbits,1 +.Linfo_string0: + .asciz "dxc" +.Linfo_string1: + .asciz "test.hlsl" +.Linfo_string2: + .asciz "u0" +.Linfo_string3: + .asciz "RWBuffer<float>" +.Linfo_string4: + .asciz "float" +.Linfo_string5: + .asciz "element" +.Linfo_string6: + .asciz "?u0@@3V?$RWBuffer@M@@A" +.Linfo_string7: + .asciz "u1" +.Linfo_string8: + .asciz "?u1@@3V?$RWBuffer@M@@A" +.Linfo_string9: + .asciz "main" +.Linfo_string10: + .asciz "dtid" +.Linfo_string11: + .asciz "uint3" +.Linfo_string12: + .asciz "vector<unsigned int, 3>" +.Linfo_string13: + .asciz "unsigned int" +.Linfo_string14: + .asciz "int" +.Linfo_string15: + .asciz "element_count" +.Linfo_string16: + .asciz "x" +.Linfo_string17: + .asciz "y" +.Linfo_string18: + .asciz "z" +.Linfo_string19: + .asciz "my_var" +.Linfo_string20: + .asciz "i" +.Linfo_string21: + .asciz "my_local_var" + .section .debug_str_offsets,"",@progbits + .long .Linfo_string0 + .long .Linfo_string1 + .long .Linfo_string2 + .long .Linfo_string4 + .long .Linfo_string5 + .long .Linfo_string3 + .long .Linfo_string6 + .long .Linfo_string7 + .long .Linfo_string8 + .long .Linfo_string9 + .long .Linfo_string10 + .long .Linfo_string13 + .long .Linfo_string14 + .long .Linfo_string15 + .long .Linfo_string16 + .long .Linfo_string17 + .long .Linfo_string18 + .long .Linfo_string12 + .long .Linfo_string11 + .long .Linfo_string19 + .long .Linfo_string20 + .long .Linfo_string21 + .section .debug_addr,"",@progbits + .long .Ldebug_addr_end0-.Ldebug_addr_start0 +.Ldebug_addr_start0: + .short 5 + .byte 8 + .byte 0 +.Laddr_table_base0: + .quad .Lfunc_begin0 + .quad .Ltmp3 +.Ldebug_addr_end0: + .section .debug_names,"",@progbits + .section ".note.GNU-stack","",@progbits + .section .debug_line,"",@progbits +.Lline_table_start0: diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/high_pc_exclusive.s b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/high_pc_exclusive.s new file mode 100644 index 0000000..a9a9016 --- /dev/null +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/high_pc_exclusive.s @@ -0,0 +1,278 @@ +# Regression test for: +# - Instructions at DW_AT_high_pc of a scope incorrectly included in the scope + +# clang test.cpp --target=i686-pc-linux -g -O0 +# 1 +# 2 int main(void) { +# 3 float ret = 0; +# 4 for (int i = 0; i < 10; i++) { +# 5 ret += i; +# 6 } +# 7 return ret; +# 8 } +# 9 + +# REQUIRES: x86-registered-target + +# RUN: llvm-mc %s -triple=i686-pc-linux -filetype=obj -o - | \ +# RUN: llvm-debuginfo-analyzer --attribute=all \ +# RUN: --print=all \ +# RUN: --output-sort=offset \ +# RUN: - | \ +# RUN: FileCheck %s + +# Make sure the line mapping at 0x3c does not show up at the scope level 004 +# CHECK-NOT: [0x000000003c][004] 7 {Line} + +# Make sure it *does* appear at scope level 003 +# CHECK: [0x000000003c][003] 7 {Line} + + .file "compile.cpp" + .text + .globl main # -- Begin function main + .p2align 4 + .type main,@function +main: # @main +.Lfunc_begin0: + .file 0 "test.cpp" + .loc 0 2 0 + .cfi_startproc +# %bb.0: # %entry + pushl %ebp + .cfi_def_cfa_offset 8 + .cfi_offset %ebp, -8 + movl %esp, %ebp + .cfi_def_cfa_register %ebp + subl $12, %esp + movl $0, -4(%ebp) +.Ltmp0: + .loc 0 3 15 prologue_end + xorps %xmm0, %xmm0 + movss %xmm0, -8(%ebp) +.Ltmp1: + .loc 0 4 18 + movl $0, -12(%ebp) +.LBB0_1: # %for.cond + # =>This Inner Loop Header: Depth=1 +.Ltmp2: + .loc 0 4 27 is_stmt 0 + cmpl $10, -12(%ebp) +.Ltmp3: + .loc 0 4 9 + jge .LBB0_4 +# %bb.2: # %for.body + # in Loop: Header=BB0_1 Depth=1 +.Ltmp4: + .loc 0 5 18 is_stmt 1 + cvtsi2ssl -12(%ebp), %xmm0 + .loc 0 5 15 is_stmt 0 + addss -8(%ebp), %xmm0 + movss %xmm0, -8(%ebp) +.Ltmp5: +# %bb.3: # %for.inc + # in Loop: Header=BB0_1 Depth=1 + .loc 0 4 34 is_stmt 1 + movl -12(%ebp), %eax + addl $1, %eax + movl %eax, -12(%ebp) + .loc 0 4 9 is_stmt 0 + jmp .LBB0_1 +.Ltmp6: +.LBB0_4: # %for.end + .loc 0 7 16 is_stmt 1 + cvttss2si -8(%ebp), %eax + .loc 0 7 9 epilogue_begin is_stmt 0 + addl $12, %esp + popl %ebp + .cfi_def_cfa %esp, 4 + retl +.Ltmp7: +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 1 # DW_CHILDREN_yes + .byte 37 # DW_AT_producer + .byte 37 # DW_FORM_strx1 + .byte 19 # DW_AT_language + .byte 5 # DW_FORM_data2 + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 114 # DW_AT_str_offsets_base + .byte 23 # DW_FORM_sec_offset + .byte 16 # DW_AT_stmt_list + .byte 23 # DW_FORM_sec_offset + .byte 27 # DW_AT_comp_dir + .byte 37 # DW_FORM_strx1 + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 115 # DW_AT_addr_base + .byte 23 # DW_FORM_sec_offset + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 2 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 1 # DW_CHILDREN_yes + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 64 # DW_AT_frame_base + .byte 24 # DW_FORM_exprloc + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 3 # Abbreviation Code + .byte 52 # DW_TAG_variable + .byte 0 # DW_CHILDREN_no + .byte 2 # DW_AT_location + .byte 24 # DW_FORM_exprloc + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 4 # Abbreviation Code + .byte 11 # DW_TAG_lexical_block + .byte 1 # DW_CHILDREN_yes + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 5 # Abbreviation Code + .byte 36 # DW_TAG_base_type + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 62 # DW_AT_encoding + .byte 11 # DW_FORM_data1 + .byte 11 # DW_AT_byte_size + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + .section .debug_info,"",@progbits +.Lcu_begin0: + .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit +.Ldebug_info_start0: + .short 5 # DWARF version number + .byte 1 # DWARF Unit Type + .byte 4 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + .byte 1 # Abbrev [1] 0xc:0x4d DW_TAG_compile_unit + .byte 0 # DW_AT_producer + .short 33 # DW_AT_language + .byte 1 # DW_AT_name + .long .Lstr_offsets_base0 # DW_AT_str_offsets_base + .long .Lline_table_start0 # DW_AT_stmt_list + .byte 2 # DW_AT_comp_dir + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .long .Laddr_table_base0 # DW_AT_addr_base + .byte 2 # Abbrev [2] 0x23:0x2d DW_TAG_subprogram + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .byte 1 # DW_AT_frame_base + .byte 85 + .byte 3 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 2 # DW_AT_decl_line + .long 80 # DW_AT_type + # DW_AT_external + .byte 3 # Abbrev [3] 0x32:0xb DW_TAG_variable + .byte 2 # DW_AT_location + .byte 145 + .byte 120 + .byte 5 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 3 # DW_AT_decl_line + .long 84 # DW_AT_type + .byte 4 # Abbrev [4] 0x3d:0x12 DW_TAG_lexical_block + .byte 1 # DW_AT_low_pc + .long .Ltmp6-.Ltmp1 # DW_AT_high_pc + .byte 3 # Abbrev [3] 0x43:0xb DW_TAG_variable + .byte 2 # DW_AT_location + .byte 145 + .byte 116 + .byte 7 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 4 # DW_AT_decl_line + .long 80 # DW_AT_type + .byte 0 # End Of Children Mark + .byte 0 # End Of Children Mark + .byte 5 # Abbrev [5] 0x50:0x4 DW_TAG_base_type + .byte 4 # DW_AT_name + .byte 5 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 5 # Abbrev [5] 0x54:0x4 DW_TAG_base_type + .byte 6 # DW_AT_name + .byte 4 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 0 # End Of Children Mark +.Ldebug_info_end0: + .section .debug_str_offsets,"",@progbits + .long 36 # Length of String Offsets Set + .short 5 + .short 0 +.Lstr_offsets_base0: + .section .debug_str,"MS",@progbits,1 +.Linfo_string0: + .asciz "clang version 22.0.0" # string offset=0 +.Linfo_string1: + .asciz "test.cpp" # string offset=113 +.Linfo_string2: + .asciz "F:\\llvm-project" # string offset=142 +.Linfo_string3: + .asciz "main" # string offset=158 +.Linfo_string4: + .asciz "int" # string offset=163 +.Linfo_string5: + .asciz "ret" # string offset=167 +.Linfo_string6: + .asciz "float" # string offset=171 +.Linfo_string7: + .asciz "i" # string offset=177 + .section .debug_str_offsets,"",@progbits + .long .Linfo_string0 + .long .Linfo_string1 + .long .Linfo_string2 + .long .Linfo_string3 + .long .Linfo_string4 + .long .Linfo_string5 + .long .Linfo_string6 + .long .Linfo_string7 + .section .debug_addr,"",@progbits + .long .Ldebug_addr_end0-.Ldebug_addr_start0 # Length of contribution +.Ldebug_addr_start0: + .short 5 # DWARF version number + .byte 4 # Address size + .byte 0 # Segment selector size +.Laddr_table_base0: + .long .Lfunc_begin0 + .long .Ltmp1 +.Ldebug_addr_end0: + .ident "clang version 22.0.0" + .section ".note.GNU-stack","",@progbits + .section .debug_line,"",@progbits +.Lline_table_start0: diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/pr-incorrect-logical-instructions.test b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/pr-incorrect-logical-instructions.test index a99eae2..b38db28 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/pr-incorrect-logical-instructions.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/DWARF/pr-incorrect-logical-instructions.test @@ -84,7 +84,6 @@ ; ONE-NEXT: [003] {Code} 'addq $0x10, %rsp' ; ONE-NEXT: [003] {Code} 'popq %rbp' ; ONE-NEXT: [003] {Code} 'retq' -; ONE-NEXT: [003] {Code} 'data16' ; ONE-NEXT: [002] 10 {Function} extern not_inlined 'test' -> 'int' ; ONE-NEXT: [003] {Block} ; ONE-NEXT: [004] 13 {Line} @@ -106,8 +105,6 @@ ; ONE-NEXT: [004] {Code} 'movl -0x8(%rbp), %eax' ; ONE-NEXT: [004] {Code} 'addl $0x1, %eax' ; ONE-NEXT: [004] {Code} 'movl %eax, -0x8(%rbp)' -; ONE-NEXT: [004] 17 {Line} -; ONE-NEXT: [004] {Code} 'movl -0x8(%rbp), %eax' ; ONE-NEXT: [003] 10 {Line} ; ONE-NEXT: [003] {Code} 'pushq %rbp' ; ONE-NEXT: [003] {Code} 'movq %rsp, %rbp' @@ -120,6 +117,8 @@ ; ONE-NEXT: [003] 11 {Line} ; ONE-NEXT: [003] {Code} 'movl %eax, -0x8(%rbp)' ; ONE-NEXT: [003] 17 {Line} +; ONE-NEXT: [003] {Code} 'movl -0x8(%rbp), %eax' +; ONE-NEXT: [003] 17 {Line} ; ONE-NEXT: [003] {Code} 'addq $0x10, %rsp' ; ONE-NEXT: [003] {Code} 'popq %rbp' ; ONE-NEXT: [003] {Code} 'retq' @@ -132,7 +131,8 @@ ; ONE-NEXT: [003] {Code} 'xorl %eax, %eax' ; ONE-NEXT: [003] {Code} 'popq %rbp' ; ONE-NEXT: [003] {Code} 'retq' -; ONE-NEXT: [003] 21 {Line} +; ONE-NEXT: [002] {Code} 'data16' +; ONE-NEXT: [002] 21 {Line} ; RUN: llvm-debuginfo-analyzer --attribute=level \ ; RUN: --print=instructions \ @@ -172,7 +172,6 @@ ; TWO-NEXT: [003] {Code} 'addq $0x10, %rsp' ; TWO-NEXT: [003] {Code} 'popq %rbp' ; TWO-NEXT: [003] {Code} 'retq' -; TWO-NEXT: [003] {Code} 'data16' ; TWO-NEXT: [002] 10 {Function} extern not_inlined 'test' -> 'int' ; TWO-NEXT: [003] {Block} ; TWO-NEXT: [004] {Code} 'movl $0x0, -0xc(%rbp)' @@ -187,7 +186,6 @@ ; TWO-NEXT: [004] {Code} 'movl -0x8(%rbp), %eax' ; TWO-NEXT: [004] {Code} 'addl $0x1, %eax' ; TWO-NEXT: [004] {Code} 'movl %eax, -0x8(%rbp)' -; TWO-NEXT: [004] {Code} 'movl -0x8(%rbp), %eax' ; TWO-NEXT: [003] {Code} 'pushq %rbp' ; TWO-NEXT: [003] {Code} 'movq %rsp, %rbp' ; TWO-NEXT: [003] {Code} 'subq $0x10, %rsp' @@ -195,6 +193,7 @@ ; TWO-NEXT: [003] {Code} 'movl -0x4(%rbp), %eax' ; TWO-NEXT: [003] {Code} 'subl (%rip), %eax' ; TWO-NEXT: [003] {Code} 'movl %eax, -0x8(%rbp)' +; TWO-NEXT: [003] {Code} 'movl -0x8(%rbp), %eax' ; TWO-NEXT: [003] {Code} 'addq $0x10, %rsp' ; TWO-NEXT: [003] {Code} 'popq %rbp' ; TWO-NEXT: [003] {Code} 'retq' diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/01-wasm-print-basic-details.test b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/01-wasm-print-basic-details.test index 4927086..183e3dd 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/01-wasm-print-basic-details.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/01-wasm-print-basic-details.test @@ -56,8 +56,6 @@ ; ONE-NEXT: [004] {Code} 'local.get 11' ; ONE-NEXT: [004] {Code} 'i32.store 28' ; ONE-NEXT: [004] {Code} 'br 1' -; ONE-NEXT: [004] - {Line} -; ONE-NEXT: [004] {Code} 'end' ; ONE-NEXT: [003] 4 {TypeAlias} 'INTEGER' -> 'int' ; ONE-NEXT: [003] 2 {Line} ; ONE-NEXT: [003] {Code} 'nop' @@ -98,6 +96,8 @@ ; ONE-NEXT: [003] {Code} 'local.get 9' ; ONE-NEXT: [003] {Code} 'i32.eqz' ; ONE-NEXT: [003] {Code} 'br_if 0' +; ONE-NEXT: [003] - {Line} +; ONE-NEXT: [003] {Code} 'end' ; ONE-NEXT: [003] 8 {Line} ; ONE-NEXT: [003] {Code} 'local.get 5' ; ONE-NEXT: [003] {Code} 'i32.load 20' @@ -115,6 +115,6 @@ ; ONE-NEXT: [003] {Code} 'local.get 13' ; ONE-NEXT: [003] {Code} 'return' ; ONE-NEXT: [003] {Code} 'end' -; ONE-NEXT: [003] 9 {Line} -; ONE-NEXT: [003] {Code} 'unreachable' ; ONE-NEXT: [002] 1 {TypeAlias} 'INTPTR' -> '* const int' +; ONE-NEXT: [002] 9 {Line} +; ONE-NEXT: [002] {Code} 'unreachable' diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/02-wasm-logical-lines.test b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/02-wasm-logical-lines.test index 50a531a..8d76464 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/02-wasm-logical-lines.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/02-wasm-logical-lines.test @@ -71,5 +71,5 @@ ; ONE-NEXT: [003] {Code} 'local.get 6' ; ONE-NEXT: [003] {Code} 'return' ; ONE-NEXT: [003] {Code} 'end' -; ONE-NEXT: [003] 6 {Line} -; ONE-NEXT: [003] {Code} 'return' +; ONE-NEXT: [002] 6 {Line} +; ONE-NEXT: [002] {Code} 'return' diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/03-wasm-incorrect-lexical-scope-typedef.test b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/03-wasm-incorrect-lexical-scope-typedef.test index 1192a0cb..a89d49a 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/03-wasm-incorrect-lexical-scope-typedef.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/03-wasm-incorrect-lexical-scope-typedef.test @@ -55,7 +55,6 @@ ; ONE-NEXT: [003] - {Line} ; ONE-NEXT: [003] 1 {Line} ; ONE-NEXT: [003] 1 {Line} -; ONE-NEXT: [003] 1 {Line} ; ONE-NEXT: [002] 3 {Function} extern not_inlined 'foo' -> 'unsigned int' ; ONE-NEXT: [003] {Block} ; ONE-NEXT: [004] 9 {Variable} 'Added' -> 'FLOAT' @@ -67,7 +66,6 @@ ; ONE-NEXT: [004] 10 {Line} ; ONE-NEXT: [004] 10 {Line} ; ONE-NEXT: [004] 10 {Line} -; ONE-NEXT: [004] 13 {Line} ; ONE-NEXT: [003] 3 {Parameter} 'Param' -> 'char' ; ONE-NEXT: [003] 7 {TypeAlias} 'FLOAT' -> 'float' ; ONE-NEXT: [003] 4 {TypeAlias} 'INT' -> 'int' @@ -79,6 +77,8 @@ ; ONE-NEXT: [003] 13 {Line} ; ONE-NEXT: [003] 13 {Line} ; ONE-NEXT: [003] 13 {Line} +; ONE-NEXT: [002] 1 {Line} +; ONE-NEXT: [002] 13 {Line} ; ONE-EMPTY: ; ONE-NEXT: Logical View: ; ONE-NEXT: [000] {File} 'pr-44884-dwarf-gcc.o' -> elf64-x86-64 @@ -99,7 +99,6 @@ ; ONE-NEXT: [005] 9 {Line} ; ONE-NEXT: [005] 9 {Line} ; ONE-NEXT: [005] 10 {Line} -; ONE-NEXT: [005] 13 {Line} ; ONE-NEXT: [004] 7 {TypeAlias} 'FLOAT' -> 'float' ; ONE-NEXT: [003] 3 {Parameter} 'Param' -> 'char' ; ONE-NEXT: [003] 4 {TypeAlias} 'INT' -> 'int' @@ -107,8 +106,9 @@ ; ONE-NEXT: [003] 3 {Line} ; ONE-NEXT: [003] 5 {Line} ; ONE-NEXT: [003] 13 {Line} +; ONE-NEXT: [003] 13 {Line} ; ONE-NEXT: [003] 14 {Line} -; ONE-NEXT: [003] 14 {Line} +; ONE-NEXT: [002] 14 {Line} ; Using the selection facilities, we can produce a simple tabular ; output showing just the logical types that are 'Typedef'. diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/06-wasm-full-logical-view.test b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/06-wasm-full-logical-view.test index ac4873f..e152f40 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/06-wasm-full-logical-view.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/WebAssembly/06-wasm-full-logical-view.test @@ -64,8 +64,6 @@ ; ONE-NEXT: [0x000000005d][004] {Code} 'local.get 11' ; ONE-NEXT: [0x000000005f][004] {Code} 'i32.store 28' ; ONE-NEXT: [0x0000000062][004] {Code} 'br 1' -; ONE-NEXT: [0x0000000064][004] 0 {Line} '{{.*}}/general/test.cpp' -; ONE-NEXT: [0x0000000064][004] {Code} 'end' ; ONE-NEXT: [0x000000005e][003] 2 {Parameter} 'ParamBool' -> [0x00000000b3]'bool' ; ONE-NEXT: [0x000000005e][004] {Coverage} 100.00% ; ONE-NEXT: [0x000000005f][004] {Location} @@ -118,6 +116,8 @@ ; ONE-NEXT: [0x0000000047][003] {Code} 'local.get 9' ; ONE-NEXT: [0x0000000049][003] {Code} 'i32.eqz' ; ONE-NEXT: [0x000000004a][003] {Code} 'br_if 0' +; ONE-NEXT: [0x0000000064][003] 0 {Line} '{{.*}}/general/test.cpp' +; ONE-NEXT: [0x0000000064][003] {Code} 'end' ; ONE-NEXT: [0x0000000065][003] 8 {Line} {NewStatement} '{{.*}}/general/test.cpp' ; ONE-NEXT: [0x0000000065][003] {Code} 'local.get 5' ; ONE-NEXT: [0x0000000067][003] {Code} 'i32.load 20' @@ -135,8 +135,8 @@ ; ONE-NEXT: [0x000000007b][003] {Code} 'local.get 13' ; ONE-NEXT: [0x000000007d][003] {Code} 'return' ; ONE-NEXT: [0x000000007e][003] {Code} 'end' -; ONE-NEXT: [0x000000007f][003] 9 {Line} {NewStatement} {EndSequence} '{{.*}}/general/test.cpp' -; ONE-NEXT: [0x000000007f][003] {Code} 'unreachable' +; ONE-NEXT: [0x000000007f][002] 9 {Line} {NewStatement} {EndSequence} '{{.*}}/general/test.cpp' +; ONE-NEXT: [0x000000007f][002] {Code} 'unreachable' ; ONE-EMPTY: ; ONE-NEXT: ----------------------------- ; ONE-NEXT: Element Total Printed diff --git a/llvm/test/tools/llvm-dwarfutil/ELF/X86/mirror-permissions-unix.test b/llvm/test/tools/llvm-dwarfutil/ELF/X86/mirror-permissions-unix.test index a95d1c0..fdcba4d 100644 --- a/llvm/test/tools/llvm-dwarfutil/ELF/X86/mirror-permissions-unix.test +++ b/llvm/test/tools/llvm-dwarfutil/ELF/X86/mirror-permissions-unix.test @@ -3,7 +3,6 @@ ## Setting the umask to 0 ensures deterministic permissions across ## test environments. # UNSUPPORTED: system-windows -# REQUIRES: shell # RUN: touch %t # RUN: chmod 0777 %t diff --git a/llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s b/llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s new file mode 100644 index 0000000..7cd088f --- /dev/null +++ b/llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s @@ -0,0 +1,21 @@ +REQUIRES: aarch64-registered-target, asserts + +RUN: llvm-exegesis -mcpu=neoverse-v2 --use-dummy-perf-counters --min-instructions=100 --mode=latency --debug-only=preview-gen-assembly --opcode-name=ADDVv4i16v 2>&1 | FileCheck %s -check-prefix=PREVIEW + +PREVIEW: Generated assembly snippet: +PREVIEW-NEXT: ``` +PREVIEW: {{[04]}}: {{.*}} movi d{{[0-9]+}}, #0000000000000000 +PREVIEW-NEXT: {{[48]}}: {{.*}} addv h{{[0-9]+}}, v{{[0-9]+}}.4h +PREVIEW: ... ({{[0-9]+}} more instructions) +PREVIEW-NEXT: {{.*}} addv h{{[0-9]+}}, v{{[0-9]+}}.4h +PREVIEW: {{.*}} ret +PREVIEW-NEXT:``` + +RUN: llvm-exegesis -mcpu=neoverse-v2 --use-dummy-perf-counters --min-instructions=100 --mode=latency --debug-only=print-gen-assembly --opcode-name=ADDVv4i16v 2>&1 | FileCheck %s -check-prefix=PRINT +PRINT: Generated assembly snippet: +PRINT-NEXT: ``` +PRINT: {{[04]}}: {{.*}} movi d{{[0-9]+}}, #0000000000000000 +PRINT-NEXT: {{[48]}}: {{.*}} addv h{{[0-9]+}}, v{{[0-9]+}}.4h +PRINT-NEXT: {{.*}} addv h{{[0-9]+}}, v{{[0-9]+}}.4h +PRINT: {{.*}} ret +PRINT-NEXT:``` diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s new file mode 100644 index 0000000..168cc585 --- /dev/null +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -0,0 +1,78 @@ +# REQUIRES: aarch64-registered-target + + + +// Test for omitting OperandType::OPERAND_SHIFT_MSL + +// MOVIv2s_msl: MOVI vd, #imm{, shift} +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_throughput +# MOVIv4s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv4s_msl opcode + +// TODO: Add test to check if the immediate value is correct when serial execution strategy is added for MOVIv4s_msl + + +# MOVIv4s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv4s_msl opcode +# MOVIv4s_msl_throughput: --- +# MOVIv4s_msl_throughput-NEXT: mode: inverse_throughput +# MOVIv4s_msl_throughput-NEXT: key: +# MOVIv4s_msl_throughput-NEXT: instructions: +# MOVIv4s_msl_throughput-NEXT: MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x108 +# MOVIv4s_msl_throughput: ... + +// MOVIv2s_msl: MOVI vd, #imm{, shift} +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput +# MOVIv2s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode + +// TODO: Add test to check if the immediate value is correct when serial execution strategy is added for MOVIv2s_msl + + +# MOVIv2s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode +# MOVIv2s_msl_throughput: --- +# MOVIv2s_msl_throughput-NEXT: mode: inverse_throughput +# MOVIv2s_msl_throughput-NEXT: key: +# MOVIv2s_msl_throughput-NEXT: instructions: +# MOVIv2s_msl_throughput-NEXT: MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x108 +# MOVIv2s_msl_throughput: ... + + + +// Test for omitting OperandType::OPERAND_PCREL +// LDRDl: LDRD ldr1, ldr2, [pc, #imm] +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_throughput + +# LDRDl_latency-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes +# LDRDl_throughput-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes + +# LDRDl_throughput: --- +# LDRDl_throughput-NEXT: mode: inverse_throughput +# LDRDl_throughput-NEXT: key: +# LDRDl_throughput-NEXT: instructions: +# LDRDl_throughput-NEXT: LDRDl [[REG1:D[0-9]+|LR]] i_0x8 +# LDRDl_throughput: ... + + + +// Test for omitting OperandType::OPERAND_IMPLICIT_IMM_0 + +// UMOVvi16_idx0: UMOV wd, vn.h[index] +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_throughput + +# UMOVvi16_idx0_latency-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode +# UMOVvi16_idx0_latency: --- +# UMOVvi16_idx0_latency-NEXT: mode: latency +# UMOVvi16_idx0_latency-NEXT: key: +# UMOVvi16_idx0_latency-NEXT: instructions: +# UMOVvi16_idx0_latency-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0 +# UMOVvi16_idx0_latency: ... + +# UMOVvi16_idx0_throughput-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode +# UMOVvi16_idx0_throughput: --- +# UMOVvi16_idx0_throughput-NEXT: mode: inverse_throughput +# UMOVvi16_idx0_throughput-NEXT: key: +# UMOVvi16_idx0_throughput-NEXT: instructions: +# UMOVvi16_idx0_throughput-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0 +# UMOVvi16_idx0_throughput: ... diff --git a/llvm/test/tools/llvm-exegesis/AArch64/loop-register.s b/llvm/test/tools/llvm-exegesis/AArch64/loop-register.s new file mode 100644 index 0000000..db8f7a0 --- /dev/null +++ b/llvm/test/tools/llvm-exegesis/AArch64/loop-register.s @@ -0,0 +1,23 @@ +; FIXME: this test fails with a stage2 build, in which case it seems to +; generate extra function prologue instructions that interfere with matching +; the STR of X19. Disable this for now. +; +; UNSUPPORTED: target={{.*}} + +REQUIRES: aarch64-registered-target, asserts + +RUN: llvm-exegesis -mcpu=neoverse-v2 --use-dummy-perf-counters --mode=latency --debug-only=print-gen-assembly --opcode-name=ADDVv4i16v -repetition-mode=loop 2>&1 | FileCheck %s + +CHECK: str x19, [sp, #-16]! +CHECK-NEXT: movi d[[REG:[0-9]+]], #0000000000000000 +CHECK-NEXT: mov x19, #10000 +CHECK-NEXT: nop +CHECK-NEXT: nop +CHECK-NEXT: nop +CHECK-NEXT: nop +CHECK-NEXT: nop +CHECK-NEXT: addv h[[REG]], v[[REG]].4h +CHECK-NEXT: subs x19, x19, #1 +CHECK-NEXT: b.ne #-8 +CHECK-NEXT: ldr x19, [sp], #16 +CHECK-NEXT: ret diff --git a/llvm/test/tools/llvm-ir2vec/embeddings-flowaware.ll b/llvm/test/tools/llvm-ir2vec/embeddings-flowaware.ll new file mode 100644 index 0000000..b2362f8 --- /dev/null +++ b/llvm/test/tools/llvm-ir2vec/embeddings-flowaware.ll @@ -0,0 +1,73 @@ +; RUN: llvm-ir2vec embeddings --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-DEFAULT +; RUN: llvm-ir2vec embeddings --level=func --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-FUNC-LEVEL +; RUN: llvm-ir2vec embeddings --level=func --function=abc --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-FUNC-LEVEL-ABC +; RUN: not llvm-ir2vec embeddings --level=func --function=def --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s 2>&1 | FileCheck %s -check-prefix=CHECK-FUNC-DEF +; RUN: llvm-ir2vec embeddings --level=bb --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-BB-LEVEL +; RUN: llvm-ir2vec embeddings --level=bb --function=abc_repeat --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-BB-LEVEL-ABC-REPEAT +; RUN: llvm-ir2vec embeddings --level=inst --function=abc_repeat --ir2vec-kind=flow-aware --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-INST-LEVEL-ABC-REPEAT + +define dso_local noundef float @abc(i32 noundef %a, float noundef %b) #0 { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca float, align 4 + store i32 %a, ptr %a.addr, align 4 + store float %b, ptr %b.addr, align 4 + %0 = load i32, ptr %a.addr, align 4 + %1 = load i32, ptr %a.addr, align 4 + %mul = mul nsw i32 %0, %1 + %conv = sitofp i32 %mul to float + %2 = load float, ptr %b.addr, align 4 + %add = fadd float %conv, %2 + ret float %add +} + +define dso_local noundef float @abc_repeat(i32 noundef %a, float noundef %b) #0 { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca float, align 4 + store i32 %a, ptr %a.addr, align 4 + store float %b, ptr %b.addr, align 4 + %0 = load i32, ptr %a.addr, align 4 + %1 = load i32, ptr %a.addr, align 4 + %mul = mul nsw i32 %0, %1 + %conv = sitofp i32 %mul to float + %2 = load float, ptr %b.addr, align 4 + %add = fadd float %conv, %2 + ret float %add +} + +; CHECK-DEFAULT: Function: abc +; CHECK-DEFAULT-NEXT: [ 3630.00 3672.00 3714.00 ] +; CHECK-DEFAULT-NEXT: Function: abc_repeat +; CHECK-DEFAULT-NEXT: [ 3630.00 3672.00 3714.00 ] + +; CHECK-FUNC-LEVEL: Function: abc +; CHECK-FUNC-LEVEL-NEXT: [ 3630.00 3672.00 3714.00 ] +; CHECK-FUNC-LEVEL-NEXT: Function: abc_repeat +; CHECK-FUNC-LEVEL-NEXT: [ 3630.00 3672.00 3714.00 ] + +; CHECK-FUNC-LEVEL-ABC: Function: abc +; CHECK-FUNC-LEVEL-NEXT-ABC: [ 3630.00 3672.00 3714.00 ] + +; CHECK-FUNC-DEF: Error: Function 'def' not found + +; CHECK-BB-LEVEL: Function: abc +; CHECK-BB-LEVEL-NEXT: entry: [ 3630.00 3672.00 3714.00 ] +; CHECK-BB-LEVEL-NEXT: Function: abc_repeat +; CHECK-BB-LEVEL-NEXT: entry: [ 3630.00 3672.00 3714.00 ] + +; CHECK-BB-LEVEL-ABC-REPEAT: Function: abc_repeat +; CHECK-BB-LEVEL-ABC-REPEAT-NEXT: entry: [ 3630.00 3672.00 3714.00 ] + +; CHECK-INST-LEVEL-ABC-REPEAT: Function: abc_repeat +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %a.addr = alloca i32, align 4 [ 91.00 92.00 93.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %b.addr = alloca float, align 4 [ 91.00 92.00 93.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: store i32 %a, ptr %a.addr, align 4 [ 188.00 190.00 192.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: store float %b, ptr %b.addr, align 4 [ 188.00 190.00 192.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %0 = load i32, ptr %a.addr, align 4 [ 185.00 187.00 189.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %1 = load i32, ptr %a.addr, align 4 [ 185.00 187.00 189.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %mul = mul nsw i32 %0, %1 [ 419.00 424.00 429.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %conv = sitofp i32 %mul to float [ 549.00 555.00 561.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %2 = load float, ptr %b.addr, align 4 [ 185.00 187.00 189.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: %add = fadd float %conv, %2 [ 774.00 783.00 792.00 ] +; CHECK-INST-LEVEL-ABC-REPEAT-NEXT: ret float %add [ 775.00 785.00 795.00 ] diff --git a/llvm/test/tools/llvm-ir2vec/embeddings.ll b/llvm/test/tools/llvm-ir2vec/embeddings-symbolic.ll index f9aa108..f9aa108 100644 --- a/llvm/test/tools/llvm-ir2vec/embeddings.ll +++ b/llvm/test/tools/llvm-ir2vec/embeddings-symbolic.ll diff --git a/llvm/test/tools/llvm-ir2vec/entities.ll b/llvm/test/tools/llvm-ir2vec/entities.ll index 737044c..4b51adf 100644 --- a/llvm/test/tools/llvm-ir2vec/entities.ll +++ b/llvm/test/tools/llvm-ir2vec/entities.ll @@ -1,6 +1,6 @@ ; RUN: llvm-ir2vec entities | FileCheck %s -CHECK: 92 +CHECK: 84 CHECK-NEXT: Ret 0 CHECK-NEXT: Br 1 CHECK-NEXT: Switch 2 @@ -48,48 +48,40 @@ CHECK-NEXT: SIToFP 43 CHECK-NEXT: FPTrunc 44 CHECK-NEXT: FPExt 45 CHECK-NEXT: PtrToInt 46 -CHECK-NEXT: IntToPtr 47 -CHECK-NEXT: BitCast 48 -CHECK-NEXT: AddrSpaceCast 49 -CHECK-NEXT: CleanupPad 50 -CHECK-NEXT: CatchPad 51 -CHECK-NEXT: ICmp 52 -CHECK-NEXT: FCmp 53 -CHECK-NEXT: PHI 54 -CHECK-NEXT: Call 55 -CHECK-NEXT: Select 56 -CHECK-NEXT: UserOp1 57 -CHECK-NEXT: UserOp2 58 -CHECK-NEXT: VAArg 59 -CHECK-NEXT: ExtractElement 60 -CHECK-NEXT: InsertElement 61 -CHECK-NEXT: ShuffleVector 62 -CHECK-NEXT: ExtractValue 63 -CHECK-NEXT: InsertValue 64 -CHECK-NEXT: LandingPad 65 -CHECK-NEXT: Freeze 66 -CHECK-NEXT: FloatTy 67 +CHECK-NEXT: PtrToAddr 47 +CHECK-NEXT: IntToPtr 48 +CHECK-NEXT: BitCast 49 +CHECK-NEXT: AddrSpaceCast 50 +CHECK-NEXT: CleanupPad 51 +CHECK-NEXT: CatchPad 52 +CHECK-NEXT: ICmp 53 +CHECK-NEXT: FCmp 54 +CHECK-NEXT: PHI 55 +CHECK-NEXT: Call 56 +CHECK-NEXT: Select 57 +CHECK-NEXT: UserOp1 58 +CHECK-NEXT: UserOp2 59 +CHECK-NEXT: VAArg 60 +CHECK-NEXT: ExtractElement 61 +CHECK-NEXT: InsertElement 62 +CHECK-NEXT: ShuffleVector 63 +CHECK-NEXT: ExtractValue 64 +CHECK-NEXT: InsertValue 65 +CHECK-NEXT: LandingPad 66 +CHECK-NEXT: Freeze 67 CHECK-NEXT: FloatTy 68 -CHECK-NEXT: FloatTy 69 -CHECK-NEXT: FloatTy 70 -CHECK-NEXT: FloatTy 71 -CHECK-NEXT: FloatTy 72 -CHECK-NEXT: FloatTy 73 -CHECK-NEXT: VoidTy 74 -CHECK-NEXT: LabelTy 75 -CHECK-NEXT: MetadataTy 76 -CHECK-NEXT: UnknownTy 77 -CHECK-NEXT: TokenTy 78 -CHECK-NEXT: IntegerTy 79 -CHECK-NEXT: FunctionTy 80 -CHECK-NEXT: PointerTy 81 -CHECK-NEXT: StructTy 82 -CHECK-NEXT: ArrayTy 83 -CHECK-NEXT: VectorTy 84 -CHECK-NEXT: VectorTy 85 -CHECK-NEXT: PointerTy 86 -CHECK-NEXT: UnknownTy 87 -CHECK-NEXT: Function 88 -CHECK-NEXT: Pointer 89 -CHECK-NEXT: Constant 90 -CHECK-NEXT: Variable 91 +CHECK-NEXT: VoidTy 69 +CHECK-NEXT: LabelTy 70 +CHECK-NEXT: MetadataTy 71 +CHECK-NEXT: VectorTy 72 +CHECK-NEXT: TokenTy 73 +CHECK-NEXT: IntegerTy 74 +CHECK-NEXT: FunctionTy 75 +CHECK-NEXT: PointerTy 76 +CHECK-NEXT: StructTy 77 +CHECK-NEXT: ArrayTy 78 +CHECK-NEXT: UnknownTy 79 +CHECK-NEXT: Function 80 +CHECK-NEXT: Pointer 81 +CHECK-NEXT: Constant 82 +CHECK-NEXT: Variable 83 diff --git a/llvm/test/tools/llvm-ir2vec/triplets.ll b/llvm/test/tools/llvm-ir2vec/triplets.ll index a7fd9e4..7b476f6 100644 --- a/llvm/test/tools/llvm-ir2vec/triplets.ll +++ b/llvm/test/tools/llvm-ir2vec/triplets.ll @@ -25,41 +25,41 @@ entry: } ; TRIPLETS: MAX_RELATION=3 -; TRIPLETS-NEXT: 12 79 0 -; TRIPLETS-NEXT: 12 91 2 -; TRIPLETS-NEXT: 12 91 3 +; TRIPLETS-NEXT: 12 74 0 +; TRIPLETS-NEXT: 12 83 2 +; TRIPLETS-NEXT: 12 83 3 ; TRIPLETS-NEXT: 12 0 1 -; TRIPLETS-NEXT: 0 74 0 -; TRIPLETS-NEXT: 0 91 2 -; TRIPLETS-NEXT: 16 79 0 -; TRIPLETS-NEXT: 16 91 2 -; TRIPLETS-NEXT: 16 91 3 +; TRIPLETS-NEXT: 0 69 0 +; TRIPLETS-NEXT: 0 83 2 +; TRIPLETS-NEXT: 16 74 0 +; TRIPLETS-NEXT: 16 83 2 +; TRIPLETS-NEXT: 16 83 3 ; TRIPLETS-NEXT: 16 0 1 -; TRIPLETS-NEXT: 0 74 0 -; TRIPLETS-NEXT: 0 91 2 -; TRIPLETS-NEXT: 30 81 0 -; TRIPLETS-NEXT: 30 90 2 +; TRIPLETS-NEXT: 0 69 0 +; TRIPLETS-NEXT: 0 83 2 +; TRIPLETS-NEXT: 30 76 0 +; TRIPLETS-NEXT: 30 82 2 ; TRIPLETS-NEXT: 30 30 1 -; TRIPLETS-NEXT: 30 81 0 -; TRIPLETS-NEXT: 30 90 2 +; TRIPLETS-NEXT: 30 76 0 +; TRIPLETS-NEXT: 30 82 2 ; TRIPLETS-NEXT: 30 32 1 -; TRIPLETS-NEXT: 32 74 0 -; TRIPLETS-NEXT: 32 91 2 -; TRIPLETS-NEXT: 32 89 3 +; TRIPLETS-NEXT: 32 69 0 +; TRIPLETS-NEXT: 32 83 2 +; TRIPLETS-NEXT: 32 81 3 ; TRIPLETS-NEXT: 32 32 1 -; TRIPLETS-NEXT: 32 74 0 -; TRIPLETS-NEXT: 32 91 2 -; TRIPLETS-NEXT: 32 89 3 +; TRIPLETS-NEXT: 32 69 0 +; TRIPLETS-NEXT: 32 83 2 +; TRIPLETS-NEXT: 32 81 3 ; TRIPLETS-NEXT: 32 31 1 -; TRIPLETS-NEXT: 31 79 0 -; TRIPLETS-NEXT: 31 89 2 +; TRIPLETS-NEXT: 31 74 0 +; TRIPLETS-NEXT: 31 81 2 ; TRIPLETS-NEXT: 31 31 1 -; TRIPLETS-NEXT: 31 79 0 -; TRIPLETS-NEXT: 31 89 2 +; TRIPLETS-NEXT: 31 74 0 +; TRIPLETS-NEXT: 31 81 2 ; TRIPLETS-NEXT: 31 12 1 -; TRIPLETS-NEXT: 12 79 0 -; TRIPLETS-NEXT: 12 91 2 -; TRIPLETS-NEXT: 12 91 3 +; TRIPLETS-NEXT: 12 74 0 +; TRIPLETS-NEXT: 12 83 2 +; TRIPLETS-NEXT: 12 83 3 ; TRIPLETS-NEXT: 12 0 1 -; TRIPLETS-NEXT: 0 74 0 -; TRIPLETS-NEXT: 0 91 2 +; TRIPLETS-NEXT: 0 69 0 +; TRIPLETS-NEXT: 0 83 2
\ No newline at end of file diff --git a/llvm/test/tools/llvm-lipo/create-archive-input.test b/llvm/test/tools/llvm-lipo/create-archive-input.test index c432381..555151f 100644 --- a/llvm/test/tools/llvm-lipo/create-archive-input.test +++ b/llvm/test/tools/llvm-lipo/create-archive-input.test @@ -10,11 +10,12 @@ # RUN: llvm-ar cr %t.different_architectures.a %t-i386.o %t-x86_64.o # RUN: not llvm-lipo %t.different_architectures.a -create -output /dev/null 2>&1 | FileCheck --check-prefix=ARCHIVE-WITH-DIFFERENT-ARCHS %s -# RUN: llvm-ar cr %t.contains_fat_binary.a %t-universal.o +# RUN: llvm-ar cr %t.contains_fat_binary.a %t-universal.o # RUN: not llvm-lipo %t.contains_fat_binary.a -create -output /dev/null 2>&1 | FileCheck --check-prefix=ARCHIVE-WITH-FAT-BINARY %s # RUN: llvm-ar cr %t-i386-lib.a %t-i386.o # RUN: llvm-lipo %t-i386-lib.a %t-x86_64.o -create -output %t-i386-x86_64-universal.o +# RUN: llvm-lipo %t-i386-lib.a -info | FileCheck --check-prefix=INFO-i386 %s # RUN: llvm-lipo %t-i386-x86_64-universal.o -info | FileCheck --check-prefix=INFO-i386-x86_64 %s # RUN: llvm-lipo %t-i386-x86_64-universal.o -thin i386 -output %t-extracted-i386-lib.a # RUN: cmp %t-extracted-i386-lib.a %t-i386-lib.a @@ -51,4 +52,5 @@ # ARCHIVE-WITH-DIFFERENT-ARCHS: all members must match # ARCHIVE-WITH-FAT-BINARY: fat file (not allowed in an archive) # +# INFO-i386: i386 # INFO-i386-x86_64: i386 x86_64 diff --git a/llvm/test/tools/llvm-lto2/version.test b/llvm/test/tools/llvm-lto2/version.test new file mode 100644 index 0000000..80e465a --- /dev/null +++ b/llvm/test/tools/llvm-lto2/version.test @@ -0,0 +1,7 @@ +## Show that you can run version as a main command for llvm-lto2 +## or a subcommand of llvm-lto2 run. + +RUN: llvm-lto2 --version | FileCheck %s +RUN: llvm-lto2 run --version | FileCheck %s + +CHECK: version diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s index d8051e7..cd4135a 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s @@ -3966,18 +3966,18 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 4 0.50 fabs z31.d, p7/m, z31.d # CHECK-NEXT: 1 4 0.50 fabs z31.h, p7/m, z31.h # CHECK-NEXT: 1 4 0.50 fabs z31.s, p7/m, z31.s -# CHECK-NEXT: 1 4 0.50 facge p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 facge p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: 1 4 0.50 facge p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 facge p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: 1 4 0.50 facge p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: 1 4 0.50 facge p0.s, p0/z, z1.s, z0.s -# CHECK-NEXT: 1 4 0.50 facgt p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 facgt p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: 1 4 0.50 facgt p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 facgt p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: 1 4 0.50 facgt p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: 1 4 0.50 facgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 4 1.00 facge p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 facge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 4 1.00 facge p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 facge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 4 1.00 facge p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 facge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 4 1.00 facgt p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 facgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 4 1.00 facgt p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 facgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 4 1.00 facgt p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 facgt p0.s, p0/z, z1.s, z0.s # CHECK-NEXT: 1 4 0.50 fadd z0.d, p0/m, z0.d, #0.5 # CHECK-NEXT: 1 4 0.50 fadd z0.d, p7/m, z0.d, z31.d # CHECK-NEXT: 1 4 0.50 fadd z0.d, z1.d, z31.d @@ -4005,30 +4005,30 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 4 0.50 fcadd z31.d, p7/m, z31.d, z31.d, #270 # CHECK-NEXT: 1 4 0.50 fcadd z31.h, p7/m, z31.h, z31.h, #270 # CHECK-NEXT: 1 4 0.50 fcadd z31.s, p7/m, z31.s, z31.s, #270 -# CHECK-NEXT: 1 4 0.50 fcmeq p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmeq p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 fcmeq p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmeq p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 fcmeq p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmeq p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: 1 4 0.50 fcmge p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmge p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 fcmge p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: 1 4 0.50 fcmge p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmge p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 fcmge p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: 1 4 0.50 fcmge p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmge p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: 1 4 0.50 fcmge p0.s, p0/z, z1.s, z0.s -# CHECK-NEXT: 1 4 0.50 fcmgt p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmgt p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 fcmgt p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: 1 4 0.50 fcmgt p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmgt p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 fcmgt p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: 1 4 0.50 fcmgt p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmgt p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: 1 4 0.50 fcmgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 4 1.00 fcmeq p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmeq p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 fcmeq p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmeq p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 fcmeq p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmeq p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 fcmge p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmge p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 fcmge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 4 1.00 fcmge p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmge p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 fcmge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 4 1.00 fcmge p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmge p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 fcmge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 4 1.00 fcmgt p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmgt p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 fcmgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 4 1.00 fcmgt p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmgt p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 fcmgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 4 1.00 fcmgt p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmgt p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 fcmgt p0.s, p0/z, z1.s, z0.s # CHECK-NEXT: 1 4 0.50 fcmla z0.d, p0/m, z0.d, z0.d, #0 # CHECK-NEXT: 1 4 0.50 fcmla z0.d, p0/m, z1.d, z2.d, #90 # CHECK-NEXT: 1 4 0.50 fcmla z0.h, p0/m, z0.h, z0.h, #0 @@ -4045,21 +4045,21 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 4 0.50 fcmla z31.h, p7/m, z31.h, z31.h, #270 # CHECK-NEXT: 1 4 0.50 fcmla z31.h, z31.h, z7.h[3], #270 # CHECK-NEXT: 1 4 0.50 fcmla z31.s, p7/m, z31.s, z31.s, #270 -# CHECK-NEXT: 1 4 0.50 fcmle p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmle p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmle p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmlt p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmlt p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmlt p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmne p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmne p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 fcmne p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmne p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 fcmne p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: 1 4 0.50 fcmne p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: 1 4 0.50 fcmuo p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: 1 4 0.50 fcmuo p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: 1 4 0.50 fcmuo p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 fcmle p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmle p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmle p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmlt p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmlt p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmlt p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmne p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmne p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 fcmne p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmne p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 fcmne p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 4 1.00 fcmne p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 4 1.00 fcmuo p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 4 1.00 fcmuo p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 4 1.00 fcmuo p0.s, p0/z, z0.s, z1.s # CHECK-NEXT: 1 4 0.50 fcvt z0.d, p0/m, z0.h # CHECK-NEXT: 1 4 0.50 fcvt z0.d, p0/m, z0.s # CHECK-NEXT: 1 4 0.50 fcvt z0.h, p0/m, z0.d @@ -6848,7 +6848,7 @@ zip2 z31.s, z31.s, z31.s # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] -# CHECK-NEXT: 79.00 75.00 75.00 9.00 - 209.00 3667.00 - - 1290.00 924.00 199.50 199.50 670.00 +# CHECK-NEXT: 79.00 75.00 75.00 9.00 - 209.00 3667.00 - - 1315.50 949.50 199.50 199.50 670.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions: @@ -7398,18 +7398,18 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fabs z31.d, p7/m, z31.d # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fabs z31.h, p7/m, z31.h # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fabs z31.s, p7/m, z31.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facge p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facge p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facge p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facge p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facge p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facge p0.s, p0/z, z1.s, z0.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facgt p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facgt p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facgt p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facgt p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facgt p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - facgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facge p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facge p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facge p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facgt p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facgt p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facgt p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - facgt p0.s, p0/z, z1.s, z0.s # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fadd z0.d, p0/m, z0.d, #0.5 # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fadd z0.d, p7/m, z0.d, z31.d # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fadd z0.d, z1.d, z31.d @@ -7437,30 +7437,30 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcadd z31.d, p7/m, z31.d, z31.d, #270 # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcadd z31.h, p7/m, z31.h, z31.h, #270 # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcadd z31.s, p7/m, z31.s, z31.s, #270 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmeq p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmeq p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmeq p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmeq p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmeq p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmeq p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmge p0.s, p0/z, z1.s, z0.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.d, p0/z, z1.d, z0.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.h, p0/z, z1.h, z0.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmeq p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmeq p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmeq p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmeq p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmeq p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmeq p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmgt p0.s, p0/z, z1.s, z0.s # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - fcmla z0.d, p0/m, z0.d, z0.d, #0 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - fcmla z0.d, p0/m, z1.d, z2.d, #90 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - fcmla z0.h, p0/m, z0.h, z0.h, #0 @@ -7477,21 +7477,21 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - fcmla z31.h, p7/m, z31.h, z31.h, #270 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - fcmla z31.h, z31.h, z7.h[3], #270 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - fcmla z31.s, p7/m, z31.s, z31.s, #270 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmle p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmle p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmle p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmlt p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmlt p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmlt p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmne p0.d, p0/z, z0.d, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmne p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmne p0.h, p0/z, z0.h, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmne p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmne p0.s, p0/z, z0.s, #0.0 -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmne p0.s, p0/z, z0.s, z1.s -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmuo p0.d, p0/z, z0.d, z1.d -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmuo p0.h, p0/z, z0.h, z1.h -# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcmuo p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmle p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmle p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmle p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmlt p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmlt p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmlt p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmne p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmne p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmne p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmne p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmne p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmne p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmuo p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmuo p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - fcmuo p0.s, p0/z, z0.s, z1.s # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcvt z0.d, p0/m, z0.h # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcvt z0.d, p0/m, z0.s # CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fcvt z0.h, p0/m, z0.d diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s index 5cf5ed5..234a3e2 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s @@ -3002,357 +3002,357 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu # CHECK-NEXT: 1 8 4.00 8 SMX60_VIEU[4] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VV vaaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADDU_VX vaaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VV vaadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VAADD_VX vaadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VV vasubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUBU_VX vasubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VV vasub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VV vasub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VASUB_VX vasub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -3882,445 +3882,445 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VI vsaddu.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VV vsaddu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADDU_VX vsaddu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VI vsadd.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VV vsadd.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSADD_VX vsadd.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VV vssubu.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUBU_VX vssubu.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VV vssub.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSUB_VX vssub.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -4574,7 +4574,7 @@ vwsub.wx v8, v16, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] -# CHECK-NEXT: - 1120.00 - - - - 3292.00 - +# CHECK-NEXT: - 1120.00 - - - - 4084.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions: @@ -5267,11 +5267,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5279,29 +5279,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5311,11 +5311,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5323,29 +5323,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5355,11 +5355,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5367,29 +5367,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5399,11 +5399,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5411,29 +5411,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vaadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vaadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5443,11 +5443,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5455,29 +5455,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5487,11 +5487,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5499,29 +5499,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5531,11 +5531,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5543,29 +5543,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5575,11 +5575,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5587,29 +5587,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vasub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vasub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 4.00 - vmadc.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6147,11 +6147,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6159,29 +6159,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6191,11 +6191,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6203,29 +6203,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6235,11 +6235,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6247,29 +6247,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsaddu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsaddu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6279,11 +6279,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6291,29 +6291,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6323,11 +6323,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6335,29 +6335,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6367,11 +6367,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6379,29 +6379,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsadd.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6411,11 +6411,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6423,29 +6423,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6455,11 +6455,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6467,29 +6467,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssubu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssubu.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6499,11 +6499,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6511,29 +6511,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6543,11 +6543,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6555,29 +6555,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssub.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 4.00 - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s index 89d3872..5a5f366 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s @@ -2630,269 +2630,269 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VI vssra.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VV vssra.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRA_VX vssra.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VI vssrl.vi v8, v8, 12 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VV vssrl.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSSRL_VX vssrl.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5 # CHECK: Resources: # CHECK-NEXT: [0] - SMX60_FP @@ -2906,7 +2906,7 @@ vssrl.vx v8, v8, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] -# CHECK-NEXT: - 708.00 - - - - 2436.00 - +# CHECK-NEXT: - 708.00 - - - - 3060.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions: @@ -4069,43 +4069,43 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4113,43 +4113,43 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4157,43 +4157,43 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssra.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4201,43 +4201,43 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vi v8, v8, 12 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4245,43 +4245,43 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4289,40 +4289,40 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 2.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vssrl.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vssrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vssrl.vx v8, v8, t5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s index 572ebf2..a166f15 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s @@ -1906,93 +1906,93 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu # CHECK-NEXT: 1 8 4.00 8 SMX60_VIEU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5 +# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5 # CHECK: Resources: # CHECK-NEXT: [0] - SMX60_FP @@ -2006,7 +2006,7 @@ vsmul.vx v8, v8, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] -# CHECK-NEXT: - 486.00 - - - - 3748.00 - +# CHECK-NEXT: - 486.00 - - - - 4196.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions: @@ -2901,43 +2901,43 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2945,40 +2945,40 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s index 0f19ef2..2dce795 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s @@ -105,12 +105,12 @@ vpxor %ymm3, %ymm3, %ymm5 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 83 -# CHECK-NEXT: Total Cycles: 17 +# CHECK-NEXT: Total Cycles: 19 # CHECK-NEXT: Total uOps: 83 # CHECK: Dispatch Width: 6 -# CHECK-NEXT: uOps Per Cycle: 4.88 -# CHECK-NEXT: IPC: 4.88 +# CHECK-NEXT: uOps Per Cycle: 4.37 +# CHECK-NEXT: IPC: 4.37 # CHECK-NEXT: Block RThroughput: 13.8 # CHECK: Instruction Info: @@ -208,7 +208,7 @@ vpxor %ymm3, %ymm3, %ymm5 # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 24 -# CHECK-NEXT: Max number of mappings used: 15 +# CHECK-NEXT: Max number of mappings used: 16 # CHECK: Resources: # CHECK-NEXT: [0] - SKLDivider @@ -313,92 +313,92 @@ vpxor %ymm3, %ymm3, %ymm5 # CHECK-NEXT: - - - - - - - - - - vpxor %ymm3, %ymm3, %ymm5 # CHECK: Timeline view: -# CHECK-NEXT: 0123456 +# CHECK-NEXT: 012345678 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DR . . .. subl %eax, %eax -# CHECK-NEXT: [0,1] DR . . .. subq %rax, %rax -# CHECK-NEXT: [0,2] DR . . .. xorl %eax, %eax -# CHECK-NEXT: [0,3] DR . . .. xorq %rax, %rax -# CHECK-NEXT: [0,4] DeER . . .. pcmpgtb %mm2, %mm2 -# CHECK-NEXT: [0,5] D=eER. . .. pcmpgtd %mm2, %mm2 -# CHECK-NEXT: [0,6] .D=eER . .. pcmpgtw %mm2, %mm2 -# CHECK-NEXT: [0,7] .D---R . .. pcmpgtb %xmm2, %xmm2 -# CHECK-NEXT: [0,8] .D---R . .. pcmpgtd %xmm2, %xmm2 -# CHECK-NEXT: [0,9] .D---R . .. pcmpgtq %xmm2, %xmm2 -# CHECK-NEXT: [0,10] .D---R . .. pcmpgtw %xmm2, %xmm2 -# CHECK-NEXT: [0,11] .D---R . .. vpcmpgtb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,12] . D--R . .. vpcmpgtd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,13] . D--R . .. vpcmpgtq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,14] . D--R . .. vpcmpgtw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,15] . D--R . .. vpcmpgtb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,16] . D--R . .. vpcmpgtd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,17] . D--R . .. vpcmpgtq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,18] . D-R . .. vpcmpgtw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,19] . D-R . .. vpcmpgtb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,20] . D-R . .. vpcmpgtd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,21] . D-R . .. vpcmpgtq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,22] . D-R . .. vpcmpgtw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,23] . D-R . .. vpcmpgtb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,24] . DR . .. vpcmpgtd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,25] . DR . .. vpcmpgtq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,26] . DR . .. vpcmpgtw %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,27] . DeER . .. psubb %mm2, %mm2 -# CHECK-NEXT: [0,28] . D=eER . .. psubd %mm2, %mm2 -# CHECK-NEXT: [0,29] . D==eER. .. psubq %mm2, %mm2 -# CHECK-NEXT: [0,30] . D==eER .. psubw %mm2, %mm2 -# CHECK-NEXT: [0,31] . D----R .. psubb %xmm2, %xmm2 -# CHECK-NEXT: [0,32] . D----R .. psubd %xmm2, %xmm2 -# CHECK-NEXT: [0,33] . D----R .. psubq %xmm2, %xmm2 -# CHECK-NEXT: [0,34] . D----R .. psubw %xmm2, %xmm2 -# CHECK-NEXT: [0,35] . D----R .. vpsubb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,36] . .D---R .. vpsubd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,37] . .D---R .. vpsubq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,38] . .D---R .. vpsubw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,39] . .D---R .. vpsubb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,40] . .D---R .. vpsubd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,41] . .D---R .. vpsubq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,42] . . D--R .. vpsubw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,43] . . D--R .. vpsubb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,44] . . D--R .. vpsubd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,45] . . D--R .. vpsubq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,46] . . D--R .. vpsubw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,47] . . D--R .. vpsubb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,48] . . D-R .. vpsubd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,49] . . D-R .. vpsubq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,50] . . D-R .. vpsubw %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,51] . . DeER .. andnps %xmm0, %xmm0 -# CHECK-NEXT: [0,52] . . DeER .. andnpd %xmm1, %xmm1 -# CHECK-NEXT: [0,53] . . DeER .. vandnps %xmm2, %xmm2, %xmm2 -# CHECK-NEXT: [0,54] . . DeER .. vandnpd %xmm1, %xmm1, %xmm1 -# CHECK-NEXT: [0,55] . . DeER .. vandnps %ymm2, %ymm2, %ymm2 -# CHECK-NEXT: [0,56] . . D=eER .. vandnpd %ymm1, %ymm1, %ymm1 -# CHECK-NEXT: [0,57] . . DeE-R .. pandn %mm2, %mm2 -# CHECK-NEXT: [0,58] . . D=eER .. pandn %xmm2, %xmm2 -# CHECK-NEXT: [0,59] . . D=eER .. vpandn %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,60] . . D=eER.. vpandn %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,61] . . D=eER.. vandnps %xmm2, %xmm2, %xmm5 -# CHECK-NEXT: [0,62] . . D=eER.. vandnpd %xmm1, %xmm1, %xmm5 -# CHECK-NEXT: [0,63] . . D==eER. vpandn %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,64] . . D==eER. vandnps %ymm2, %ymm2, %ymm5 -# CHECK-NEXT: [0,65] . . D==eER. vandnpd %ymm1, %ymm1, %ymm5 -# CHECK-NEXT: [0,66] . . .D==eER vpandn %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,67] . . .D----R xorps %xmm0, %xmm0 -# CHECK-NEXT: [0,68] . . .D----R xorpd %xmm1, %xmm1 -# CHECK-NEXT: [0,69] . . .D----R vxorps %xmm2, %xmm2, %xmm2 -# CHECK-NEXT: [0,70] . . .D----R vxorpd %xmm1, %xmm1, %xmm1 -# CHECK-NEXT: [0,71] . . .D----R vxorps %ymm2, %ymm2, %ymm2 -# CHECK-NEXT: [0,72] . . . D---R vxorpd %ymm1, %ymm1, %ymm1 -# CHECK-NEXT: [0,73] . . . D=eER pxor %mm2, %mm2 -# CHECK-NEXT: [0,74] . . . D---R pxor %xmm2, %xmm2 -# CHECK-NEXT: [0,75] . . . D---R vpxor %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,76] . . . D---R vpxor %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,77] . . . D---R vxorps %xmm4, %xmm4, %xmm5 -# CHECK-NEXT: [0,78] . . . D--R vxorpd %xmm1, %xmm1, %xmm3 -# CHECK-NEXT: [0,79] . . . D--R vxorps %ymm4, %ymm4, %ymm5 -# CHECK-NEXT: [0,80] . . . D--R vxorpd %ymm1, %ymm1, %ymm3 -# CHECK-NEXT: [0,81] . . . D--R vpxor %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,82] . . . D--R vpxor %ymm3, %ymm3, %ymm5 +# CHECK: [0,0] DR . . . . subl %eax, %eax +# CHECK-NEXT: [0,1] DR . . . . subq %rax, %rax +# CHECK-NEXT: [0,2] DR . . . . xorl %eax, %eax +# CHECK-NEXT: [0,3] DR . . . . xorq %rax, %rax +# CHECK-NEXT: [0,4] DeER . . . . pcmpgtb %mm2, %mm2 +# CHECK-NEXT: [0,5] D=eER. . . . pcmpgtd %mm2, %mm2 +# CHECK-NEXT: [0,6] .D=eER . . . pcmpgtw %mm2, %mm2 +# CHECK-NEXT: [0,7] .D---R . . . pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: [0,8] .D---R . . . pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: [0,9] .D---R . . . pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: [0,10] .D---R . . . pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: [0,11] .D---R . . . vpcmpgtb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,12] . D--R . . . vpcmpgtd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,13] . D--R . . . vpcmpgtq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,14] . D---R . . . vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,15] . D---R . . . vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,16] . D---R . . . vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,17] . D---R . . . vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,18] . D--R . . . vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,19] . D--R . . . vpcmpgtb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,20] . D--R . . . vpcmpgtd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,21] . D--R . . . vpcmpgtq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,22] . D---R . . . vpcmpgtw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,23] . D---R . . . vpcmpgtb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,24] . D--R . . . vpcmpgtd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,25] . D--R . . . vpcmpgtq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,26] . D--R . . . vpcmpgtw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,27] . DeER . . . psubb %mm2, %mm2 +# CHECK-NEXT: [0,28] . D=eER . . . psubd %mm2, %mm2 +# CHECK-NEXT: [0,29] . D==eER. . . psubq %mm2, %mm2 +# CHECK-NEXT: [0,30] . D==eER . . psubw %mm2, %mm2 +# CHECK-NEXT: [0,31] . D----R . . psubb %xmm2, %xmm2 +# CHECK-NEXT: [0,32] . D----R . . psubd %xmm2, %xmm2 +# CHECK-NEXT: [0,33] . D----R . . psubq %xmm2, %xmm2 +# CHECK-NEXT: [0,34] . D----R . . psubw %xmm2, %xmm2 +# CHECK-NEXT: [0,35] . D----R . . vpsubb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,36] . .D---R . . vpsubd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,37] . .D---R . . vpsubq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,38] . .D----R . . vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,39] . .D----R . . vpsubb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,40] . .D----R . . vpsubd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,41] . .D----R . . vpsubq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,42] . . D---R . . vpsubw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,43] . . D---R . . vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,44] . . D---R . . vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,45] . . D---R . . vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,46] . . D----R . . vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,47] . . D----R . . vpsubb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,48] . . D---R . . vpsubd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,49] . . D---R . . vpsubq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,50] . . D---R . . vpsubw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,51] . . DeE-R . . andnps %xmm0, %xmm0 +# CHECK-NEXT: [0,52] . . DeE-R . . andnpd %xmm1, %xmm1 +# CHECK-NEXT: [0,53] . . DeE-R . . vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: [0,54] . . DeE-R . . vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: [0,55] . . DeE-R . . vandnps %ymm2, %ymm2, %ymm2 +# CHECK-NEXT: [0,56] . . D=eER . . vandnpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [0,57] . . DeE-R . . pandn %mm2, %mm2 +# CHECK-NEXT: [0,58] . . D=eER . . pandn %xmm2, %xmm2 +# CHECK-NEXT: [0,59] . . D=eER . . vpandn %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,60] . . D=eER. . vpandn %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,61] . . D=eER. . vandnps %xmm2, %xmm2, %xmm5 +# CHECK-NEXT: [0,62] . . D=eER. . vandnpd %xmm1, %xmm1, %xmm5 +# CHECK-NEXT: [0,63] . . D==eER . vpandn %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,64] . . D==eER . vandnps %ymm2, %ymm2, %ymm5 +# CHECK-NEXT: [0,65] . . D==eER . vandnpd %ymm1, %ymm1, %ymm5 +# CHECK-NEXT: [0,66] . . .D==eER . vpandn %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,67] . . .D----R . xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,68] . . .D----R . xorpd %xmm1, %xmm1 +# CHECK-NEXT: [0,69] . . .D----R . vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: [0,70] . . .D----R . vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: [0,71] . . .D----R . vxorps %ymm2, %ymm2, %ymm2 +# CHECK-NEXT: [0,72] . . . D---R . vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [0,73] . . . D=eER . pxor %mm2, %mm2 +# CHECK-NEXT: [0,74] . . . D----R. pxor %xmm2, %xmm2 +# CHECK-NEXT: [0,75] . . . D----R. vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,76] . . . D----R. vpxor %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,77] . . . D----R. vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: [0,78] . . . D---R. vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: [0,79] . . . D---R. vxorps %ymm4, %ymm4, %ymm5 +# CHECK-NEXT: [0,80] . . . D---R. vxorpd %ymm1, %ymm1, %ymm3 +# CHECK-NEXT: [0,81] . . . D---R. vpxor %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,82] . . . D----R vpxor %ymm3, %ymm3, %ymm5 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -421,19 +421,19 @@ vpxor %ymm3, %ymm3, %ymm5 # CHECK-NEXT: 11. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 12. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 13. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 14. 1 0.0 0.0 2.0 vpcmpgtw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 15. 1 0.0 0.0 2.0 vpcmpgtb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 16. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 17. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 18. 1 0.0 0.0 1.0 vpcmpgtw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 19. 1 0.0 0.0 1.0 vpcmpgtb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 20. 1 0.0 0.0 1.0 vpcmpgtd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 21. 1 0.0 0.0 1.0 vpcmpgtq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 22. 1 0.0 0.0 1.0 vpcmpgtw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 23. 1 0.0 0.0 1.0 vpcmpgtb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 24. 1 0.0 0.0 0.0 vpcmpgtd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 25. 1 0.0 0.0 0.0 vpcmpgtq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 26. 1 0.0 0.0 0.0 vpcmpgtw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 14. 1 0.0 0.0 3.0 vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 15. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 16. 1 0.0 0.0 3.0 vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 17. 1 0.0 0.0 3.0 vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 18. 1 0.0 0.0 2.0 vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 19. 1 0.0 0.0 2.0 vpcmpgtb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 20. 1 0.0 0.0 2.0 vpcmpgtd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 21. 1 0.0 0.0 2.0 vpcmpgtq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 22. 1 0.0 0.0 3.0 vpcmpgtw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 23. 1 0.0 0.0 3.0 vpcmpgtb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 24. 1 0.0 0.0 2.0 vpcmpgtd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 25. 1 0.0 0.0 2.0 vpcmpgtq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 26. 1 0.0 0.0 2.0 vpcmpgtw %ymm3, %ymm3, %ymm5 # CHECK-NEXT: 27. 1 1.0 1.0 0.0 psubb %mm2, %mm2 # CHECK-NEXT: 28. 1 2.0 0.0 0.0 psubd %mm2, %mm2 # CHECK-NEXT: 29. 1 3.0 0.0 0.0 psubq %mm2, %mm2 @@ -445,24 +445,24 @@ vpxor %ymm3, %ymm3, %ymm5 # CHECK-NEXT: 35. 1 0.0 0.0 4.0 vpsubb %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 36. 1 0.0 0.0 3.0 vpsubd %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 37. 1 0.0 0.0 3.0 vpsubq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 38. 1 0.0 0.0 3.0 vpsubw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 39. 1 0.0 0.0 3.0 vpsubb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 40. 1 0.0 0.0 3.0 vpsubd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 41. 1 0.0 0.0 3.0 vpsubq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 42. 1 0.0 0.0 2.0 vpsubw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 43. 1 0.0 0.0 2.0 vpsubb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 44. 1 0.0 0.0 2.0 vpsubd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 45. 1 0.0 0.0 2.0 vpsubq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 46. 1 0.0 0.0 2.0 vpsubw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 47. 1 0.0 0.0 2.0 vpsubb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 48. 1 0.0 0.0 1.0 vpsubd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 49. 1 0.0 0.0 1.0 vpsubq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 50. 1 0.0 0.0 1.0 vpsubw %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 51. 1 1.0 1.0 0.0 andnps %xmm0, %xmm0 -# CHECK-NEXT: 52. 1 1.0 1.0 0.0 andnpd %xmm1, %xmm1 -# CHECK-NEXT: 53. 1 1.0 1.0 0.0 vandnps %xmm2, %xmm2, %xmm2 -# CHECK-NEXT: 54. 1 1.0 0.0 0.0 vandnpd %xmm1, %xmm1, %xmm1 -# CHECK-NEXT: 55. 1 1.0 0.0 0.0 vandnps %ymm2, %ymm2, %ymm2 +# CHECK-NEXT: 38. 1 0.0 0.0 4.0 vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 39. 1 0.0 0.0 4.0 vpsubb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 40. 1 0.0 0.0 4.0 vpsubd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 41. 1 0.0 0.0 4.0 vpsubq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 42. 1 0.0 0.0 3.0 vpsubw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 43. 1 0.0 0.0 3.0 vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 44. 1 0.0 0.0 3.0 vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 45. 1 0.0 0.0 3.0 vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 46. 1 0.0 0.0 4.0 vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 47. 1 0.0 0.0 4.0 vpsubb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 48. 1 0.0 0.0 3.0 vpsubd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 49. 1 0.0 0.0 3.0 vpsubq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 50. 1 0.0 0.0 3.0 vpsubw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 51. 1 1.0 1.0 1.0 andnps %xmm0, %xmm0 +# CHECK-NEXT: 52. 1 1.0 1.0 1.0 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 53. 1 1.0 1.0 1.0 vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: 54. 1 1.0 0.0 1.0 vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: 55. 1 1.0 0.0 1.0 vandnps %ymm2, %ymm2, %ymm2 # CHECK-NEXT: 56. 1 2.0 0.0 0.0 vandnpd %ymm1, %ymm1, %ymm1 # CHECK-NEXT: 57. 1 1.0 1.0 1.0 pandn %mm2, %mm2 # CHECK-NEXT: 58. 1 2.0 0.0 0.0 pandn %xmm2, %xmm2 @@ -481,13 +481,13 @@ vpxor %ymm3, %ymm3, %ymm5 # CHECK-NEXT: 71. 1 0.0 0.0 4.0 vxorps %ymm2, %ymm2, %ymm2 # CHECK-NEXT: 72. 1 0.0 0.0 3.0 vxorpd %ymm1, %ymm1, %ymm1 # CHECK-NEXT: 73. 1 2.0 2.0 0.0 pxor %mm2, %mm2 -# CHECK-NEXT: 74. 1 0.0 0.0 3.0 pxor %xmm2, %xmm2 -# CHECK-NEXT: 75. 1 0.0 0.0 3.0 vpxor %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 76. 1 0.0 0.0 3.0 vpxor %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 77. 1 0.0 0.0 3.0 vxorps %xmm4, %xmm4, %xmm5 -# CHECK-NEXT: 78. 1 0.0 0.0 2.0 vxorpd %xmm1, %xmm1, %xmm3 -# CHECK-NEXT: 79. 1 0.0 0.0 2.0 vxorps %ymm4, %ymm4, %ymm5 -# CHECK-NEXT: 80. 1 0.0 0.0 2.0 vxorpd %ymm1, %ymm1, %ymm3 -# CHECK-NEXT: 81. 1 0.0 0.0 2.0 vpxor %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 82. 1 0.0 0.0 2.0 vpxor %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 1 0.6 0.2 1.6 <total> +# CHECK-NEXT: 74. 1 0.0 0.0 4.0 pxor %xmm2, %xmm2 +# CHECK-NEXT: 75. 1 0.0 0.0 4.0 vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 76. 1 0.0 0.0 4.0 vpxor %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 77. 1 0.0 0.0 4.0 vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: 78. 1 0.0 0.0 3.0 vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: 79. 1 0.0 0.0 3.0 vxorps %ymm4, %ymm4, %ymm5 +# CHECK-NEXT: 80. 1 0.0 0.0 3.0 vxorpd %ymm1, %ymm1, %ymm3 +# CHECK-NEXT: 81. 1 0.0 0.0 3.0 vpxor %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 82. 1 0.0 0.0 4.0 vpxor %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 1 0.6 0.2 2.2 <total> diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s index d3f94c2..dbe3827 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s @@ -167,12 +167,12 @@ vpxorq %zmm19, %zmm19, %zmm21 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 139 -# CHECK-NEXT: Total Cycles: 27 +# CHECK-NEXT: Total Cycles: 31 # CHECK-NEXT: Total uOps: 139 # CHECK: Dispatch Width: 6 -# CHECK-NEXT: uOps Per Cycle: 5.15 -# CHECK-NEXT: IPC: 5.15 +# CHECK-NEXT: uOps Per Cycle: 4.48 +# CHECK-NEXT: IPC: 4.48 # CHECK-NEXT: Block RThroughput: 23.2 # CHECK: Instruction Info: @@ -487,148 +487,148 @@ vpxorq %zmm19, %zmm19, %zmm21 # CHECK-NEXT: - - - - - - - - - - vpxorq %zmm19, %zmm19, %zmm21 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 0123456 - -# CHECK: [0,0] DR . . . . .. subl %eax, %eax -# CHECK-NEXT: [0,1] DR . . . . .. subq %rax, %rax -# CHECK-NEXT: [0,2] DR . . . . .. xorl %eax, %eax -# CHECK-NEXT: [0,3] DR . . . . .. xorq %rax, %rax -# CHECK-NEXT: [0,4] DeER . . . . .. pcmpgtb %mm2, %mm2 -# CHECK-NEXT: [0,5] D=eER. . . . .. pcmpgtd %mm2, %mm2 -# CHECK-NEXT: [0,6] .D=eER . . . .. pcmpgtw %mm2, %mm2 -# CHECK-NEXT: [0,7] .D---R . . . .. pcmpgtb %xmm2, %xmm2 -# CHECK-NEXT: [0,8] .D---R . . . .. pcmpgtd %xmm2, %xmm2 -# CHECK-NEXT: [0,9] .D---R . . . .. pcmpgtq %xmm2, %xmm2 -# CHECK-NEXT: [0,10] .D---R . . . .. pcmpgtw %xmm2, %xmm2 -# CHECK-NEXT: [0,11] .D---R . . . .. vpcmpgtb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,12] . D--R . . . .. vpcmpgtd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,13] . D--R . . . .. vpcmpgtq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,14] . D--R . . . .. vpcmpgtw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,15] . D--R . . . .. vpcmpgtb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,16] . D--R . . . .. vpcmpgtd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,17] . D--R . . . .. vpcmpgtq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,18] . D-R . . . .. vpcmpgtw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,19] . D-R . . . .. vpcmpgtb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,20] . D-R . . . .. vpcmpgtd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,21] . D-R . . . .. vpcmpgtq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,22] . D-R . . . .. vpcmpgtw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,23] . D-R . . . .. vpcmpgtb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,24] . DR . . . .. vpcmpgtd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,25] . DR . . . .. vpcmpgtq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,26] . DR . . . .. vpcmpgtw %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,27] . DeER . . . .. psubb %mm2, %mm2 -# CHECK-NEXT: [0,28] . D=eER . . . .. psubd %mm2, %mm2 -# CHECK-NEXT: [0,29] . D==eER. . . .. psubq %mm2, %mm2 -# CHECK-NEXT: [0,30] . D==eER . . .. psubw %mm2, %mm2 -# CHECK-NEXT: [0,31] . D----R . . .. psubb %xmm2, %xmm2 -# CHECK-NEXT: [0,32] . D----R . . .. psubd %xmm2, %xmm2 -# CHECK-NEXT: [0,33] . D----R . . .. psubq %xmm2, %xmm2 -# CHECK-NEXT: [0,34] . D----R . . .. psubw %xmm2, %xmm2 -# CHECK-NEXT: [0,35] . D----R . . .. vpsubb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,36] . .D---R . . .. vpsubd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,37] . .D---R . . .. vpsubq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,38] . .D---R . . .. vpsubw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,39] . .D---R . . .. vpsubb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,40] . .D---R . . .. vpsubd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,41] . .D---R . . .. vpsubq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,42] . . D--R . . .. vpsubw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,43] . . D--R . . .. vpsubb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,44] . . D--R . . .. vpsubd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,45] . . D--R . . .. vpsubq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,46] . . D--R . . .. vpsubw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,47] . . D--R . . .. vpsubb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,48] . . D-R . . .. vpsubd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,49] . . D-R . . .. vpsubq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,50] . . D-R . . .. vpsubw %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,51] . . D-R . . .. vpsubb %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,52] . . D-R . . .. vpsubd %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,53] . . D-R . . .. vpsubq %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,54] . . DR . . .. vpsubw %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,55] . . DR . . .. vpsubb %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,56] . . DR . . .. vpsubd %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,57] . . DR . . .. vpsubq %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,58] . . DR . . .. vpsubw %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,59] . . DR . . .. vpsubb %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,60] . . DR . . .. vpsubd %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,61] . . DR . . .. vpsubq %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,62] . . DR . . .. vpsubw %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,63] . . DR . . .. vpsubb %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,64] . . DR . . .. vpsubd %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,65] . . DR . . .. vpsubq %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,66] . . .DR . . .. vpsubw %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,67] . . .DR . . .. vpsubb %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,68] . . .DR . . .. vpsubd %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,69] . . .DR . . .. vpsubq %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,70] . . .DR . . .. vpsubw %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,71] . . .DR . . .. vpsubb %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,72] . . . DR . . .. vpsubd %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,73] . . . DR . . .. vpsubq %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,74] . . . DR . . .. vpsubw %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,75] . . . DeER . .. andnps %xmm0, %xmm0 -# CHECK-NEXT: [0,76] . . . DeER . .. andnpd %xmm1, %xmm1 -# CHECK-NEXT: [0,77] . . . DeER . .. vandnps %xmm2, %xmm2, %xmm2 -# CHECK-NEXT: [0,78] . . . DeER . .. vandnpd %xmm1, %xmm1, %xmm1 -# CHECK-NEXT: [0,79] . . . DeER . .. vandnps %ymm2, %ymm2, %ymm2 -# CHECK-NEXT: [0,80] . . . D=eER . .. vandnpd %ymm1, %ymm1, %ymm1 -# CHECK-NEXT: [0,81] . . . D=eER . .. vandnps %zmm2, %zmm2, %zmm2 -# CHECK-NEXT: [0,82] . . . D==eER . .. vandnpd %zmm1, %zmm1, %zmm1 -# CHECK-NEXT: [0,83] . . . DeE--R . .. pandn %mm2, %mm2 -# CHECK-NEXT: [0,84] . . . D=eER . .. pandn %xmm2, %xmm2 -# CHECK-NEXT: [0,85] . . . DeE-R . .. vpandn %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,86] . . . D=eER . .. vpandn %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,87] . . . D==eER. .. vpandnd %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,88] . . . D===eER .. vpandnq %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,89] . . . D====eER .. vpandnd %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,90] . . . D====eER .. vpandnq %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,91] . . . D=====eER .. vpandnd %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,92] . . . D======eER.. vpandnq %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,93] . . . D=eE-----R.. vandnps %xmm2, %xmm2, %xmm5 -# CHECK-NEXT: [0,94] . . . D=eE-----R.. vandnpd %xmm1, %xmm1, %xmm5 -# CHECK-NEXT: [0,95] . . . D==eE----R.. vpandn %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,96] . . . .D=eE----R.. vandnps %ymm2, %ymm2, %ymm5 -# CHECK-NEXT: [0,97] . . . .D==eE---R.. vandnpd %ymm1, %ymm1, %ymm5 -# CHECK-NEXT: [0,98] . . . .D==eE---R.. vpandn %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,99] . . . .D===eE--R.. vandnps %zmm2, %zmm2, %zmm5 -# CHECK-NEXT: [0,100] . . . .D===eE--R.. vandnpd %zmm1, %zmm1, %zmm5 -# CHECK-NEXT: [0,101] . . . .D======eER. vpandnd %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,102] . . . . D=====eER. vpandnq %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,103] . . . . D=====eER. vpandnd %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,104] . . . . D======eER vpandnq %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,105] . . . . D======eER vpandnd %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,106] . . . . D======eER vpandnq %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,107] . . . . D--------R xorps %xmm0, %xmm0 -# CHECK-NEXT: [0,108] . . . . D-------R xorpd %xmm1, %xmm1 -# CHECK-NEXT: [0,109] . . . . D-------R vxorps %xmm2, %xmm2, %xmm2 -# CHECK-NEXT: [0,110] . . . . D-------R vxorpd %xmm1, %xmm1, %xmm1 -# CHECK-NEXT: [0,111] . . . . D-------R vxorps %ymm2, %ymm2, %ymm2 -# CHECK-NEXT: [0,112] . . . . D-------R vxorpd %ymm1, %ymm1, %ymm1 -# CHECK-NEXT: [0,113] . . . . D-------R vxorps %zmm2, %zmm2, %zmm2 -# CHECK-NEXT: [0,114] . . . . D------R vxorpd %zmm1, %zmm1, %zmm1 -# CHECK-NEXT: [0,115] . . . . D=eE---R pxor %mm2, %mm2 -# CHECK-NEXT: [0,116] . . . . D------R pxor %xmm2, %xmm2 -# CHECK-NEXT: [0,117] . . . . D------R vpxor %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,118] . . . . D------R vpxor %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: [0,119] . . . . D------R vpxord %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,120] . . . . D-----R vpxorq %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: [0,121] . . . . D-----R vpxord %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,122] . . . . D-----R vpxorq %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: [0,123] . . . . D-----R vpxord %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,124] . . . . D-----R vpxorq %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: [0,125] . . . . D-----R vxorps %xmm4, %xmm4, %xmm5 -# CHECK-NEXT: [0,126] . . . . .D----R vxorpd %xmm1, %xmm1, %xmm3 -# CHECK-NEXT: [0,127] . . . . .D----R vxorps %ymm4, %ymm4, %ymm5 -# CHECK-NEXT: [0,128] . . . . .D----R vxorpd %ymm1, %ymm1, %ymm3 -# CHECK-NEXT: [0,129] . . . . .D----R vxorps %zmm4, %zmm4, %zmm5 -# CHECK-NEXT: [0,130] . . . . .D----R vxorpd %zmm1, %zmm1, %zmm3 -# CHECK-NEXT: [0,131] . . . . .D----R vpxor %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,132] . . . . . D---R vpxor %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: [0,133] . . . . . D---R vpxord %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,134] . . . . . D---R vpxorq %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: [0,135] . . . . . D---R vpxord %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,136] . . . . . D---R vpxorq %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: [0,137] . . . . . D---R vpxord %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: [0,138] . . . . . D--R vpxorq %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DR . . . . . . subl %eax, %eax +# CHECK-NEXT: [0,1] DR . . . . . . subq %rax, %rax +# CHECK-NEXT: [0,2] DR . . . . . . xorl %eax, %eax +# CHECK-NEXT: [0,3] DR . . . . . . xorq %rax, %rax +# CHECK-NEXT: [0,4] DeER . . . . . . pcmpgtb %mm2, %mm2 +# CHECK-NEXT: [0,5] D=eER. . . . . . pcmpgtd %mm2, %mm2 +# CHECK-NEXT: [0,6] .D=eER . . . . . pcmpgtw %mm2, %mm2 +# CHECK-NEXT: [0,7] .D---R . . . . . pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: [0,8] .D---R . . . . . pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: [0,9] .D---R . . . . . pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: [0,10] .D---R . . . . . pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: [0,11] .D---R . . . . . vpcmpgtb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,12] . D--R . . . . . vpcmpgtd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,13] . D--R . . . . . vpcmpgtq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,14] . D---R . . . . . vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,15] . D---R . . . . . vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,16] . D---R . . . . . vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,17] . D---R . . . . . vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,18] . D--R . . . . . vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,19] . D--R . . . . . vpcmpgtb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,20] . D--R . . . . . vpcmpgtd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,21] . D--R . . . . . vpcmpgtq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,22] . D---R . . . . . vpcmpgtw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,23] . D---R . . . . . vpcmpgtb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,24] . D--R . . . . . vpcmpgtd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,25] . D--R . . . . . vpcmpgtq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,26] . D--R . . . . . vpcmpgtw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,27] . DeER . . . . . psubb %mm2, %mm2 +# CHECK-NEXT: [0,28] . D=eER . . . . . psubd %mm2, %mm2 +# CHECK-NEXT: [0,29] . D==eER. . . . . psubq %mm2, %mm2 +# CHECK-NEXT: [0,30] . D==eER . . . . psubw %mm2, %mm2 +# CHECK-NEXT: [0,31] . D----R . . . . psubb %xmm2, %xmm2 +# CHECK-NEXT: [0,32] . D----R . . . . psubd %xmm2, %xmm2 +# CHECK-NEXT: [0,33] . D----R . . . . psubq %xmm2, %xmm2 +# CHECK-NEXT: [0,34] . D----R . . . . psubw %xmm2, %xmm2 +# CHECK-NEXT: [0,35] . D----R . . . . vpsubb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,36] . .D---R . . . . vpsubd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,37] . .D---R . . . . vpsubq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,38] . .D----R . . . . vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,39] . .D----R . . . . vpsubb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,40] . .D----R . . . . vpsubd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,41] . .D----R . . . . vpsubq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,42] . . D---R . . . . vpsubw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,43] . . D---R . . . . vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,44] . . D---R . . . . vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,45] . . D---R . . . . vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,46] . . D----R . . . . vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,47] . . D----R . . . . vpsubb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,48] . . D---R . . . . vpsubd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,49] . . D---R . . . . vpsubq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,50] . . D---R . . . . vpsubw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,51] . . D---R . . . . vpsubb %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,52] . . D---R . . . . vpsubd %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,53] . . D---R . . . . vpsubq %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,54] . . D---R . . . . vpsubw %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,55] . . D---R . . . . vpsubb %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,56] . . D---R . . . . vpsubd %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,57] . . D---R . . . . vpsubq %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,58] . . D---R . . . . vpsubw %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,59] . . D---R . . . . vpsubb %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,60] . . D--R . . . . vpsubd %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,61] . . D--R . . . . vpsubq %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,62] . . D---R. . . . vpsubw %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,63] . . D---R. . . . vpsubb %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,64] . . D---R. . . . vpsubd %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,65] . . D---R. . . . vpsubq %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,66] . . .D--R. . . . vpsubw %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,67] . . .D--R. . . . vpsubb %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,68] . . .D--R. . . . vpsubd %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,69] . . .D--R. . . . vpsubq %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,70] . . .D---R . . . vpsubw %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,71] . . .D---R . . . vpsubb %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,72] . . . D--R . . . vpsubd %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,73] . . . D--R . . . vpsubq %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,74] . . . D--R . . . vpsubw %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,75] . . . DeER . . . andnps %xmm0, %xmm0 +# CHECK-NEXT: [0,76] . . . DeER . . . andnpd %xmm1, %xmm1 +# CHECK-NEXT: [0,77] . . . DeER . . . vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: [0,78] . . . DeER . . . vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: [0,79] . . . DeER . . . vandnps %ymm2, %ymm2, %ymm2 +# CHECK-NEXT: [0,80] . . . D=eER . . . vandnpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [0,81] . . . D=eER . . . vandnps %zmm2, %zmm2, %zmm2 +# CHECK-NEXT: [0,82] . . . D==eER . . . vandnpd %zmm1, %zmm1, %zmm1 +# CHECK-NEXT: [0,83] . . . DeE--R . . . pandn %mm2, %mm2 +# CHECK-NEXT: [0,84] . . . D=eER . . . pandn %xmm2, %xmm2 +# CHECK-NEXT: [0,85] . . . DeE-R . . . vpandn %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,86] . . . D=eER . . . vpandn %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,87] . . . D==eER. . . vpandnd %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,88] . . . D===eER . . vpandnq %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,89] . . . D====eER . . vpandnd %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,90] . . . D====eER . . vpandnq %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,91] . . . D=====eER . . vpandnd %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,92] . . . D======eER. . vpandnq %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,93] . . . D=eE-----R. . vandnps %xmm2, %xmm2, %xmm5 +# CHECK-NEXT: [0,94] . . . D=eE-----R. . vandnpd %xmm1, %xmm1, %xmm5 +# CHECK-NEXT: [0,95] . . . D==eE----R. . vpandn %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,96] . . . .D=eE----R. . vandnps %ymm2, %ymm2, %ymm5 +# CHECK-NEXT: [0,97] . . . .D==eE---R. . vandnpd %ymm1, %ymm1, %ymm5 +# CHECK-NEXT: [0,98] . . . .D==eE---R. . vpandn %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,99] . . . .D===eE--R. . vandnps %zmm2, %zmm2, %zmm5 +# CHECK-NEXT: [0,100] . . . .D===eE---R . vandnpd %zmm1, %zmm1, %zmm5 +# CHECK-NEXT: [0,101] . . . .D======eER . vpandnd %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,102] . . . . D=====eER . vpandnq %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,103] . . . . D=====eER . vpandnd %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,104] . . . . D======eER . vpandnq %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,105] . . . . D======eER . vpandnd %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,106] . . . . D======eER . vpandnq %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,107] . . . . D--------R . xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,108] . . . . D-------R . xorpd %xmm1, %xmm1 +# CHECK-NEXT: [0,109] . . . . D-------R . vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: [0,110] . . . . D-------R . vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: [0,111] . . . . D-------R . vxorps %ymm2, %ymm2, %ymm2 +# CHECK-NEXT: [0,112] . . . . D--------R . vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [0,113] . . . . D--------R . vxorps %zmm2, %zmm2, %zmm2 +# CHECK-NEXT: [0,114] . . . . D-------R . vxorpd %zmm1, %zmm1, %zmm1 +# CHECK-NEXT: [0,115] . . . . D=eE----R . pxor %mm2, %mm2 +# CHECK-NEXT: [0,116] . . . . D-------R . pxor %xmm2, %xmm2 +# CHECK-NEXT: [0,117] . . . . D-------R . vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,118] . . . . D-------R . vpxor %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: [0,119] . . . . D-------R . vpxord %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,120] . . . . D-------R . vpxorq %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: [0,121] . . . . D-------R . vpxord %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,122] . . . . D-------R . vpxorq %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: [0,123] . . . . D-------R . vpxord %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,124] . . . . D-------R . vpxorq %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: [0,125] . . . . D-------R . vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: [0,126] . . . . .D------R . vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: [0,127] . . . . .D------R . vxorps %ymm4, %ymm4, %ymm5 +# CHECK-NEXT: [0,128] . . . . .D-------R. vxorpd %ymm1, %ymm1, %ymm3 +# CHECK-NEXT: [0,129] . . . . .D-------R. vxorps %zmm4, %zmm4, %zmm5 +# CHECK-NEXT: [0,130] . . . . .D-------R. vxorpd %zmm1, %zmm1, %zmm3 +# CHECK-NEXT: [0,131] . . . . .D-------R. vpxor %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,132] . . . . . D------R. vpxor %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: [0,133] . . . . . D------R. vpxord %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,134] . . . . . D------R. vpxorq %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: [0,135] . . . . . D------R. vpxord %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,136] . . . . . D-------R vpxorq %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: [0,137] . . . . . D-------R vpxord %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: [0,138] . . . . . D------R vpxorq %zmm19, %zmm19, %zmm21 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -651,19 +651,19 @@ vpxorq %zmm19, %zmm19, %zmm21 # CHECK-NEXT: 11. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 12. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 13. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 14. 1 0.0 0.0 2.0 vpcmpgtw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 15. 1 0.0 0.0 2.0 vpcmpgtb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 16. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 17. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 18. 1 0.0 0.0 1.0 vpcmpgtw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 19. 1 0.0 0.0 1.0 vpcmpgtb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 20. 1 0.0 0.0 1.0 vpcmpgtd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 21. 1 0.0 0.0 1.0 vpcmpgtq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 22. 1 0.0 0.0 1.0 vpcmpgtw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 23. 1 0.0 0.0 1.0 vpcmpgtb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 24. 1 0.0 0.0 0.0 vpcmpgtd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 25. 1 0.0 0.0 0.0 vpcmpgtq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 26. 1 0.0 0.0 0.0 vpcmpgtw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 14. 1 0.0 0.0 3.0 vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 15. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 16. 1 0.0 0.0 3.0 vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 17. 1 0.0 0.0 3.0 vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 18. 1 0.0 0.0 2.0 vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 19. 1 0.0 0.0 2.0 vpcmpgtb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 20. 1 0.0 0.0 2.0 vpcmpgtd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 21. 1 0.0 0.0 2.0 vpcmpgtq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 22. 1 0.0 0.0 3.0 vpcmpgtw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 23. 1 0.0 0.0 3.0 vpcmpgtb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 24. 1 0.0 0.0 2.0 vpcmpgtd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 25. 1 0.0 0.0 2.0 vpcmpgtq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 26. 1 0.0 0.0 2.0 vpcmpgtw %ymm3, %ymm3, %ymm5 # CHECK-NEXT: 27. 1 1.0 1.0 0.0 psubb %mm2, %mm2 # CHECK-NEXT: 28. 1 2.0 0.0 0.0 psubd %mm2, %mm2 # CHECK-NEXT: 29. 1 3.0 0.0 0.0 psubq %mm2, %mm2 @@ -675,43 +675,43 @@ vpxorq %zmm19, %zmm19, %zmm21 # CHECK-NEXT: 35. 1 0.0 0.0 4.0 vpsubb %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 36. 1 0.0 0.0 3.0 vpsubd %xmm3, %xmm3, %xmm3 # CHECK-NEXT: 37. 1 0.0 0.0 3.0 vpsubq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 38. 1 0.0 0.0 3.0 vpsubw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 39. 1 0.0 0.0 3.0 vpsubb %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 40. 1 0.0 0.0 3.0 vpsubd %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 41. 1 0.0 0.0 3.0 vpsubq %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 42. 1 0.0 0.0 2.0 vpsubw %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 43. 1 0.0 0.0 2.0 vpsubb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 44. 1 0.0 0.0 2.0 vpsubd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 45. 1 0.0 0.0 2.0 vpsubq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 46. 1 0.0 0.0 2.0 vpsubw %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 47. 1 0.0 0.0 2.0 vpsubb %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 48. 1 0.0 0.0 1.0 vpsubd %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 49. 1 0.0 0.0 1.0 vpsubq %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 50. 1 0.0 0.0 1.0 vpsubw %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 51. 1 0.0 0.0 1.0 vpsubb %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: 52. 1 0.0 0.0 1.0 vpsubd %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: 53. 1 0.0 0.0 1.0 vpsubq %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: 54. 1 0.0 0.0 0.0 vpsubw %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: 55. 1 0.0 0.0 0.0 vpsubb %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: 56. 1 0.0 0.0 0.0 vpsubd %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: 57. 1 0.0 0.0 0.0 vpsubq %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: 58. 1 0.0 0.0 0.0 vpsubw %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: 59. 1 0.0 0.0 0.0 vpsubb %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: 60. 1 0.0 0.0 0.0 vpsubd %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: 61. 1 0.0 0.0 0.0 vpsubq %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: 62. 1 0.0 0.0 0.0 vpsubw %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: 63. 1 0.0 0.0 0.0 vpsubb %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: 64. 1 0.0 0.0 0.0 vpsubd %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: 65. 1 0.0 0.0 0.0 vpsubq %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: 66. 1 0.0 0.0 0.0 vpsubw %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: 67. 1 0.0 0.0 0.0 vpsubb %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: 68. 1 0.0 0.0 0.0 vpsubd %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: 69. 1 0.0 0.0 0.0 vpsubq %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: 70. 1 0.0 0.0 0.0 vpsubw %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: 71. 1 0.0 0.0 0.0 vpsubb %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: 72. 1 0.0 0.0 0.0 vpsubd %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: 73. 1 0.0 0.0 0.0 vpsubq %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: 74. 1 0.0 0.0 0.0 vpsubw %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 38. 1 0.0 0.0 4.0 vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 39. 1 0.0 0.0 4.0 vpsubb %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 40. 1 0.0 0.0 4.0 vpsubd %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 41. 1 0.0 0.0 4.0 vpsubq %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 42. 1 0.0 0.0 3.0 vpsubw %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 43. 1 0.0 0.0 3.0 vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 44. 1 0.0 0.0 3.0 vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 45. 1 0.0 0.0 3.0 vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 46. 1 0.0 0.0 4.0 vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 47. 1 0.0 0.0 4.0 vpsubb %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 48. 1 0.0 0.0 3.0 vpsubd %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 49. 1 0.0 0.0 3.0 vpsubq %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 50. 1 0.0 0.0 3.0 vpsubw %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 51. 1 0.0 0.0 3.0 vpsubb %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: 52. 1 0.0 0.0 3.0 vpsubd %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: 53. 1 0.0 0.0 3.0 vpsubq %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: 54. 1 0.0 0.0 3.0 vpsubw %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: 55. 1 0.0 0.0 3.0 vpsubb %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: 56. 1 0.0 0.0 3.0 vpsubd %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: 57. 1 0.0 0.0 3.0 vpsubq %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: 58. 1 0.0 0.0 3.0 vpsubw %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: 59. 1 0.0 0.0 3.0 vpsubb %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: 60. 1 0.0 0.0 2.0 vpsubd %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: 61. 1 0.0 0.0 2.0 vpsubq %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: 62. 1 0.0 0.0 3.0 vpsubw %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: 63. 1 0.0 0.0 3.0 vpsubb %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: 64. 1 0.0 0.0 3.0 vpsubd %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: 65. 1 0.0 0.0 3.0 vpsubq %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: 66. 1 0.0 0.0 2.0 vpsubw %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: 67. 1 0.0 0.0 2.0 vpsubb %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: 68. 1 0.0 0.0 2.0 vpsubd %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: 69. 1 0.0 0.0 2.0 vpsubq %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: 70. 1 0.0 0.0 3.0 vpsubw %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: 71. 1 0.0 0.0 3.0 vpsubb %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 72. 1 0.0 0.0 2.0 vpsubd %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 73. 1 0.0 0.0 2.0 vpsubq %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 74. 1 0.0 0.0 2.0 vpsubw %zmm19, %zmm19, %zmm21 # CHECK-NEXT: 75. 1 1.0 1.0 0.0 andnps %xmm0, %xmm0 # CHECK-NEXT: 76. 1 1.0 1.0 0.0 andnpd %xmm1, %xmm1 # CHECK-NEXT: 77. 1 1.0 1.0 0.0 vandnps %xmm2, %xmm2, %xmm2 @@ -737,7 +737,7 @@ vpxorq %zmm19, %zmm19, %zmm21 # CHECK-NEXT: 97. 1 3.0 2.0 3.0 vandnpd %ymm1, %ymm1, %ymm5 # CHECK-NEXT: 98. 1 3.0 2.0 3.0 vpandn %ymm3, %ymm3, %ymm5 # CHECK-NEXT: 99. 1 4.0 3.0 2.0 vandnps %zmm2, %zmm2, %zmm5 -# CHECK-NEXT: 100. 1 4.0 3.0 2.0 vandnpd %zmm1, %zmm1, %zmm5 +# CHECK-NEXT: 100. 1 4.0 3.0 3.0 vandnpd %zmm1, %zmm1, %zmm5 # CHECK-NEXT: 101. 1 7.0 0.0 0.0 vpandnd %xmm19, %xmm19, %xmm21 # CHECK-NEXT: 102. 1 6.0 0.0 0.0 vpandnq %xmm19, %xmm19, %xmm21 # CHECK-NEXT: 103. 1 6.0 0.0 0.0 vpandnd %ymm19, %ymm19, %ymm21 @@ -749,31 +749,31 @@ vpxorq %zmm19, %zmm19, %zmm21 # CHECK-NEXT: 109. 1 0.0 0.0 7.0 vxorps %xmm2, %xmm2, %xmm2 # CHECK-NEXT: 110. 1 0.0 0.0 7.0 vxorpd %xmm1, %xmm1, %xmm1 # CHECK-NEXT: 111. 1 0.0 0.0 7.0 vxorps %ymm2, %ymm2, %ymm2 -# CHECK-NEXT: 112. 1 0.0 0.0 7.0 vxorpd %ymm1, %ymm1, %ymm1 -# CHECK-NEXT: 113. 1 0.0 0.0 7.0 vxorps %zmm2, %zmm2, %zmm2 -# CHECK-NEXT: 114. 1 0.0 0.0 6.0 vxorpd %zmm1, %zmm1, %zmm1 -# CHECK-NEXT: 115. 1 2.0 2.0 3.0 pxor %mm2, %mm2 -# CHECK-NEXT: 116. 1 0.0 0.0 6.0 pxor %xmm2, %xmm2 -# CHECK-NEXT: 117. 1 0.0 0.0 6.0 vpxor %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 118. 1 0.0 0.0 6.0 vpxor %ymm3, %ymm3, %ymm3 -# CHECK-NEXT: 119. 1 0.0 0.0 6.0 vpxord %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: 120. 1 0.0 0.0 5.0 vpxorq %xmm19, %xmm19, %xmm19 -# CHECK-NEXT: 121. 1 0.0 0.0 5.0 vpxord %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: 122. 1 0.0 0.0 5.0 vpxorq %ymm19, %ymm19, %ymm19 -# CHECK-NEXT: 123. 1 0.0 0.0 5.0 vpxord %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: 124. 1 0.0 0.0 5.0 vpxorq %zmm19, %zmm19, %zmm19 -# CHECK-NEXT: 125. 1 0.0 0.0 5.0 vxorps %xmm4, %xmm4, %xmm5 -# CHECK-NEXT: 126. 1 0.0 0.0 4.0 vxorpd %xmm1, %xmm1, %xmm3 -# CHECK-NEXT: 127. 1 0.0 0.0 4.0 vxorps %ymm4, %ymm4, %ymm5 -# CHECK-NEXT: 128. 1 0.0 0.0 4.0 vxorpd %ymm1, %ymm1, %ymm3 -# CHECK-NEXT: 129. 1 0.0 0.0 4.0 vxorps %zmm4, %zmm4, %zmm5 -# CHECK-NEXT: 130. 1 0.0 0.0 4.0 vxorpd %zmm1, %zmm1, %zmm3 -# CHECK-NEXT: 131. 1 0.0 0.0 4.0 vpxor %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 132. 1 0.0 0.0 3.0 vpxor %ymm3, %ymm3, %ymm5 -# CHECK-NEXT: 133. 1 0.0 0.0 3.0 vpxord %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: 134. 1 0.0 0.0 3.0 vpxorq %xmm19, %xmm19, %xmm21 -# CHECK-NEXT: 135. 1 0.0 0.0 3.0 vpxord %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: 136. 1 0.0 0.0 3.0 vpxorq %ymm19, %ymm19, %ymm21 -# CHECK-NEXT: 137. 1 0.0 0.0 3.0 vpxord %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: 138. 1 0.0 0.0 2.0 vpxorq %zmm19, %zmm19, %zmm21 -# CHECK-NEXT: 1 0.9 0.2 2.0 <total> +# CHECK-NEXT: 112. 1 0.0 0.0 8.0 vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: 113. 1 0.0 0.0 8.0 vxorps %zmm2, %zmm2, %zmm2 +# CHECK-NEXT: 114. 1 0.0 0.0 7.0 vxorpd %zmm1, %zmm1, %zmm1 +# CHECK-NEXT: 115. 1 2.0 2.0 4.0 pxor %mm2, %mm2 +# CHECK-NEXT: 116. 1 0.0 0.0 7.0 pxor %xmm2, %xmm2 +# CHECK-NEXT: 117. 1 0.0 0.0 7.0 vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 118. 1 0.0 0.0 7.0 vpxor %ymm3, %ymm3, %ymm3 +# CHECK-NEXT: 119. 1 0.0 0.0 7.0 vpxord %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: 120. 1 0.0 0.0 7.0 vpxorq %xmm19, %xmm19, %xmm19 +# CHECK-NEXT: 121. 1 0.0 0.0 7.0 vpxord %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: 122. 1 0.0 0.0 7.0 vpxorq %ymm19, %ymm19, %ymm19 +# CHECK-NEXT: 123. 1 0.0 0.0 7.0 vpxord %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: 124. 1 0.0 0.0 7.0 vpxorq %zmm19, %zmm19, %zmm19 +# CHECK-NEXT: 125. 1 0.0 0.0 7.0 vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: 126. 1 0.0 0.0 6.0 vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: 127. 1 0.0 0.0 6.0 vxorps %ymm4, %ymm4, %ymm5 +# CHECK-NEXT: 128. 1 0.0 0.0 7.0 vxorpd %ymm1, %ymm1, %ymm3 +# CHECK-NEXT: 129. 1 0.0 0.0 7.0 vxorps %zmm4, %zmm4, %zmm5 +# CHECK-NEXT: 130. 1 0.0 0.0 7.0 vxorpd %zmm1, %zmm1, %zmm3 +# CHECK-NEXT: 131. 1 0.0 0.0 7.0 vpxor %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 132. 1 0.0 0.0 6.0 vpxor %ymm3, %ymm3, %ymm5 +# CHECK-NEXT: 133. 1 0.0 0.0 6.0 vpxord %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: 134. 1 0.0 0.0 6.0 vpxorq %xmm19, %xmm19, %xmm21 +# CHECK-NEXT: 135. 1 0.0 0.0 6.0 vpxord %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: 136. 1 0.0 0.0 7.0 vpxorq %ymm19, %ymm19, %ymm21 +# CHECK-NEXT: 137. 1 0.0 0.0 7.0 vpxord %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 138. 1 0.0 0.0 6.0 vpxorq %zmm19, %zmm19, %zmm21 +# CHECK-NEXT: 1 0.9 0.2 3.1 <total> diff --git a/llvm/test/tools/llvm-mca/X86/stack-engine-pop.s b/llvm/test/tools/llvm-mca/X86/stack-engine-pop.s new file mode 100644 index 0000000..2ffb52a --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/stack-engine-pop.s @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -timeline -iterations=2 < %s | FileCheck %s + +movq $0x80, %rsp +popq %rax +popq %rcx +popq %rdx +popq %rbx +popq %r12 + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 12 +# CHECK-NEXT: Total Cycles: 14 +# CHECK-NEXT: Total uOps: 22 + +# CHECK: Dispatch Width: 6 +# CHECK-NEXT: uOps Per Cycle: 1.57 +# CHECK-NEXT: IPC: 0.86 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.25 movq $128, %rsp +# CHECK-NEXT: 2 6 0.50 * popq %rax +# CHECK-NEXT: 2 6 0.50 * popq %rcx +# CHECK-NEXT: 2 6 0.50 * popq %rdx +# CHECK-NEXT: 2 6 0.50 * popq %rbx +# CHECK-NEXT: 2 6 0.50 * popq %r12 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SKLDivider +# CHECK-NEXT: [1] - SKLFPDivider +# CHECK-NEXT: [2] - SKLPort0 +# CHECK-NEXT: [3] - SKLPort1 +# CHECK-NEXT: [4] - SKLPort2 +# CHECK-NEXT: [5] - SKLPort3 +# CHECK-NEXT: [6] - SKLPort4 +# CHECK-NEXT: [7] - SKLPort5 +# CHECK-NEXT: [8] - SKLPort6 +# CHECK-NEXT: [9] - SKLPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 1.50 1.50 2.50 2.50 - 1.50 1.50 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - - - - - 0.50 0.50 - movq $128, %rsp +# CHECK-NEXT: - - 0.50 - 0.50 0.50 - 0.50 - - popq %rax +# CHECK-NEXT: - - - 0.50 0.50 0.50 - - 0.50 - popq %rcx +# CHECK-NEXT: - - 0.50 - 0.50 0.50 - 0.50 - - popq %rdx +# CHECK-NEXT: - - - 0.50 0.50 0.50 - - 0.50 - popq %rbx +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - popq %r12 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . movq $128, %rsp +# CHECK-NEXT: [0,1] D=eeeeeeER. . popq %rax +# CHECK-NEXT: [0,2] D=eeeeeeER. . popq %rcx +# CHECK-NEXT: [0,3] .D=eeeeeeER . popq %rdx +# CHECK-NEXT: [0,4] .D=eeeeeeER . popq %rbx +# CHECK-NEXT: [0,5] .D==eeeeeeER . popq %r12 +# CHECK-NEXT: [1,0] . DeE------R . movq $128, %rsp +# CHECK-NEXT: [1,1] . D=eeeeeeER . popq %rax +# CHECK-NEXT: [1,2] . D==eeeeeeER. popq %rcx +# CHECK-NEXT: [1,3] . D=eeeeeeER. popq %rdx +# CHECK-NEXT: [1,4] . D==eeeeeeER popq %rbx +# CHECK-NEXT: [1,5] . D==eeeeeeER popq %r12 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 1.0 1.0 3.0 movq $128, %rsp +# CHECK-NEXT: 1. 2 2.0 0.0 0.0 popq %rax +# CHECK-NEXT: 2. 2 2.5 0.5 0.0 popq %rcx +# CHECK-NEXT: 3. 2 2.0 1.0 0.0 popq %rdx +# CHECK-NEXT: 4. 2 2.5 1.5 0.0 popq %rbx +# CHECK-NEXT: 5. 2 3.0 2.0 0.0 popq %r12 +# CHECK-NEXT: 2 2.2 1.0 0.5 <total> diff --git a/llvm/test/tools/llvm-mca/X86/stack-engine-push.s b/llvm/test/tools/llvm-mca/X86/stack-engine-push.s new file mode 100644 index 0000000..fc394d4 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/stack-engine-push.s @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -timeline -iterations=2 < %s | FileCheck %s + +movq $0x80, %rsp +pushq %rax +pushq %rcx +pushq %rdx +pushq %rbx +pushq %r12 + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 12 +# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total uOps: 32 + +# CHECK: Dispatch Width: 6 +# CHECK-NEXT: uOps Per Cycle: 2.13 +# CHECK-NEXT: IPC: 0.80 +# CHECK-NEXT: Block RThroughput: 5.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.25 movq $128, %rsp +# CHECK-NEXT: 3 2 1.00 * pushq %rax +# CHECK-NEXT: 3 2 1.00 * pushq %rcx +# CHECK-NEXT: 3 2 1.00 * pushq %rdx +# CHECK-NEXT: 3 2 1.00 * pushq %rbx +# CHECK-NEXT: 3 2 1.00 * pushq %r12 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SKLDivider +# CHECK-NEXT: [1] - SKLFPDivider +# CHECK-NEXT: [2] - SKLPort0 +# CHECK-NEXT: [3] - SKLPort1 +# CHECK-NEXT: [4] - SKLPort2 +# CHECK-NEXT: [5] - SKLPort3 +# CHECK-NEXT: [6] - SKLPort4 +# CHECK-NEXT: [7] - SKLPort5 +# CHECK-NEXT: [8] - SKLPort6 +# CHECK-NEXT: [9] - SKLPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 1.50 1.50 1.50 1.50 5.00 1.50 1.50 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - - - - - - 1.00 - movq $128, %rsp +# CHECK-NEXT: - - 0.50 - 0.50 - 1.00 0.50 - 0.50 pushq %rax +# CHECK-NEXT: - - - 0.50 - 0.50 1.00 - 0.50 0.50 pushq %rcx +# CHECK-NEXT: - - 0.50 - 0.50 0.50 1.00 0.50 - - pushq %rdx +# CHECK-NEXT: - - - 0.50 0.50 - 1.00 0.50 - 0.50 pushq %rbx +# CHECK-NEXT: - - 0.50 0.50 - 0.50 1.00 - - 0.50 pushq %r12 + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . movq $128, %rsp +# CHECK-NEXT: [0,1] D=eeER . . pushq %rax +# CHECK-NEXT: [0,2] .D=eeER . . pushq %rcx +# CHECK-NEXT: [0,3] .D==eeER . . pushq %rdx +# CHECK-NEXT: [0,4] . D==eeER . . pushq %rbx +# CHECK-NEXT: [0,5] . D===eeER. . pushq %r12 +# CHECK-NEXT: [1,0] . DeE---R. . movq $128, %rsp +# CHECK-NEXT: [1,1] . D===eeER . pushq %rax +# CHECK-NEXT: [1,2] . D===eeER . pushq %rcx +# CHECK-NEXT: [1,3] . D====eeER . pushq %rdx +# CHECK-NEXT: [1,4] . D====eeER. pushq %rbx +# CHECK-NEXT: [1,5] . D=====eeER pushq %r12 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 1.0 1.0 1.5 movq $128, %rsp +# CHECK-NEXT: 1. 2 3.0 0.5 0.0 pushq %rax +# CHECK-NEXT: 2. 2 3.0 1.0 0.0 pushq %rcx +# CHECK-NEXT: 3. 2 4.0 1.0 0.0 pushq %rdx +# CHECK-NEXT: 4. 2 4.0 1.0 0.0 pushq %rbx +# CHECK-NEXT: 5. 2 5.0 1.0 0.0 pushq %r12 +# CHECK-NEXT: 2 3.3 0.9 0.3 <total> diff --git a/llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test b/llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test new file mode 100644 index 0000000..b63bc09 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test @@ -0,0 +1,294 @@ +## Tests that the copied DXContainer is identical to the original. + +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy %t %t.out +# RUN: cmp %t %t.out + +## The DXContainer described below was generated with: + +## `clang-dxc -T cs_6_7 test.hlsl /Fo temp.dxo` +## `obj2yaml temp.dxo` + +## ``` test.hlsl +## [RootSignature("")] +## [numthreads(1,1,1)] +## void main() {} +## ``` + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 + FileSize: 1984 + PartCount: 7 + PartOffsets: [ 60, 1792, 1808, 1836, 1852, 1868, 1900 ] +Parts: + - Name: DXIL + Size: 1724 + Program: + MajorVersion: 6 + MinorVersion: 7 + ShaderKind: 5 + Size: 431 + DXILMajorVersion: 1 + DXILMinorVersion: 7 + DXILSize: 1700 + DXIL: [ 0x42, 0x43, 0xC0, 0xDE, 0x21, 0xC, 0x0, 0x0, 0xA6, + 0x1, 0x0, 0x0, 0xB, 0x82, 0x20, 0x0, 0x2, 0x0, + 0x0, 0x0, 0x13, 0x0, 0x0, 0x0, 0x7, 0x81, 0x23, + 0x91, 0x41, 0xC8, 0x4, 0x49, 0x6, 0x10, 0x32, + 0x39, 0x92, 0x1, 0x84, 0xC, 0x25, 0x5, 0x8, 0x19, + 0x1E, 0x4, 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Name: SFI0 + Size: 8 + - Name: HASH + Size: 20 + Hash: + IncludesSource: false + Digest: [ 0x9F, 0xD1, 0xD9, 0xE2, 0x49, 0xFB, 0x3A, 0x6C, + 0x8C, 0x14, 0x8A, 0x96, 0x1C, 0x7D, 0x85, 0xA9 ] + - Name: ISG1 + Size: 8 + Signature: + Parameters: [] + - Name: OSG1 + Size: 8 + Signature: + Parameters: [] + - Name: RTS0 + Size: 24 + RootSignature: + Version: 2 + NumRootParameters: 0 + RootParametersOffset: 24 + NumStaticSamplers: 0 + StaticSamplersOffset: 24 + Parameters: [] + - Name: PSV0 + Size: 76 + PSVInfo: + Version: 3 + ShaderStage: 5 + MinimumWaveLaneCount: 0 + MaximumWaveLaneCount: 4294967295 + UsesViewID: 0 + SigInputVectors: 0 + SigOutputVectors: [ 0, 0, 0, 0 ] + NumThreadsX: 1 + NumThreadsY: 1 + NumThreadsZ: 1 + EntryName: main + ResourceStride: 24 + Resources: [] + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] + InputOutputMap: + - [ ] + - [ ] + - [ ] + - [ ] +... diff --git a/llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test b/llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test new file mode 100644 index 0000000..b7720c8 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test @@ -0,0 +1,42 @@ +## Tests that the copied DXContainer is identical to the original, ensuring all +## the different headers are correctly handled. + +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy %t %t.out +# RUN: cmp %t %t.out + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 + FileSize: 1996 + PartCount: 7 + PartOffsets: [ 60, 76, 92, 108, 236, 1932, 1960 ] +Parts: + - Name: FKE0 + Size: 8 + - Name: FKE1 + Size: 8 + - Name: FKE2 + Size: 8 + - Name: FKE3 + Size: 120 + - Name: FKE4 + Size: 1688 + - Name: FKE5 + Size: 20 + - Name: DXIL + Size: 28 + Program: + MajorVersion: 6 + MinorVersion: 5 + ShaderKind: 5 + Size: 8 + DXILMajorVersion: 1 + DXILMinorVersion: 5 + DXILSize: 4 + DXIL: [ 0x42, 0x43, 0xC0, 0xDE, ] +... diff --git a/llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test b/llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test new file mode 100644 index 0000000..3209955 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test @@ -0,0 +1,43 @@ +## Check that llvm-objcopy reports a suitable error when it +## encounters an invalid input during reading. + +## We can't have multiple DXIL parts. +# RUN: yaml2obj %s --docnum=1 -o %t1 +# RUN: not llvm-objcopy %t1 %t1.out 2>&1 | FileCheck %s -DFILE=%t1 --check-prefix=ERROR1 + +# ERROR1: error: '[[FILE]]': More than one DXIL part is present in the file + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 + PartCount: 2 +Parts: + - Name: DXIL + Size: 28 + - Name: DXIL + Size: 28 +... + +## The first part offset is out of file bounds. +# RUN: yaml2obj %s --docnum=2 -o %t2 +# RUN: not llvm-objcopy %t2 %t2.out 2>&1 | FileCheck %s -DFILE=%t2 --check-prefix=ERROR2 + +# ERROR2: error: '[[FILE]]': Reading structure out of file bounds + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 2 + Minor: 0 + PartCount: 1 + PartOffsets: [ 48 ] +Parts: + - Name: DXIL + Size: 28 +... diff --git a/llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test b/llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test new file mode 100644 index 0000000..4f4a138 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test @@ -0,0 +1,51 @@ +## Tests that the copied DXContainer correctly has the specified headers +## removed. + +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy --remove-section=FKE1 --remove-section=FKE4 %t %t.out +# RUN: obj2yaml %t.out | FileCheck %s + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 +## FileSize = 1996 - 8 (FKE1 content) - 1688 (FKE4 content) +## - 8 (2 part offsets) - 16 (2 part headers) +## = 276 +# CHECK: FileSize: 276 + FileSize: 1996 +# CHECK-NEXT: PartCount: 5 + PartCount: 7 +# CHECK-NEXT: PartOffsets: [ 52, 68, 84, 212, 240 ] + PartOffsets: [ 60, 76, 92, 108, 236, 1932, 1960 ] +Parts: +# CHECK-NEXT: Parts +# CHECK-NOT: FKE1 +# CHECK-NOT: FKE4 + - Name: FKE0 + Size: 8 + - Name: FKE1 + Size: 8 + - Name: FKE2 + Size: 8 + - Name: FKE3 + Size: 120 + - Name: FKE4 + Size: 1688 + - Name: FKE5 + Size: 20 + - Name: DXIL + Size: 28 + Program: + MajorVersion: 6 + MinorVersion: 5 + ShaderKind: 5 + Size: 8 + DXILMajorVersion: 1 + DXILMinorVersion: 5 + DXILSize: 4 + DXIL: [ 0x42, 0x43, 0xC0, 0xDE, ] +... diff --git a/llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test b/llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test new file mode 100644 index 0000000..585c4d6 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test @@ -0,0 +1,302 @@ +## Tests that the RTS0 (root signature) part is correctly removed from the +## copied DXContainer. + +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy --remove-section=RTS0 %t %t.out +# RUN: obj2yaml %t.out | FileCheck %s + +## The DXContainer described below was generated with: + +## `clang-dxc -T cs_6_7 test.hlsl /Fo temp.dxo` +## `obj2yaml temp.dxo` + +## ``` test.hlsl +## [RootSignature("")] +## [numthreads(1,1,1)] +## void main() {} +## ``` + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 +## FileSize = 1984 - 24 (RTS0 content) - 4 (1 part offset) - 8 (1 part header) +## = 1948 +# CHECK: FileSize: 1948 + FileSize: 1984 +# CHECK-NEXT: PartCount: 6 + PartCount: 7 +# CHECK-NEXT: PartOffsets: [ 56, 1788, 1804, 1832, 1848, 1864 ] + PartOffsets: [ 60, 1792, 1808, 1836, 1852, 1868, 1900 ] +Parts: +# CHECK-NEXT: Parts +# CHECK-NOT: RTS0 + - Name: DXIL + Size: 1724 + Program: + MajorVersion: 6 + MinorVersion: 7 + ShaderKind: 5 + Size: 431 + DXILMajorVersion: 1 + DXILMinorVersion: 7 + DXILSize: 1700 + DXIL: [ 0x42, 0x43, 0xC0, 0xDE, 0x21, 0xC, 0x0, 0x0, 0xA6, + 0x1, 0x0, 0x0, 0xB, 0x82, 0x20, 0x0, 0x2, 0x0, + 0x0, 0x0, 0x13, 0x0, 0x0, 0x0, 0x7, 0x81, 0x23, + 0x91, 0x41, 0xC8, 0x4, 0x49, 0x6, 0x10, 0x32, + 0x39, 0x92, 0x1, 0x84, 0xC, 0x25, 0x5, 0x8, 0x19, + 0x1E, 0x4, 0x8B, 0x62, 0x80, 0x10, 0x45, 0x2, + 0x42, 0x92, 0xB, 0x42, 0x84, 0x10, 0x32, 0x14, + 0x38, 0x8, 0x18, 0x4B, 0xA, 0x32, 0x42, 0x88, + 0x48, 0x90, 0x14, 0x20, 0x43, 0x46, 0x88, 0xA5, + 0x0, 0x19, 0x32, 0x42, 0xE4, 0x48, 0xE, 0x90, + 0x11, 0x22, 0xC4, 0x50, 0x41, 0x51, 0x81, 0x8C, + 0xE1, 0x83, 0xE5, 0x8A, 0x4, 0x21, 0x46, 0x6, + 0x51, 0x18, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x1B, + 0x90, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0x7, 0xC0, + 0x1, 0x24, 0x80, 0x2, 0x0, 0x0, 0x0, 0x49, 0x18, + 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x13, 0x82, 0x0, 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0x6E, 0x74, 0x73, 0x43, 0x9, 0x24, + 0x13, 0xB1, 0xB1, 0xD9, 0xB5, 0xB9, 0xB4, 0xBD, + 0x91, 0xD5, 0xB1, 0x95, 0xB9, 0x98, 0xB1, 0x85, + 0x9D, 0xCD, 0xD, 0x45, 0x98, 0x28, 0x0, 0x0, 0x71, + 0x20, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x6, 0x40, + 0x30, 0x0, 0xD2, 0x0, 0x0, 0x0, 0x61, 0x20, 0x0, + 0x0, 0x6, 0x0, 0x0, 0x0, 0x13, 0x4, 0x1, 0x86, + 0x3, 0x1, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x7, 0x50, + 0x10, 0xCD, 0x14, 0x61, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0 ] + - Name: SFI0 + Size: 8 + - Name: HASH + Size: 20 + Hash: + IncludesSource: false + Digest: [ 0x9F, 0xD1, 0xD9, 0xE2, 0x49, 0xFB, 0x3A, 0x6C, + 0x8C, 0x14, 0x8A, 0x96, 0x1C, 0x7D, 0x85, 0xA9 ] + - Name: ISG1 + Size: 8 + Signature: + Parameters: [] + - Name: OSG1 + Size: 8 + Signature: + Parameters: [] + - Name: RTS0 + Size: 24 + RootSignature: + Version: 2 + NumRootParameters: 0 + RootParametersOffset: 24 + NumStaticSamplers: 0 + StaticSamplersOffset: 24 + Parameters: [] + - Name: PSV0 + Size: 76 + PSVInfo: + Version: 3 + ShaderStage: 5 + MinimumWaveLaneCount: 0 + MaximumWaveLaneCount: 4294967295 + UsesViewID: 0 + SigInputVectors: 0 + SigOutputVectors: [ 0, 0, 0, 0 ] + NumThreadsX: 1 + NumThreadsY: 1 + NumThreadsZ: 1 + EntryName: main + ResourceStride: 24 + Resources: [] + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] + InputOutputMap: + - [ ] + - [ ] + - [ ] + - [ ] +... diff --git a/llvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test b/llvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test index 8f4993f..66a481a 100644 --- a/llvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test +++ b/llvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test @@ -6,7 +6,6 @@ ## Setting the umask to 0 ensures deterministic permissions across ## test environments. # UNSUPPORTED: system-windows -# REQUIRES: shell # RUN: touch %t # RUN: chmod 0777 %t diff --git a/llvm/test/tools/llvm-objcopy/ELF/respect-umask.test b/llvm/test/tools/llvm-objcopy/ELF/respect-umask.test index 376e33a..02e9b93 100644 --- a/llvm/test/tools/llvm-objcopy/ELF/respect-umask.test +++ b/llvm/test/tools/llvm-objcopy/ELF/respect-umask.test @@ -1,10 +1,8 @@ ## This tests that the umask is respected when ## assigning permissions of output files. -## Windows has no umask so this test makes no sense, nor would -## it work because there is no umask(1) in a Windows environment +## Windows has no umask so this test makes no sense. # UNSUPPORTED: system-windows -# REQUIRES: shell # RUN: rm -f %t # RUN: touch %t diff --git a/llvm/test/tools/llvm-objdump/DXContainer/input-output-signatures.yaml b/llvm/test/tools/llvm-objdump/DXContainer/input-output-signatures.yaml new file mode 100644 index 0000000..ad979d2 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/DXContainer/input-output-signatures.yaml @@ -0,0 +1,167 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump -p %t | FileCheck %s --match-full-lines --strict-whitespace + +## This test covers llvm-objdump printing private headers for the ISG1, OSG1, +## and PSG1 "parts" of the DX container file format. The test uses a few +## absurdly large values and long string names to ensure that the columns in the +## printed table widen correctly. + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 + FileSize: 630 + PartCount: 3 + PartOffsets: [ 64, 124, 184 ] +Parts: + - Name: ISG1 + Size: 52 + Signature: + Parameters: + - Stream: 0 + Name: AAA_HSFoo + Index: 4391238 # This value forces the index column to widen + SystemValue: Undefined + CompType: Float32 + Register: 0 + Mask: 7 + ExclusiveMask: 2 + MinPrecision: Default + - Name: OSG1 + Size: 52 + Signature: + Parameters: + - Stream: 0 + Name: SV_Position + Index: 0 + SystemValue: Position + CompType: Float32 + Register: 2147483647 # This value forces the register column to widen + Mask: 15 + ExclusiveMask: 0 + MinPrecision: Default + - Name: PSG1 + Size: 402 + Signature: + Parameters: + - Stream: 0 + Name: SV_TessFactor + Index: 0 + SystemValue: FinalQuadEdgeTessfactor # The tessfactor forces the SysVal column to widen + CompType: Float32 + Register: 0 + Mask: 8 + ExclusiveMask: 8 + MinPrecision: Default + - Stream: 0 + Name: BBB + Index: 0 + SystemValue: Undefined + CompType: Float32 + Register: 0 + Mask: 7 + ExclusiveMask: 0 + MinPrecision: Default + - Stream: 0 + Name: SV_TessFactor + Index: 1 + SystemValue: FinalQuadEdgeTessfactor + CompType: Float32 + Register: 1 + Mask: 8 + ExclusiveMask: 8 + MinPrecision: Default + - Stream: 0 + Name: BBB + Index: 1 + SystemValue: Undefined + CompType: Float32 + Register: 1 + Mask: 7 + ExclusiveMask: 0 + MinPrecision: Default + - Stream: 0 + Name: SV_TessFactor + Index: 2 + SystemValue: FinalQuadEdgeTessfactor + CompType: Float32 + Register: 2 + Mask: 8 + ExclusiveMask: 8 + MinPrecision: Default + - Stream: 0 + Name: BBB + Index: 2 + SystemValue: Undefined + CompType: Float32 + Register: 2 + Mask: 7 + ExclusiveMask: 0 + MinPrecision: Default + - Stream: 0 + Name: SV_TessFactor + Index: 3 + SystemValue: FinalQuadEdgeTessfactor + CompType: Float32 + Register: 3 + Mask: 8 + ExclusiveMask: 8 + MinPrecision: Default + - Stream: 0 + Name: SV_InsideTessFactor + Index: 0 + SystemValue: FinalQuadInsideTessfactor + CompType: Float32 + Register: 4 + Mask: 8 + ExclusiveMask: 0 + MinPrecision: Default + - Stream: 0 + Name: SV_InsideTessFactor + Index: 1 + SystemValue: FinalQuadInsideTessfactor + CompType: Float32 + Register: 5 + Mask: 8 + ExclusiveMask: 0 + MinPrecision: Default + - Stream: 0 + Name: AVeryLongStringThatWillForceWidening # This value forces name column to widen + Index: 0 + SystemValue: Undefined + CompType: Float32 + Register: 6 + Mask: 15 + ExclusiveMask: 4 + MinPrecision: Default +... + +# CHECK:; Input signature: +# CHECK-NEXT:; +# CHECK-NEXT:; Name Index Mask Register SysValue Format Used +# CHECK-NEXT:; ------------------------ ------- ----- -------- ---------- ------- ----- +# CHECK-NEXT:; AAA_HSFoo 4391238 xyz 0 Undefined Float32 y + +# CHECK:; Output signature: +# CHECK-NEXT:; +# CHECK-NEXT:; Name Index Mask Register SysValue Format Used +# CHECK-NEXT:; ------------------------ ----- ----- ---------- ---------- ------- ----- +# CHECK-NEXT:; SV_Position 0 xyzw 2147483647 Position Float32 + +# CHECK:; Patch Constant signature: +# CHECK-NEXT:; +# CHECK-NEXT:; Name Index Mask Register SysValue Format Used +# CHECK-NEXT:; ------------------------------------ ----- ----- -------- ------------------------- ------- ----- +# CHECK-NEXT:; SV_TessFactor 0 w 0 FinalQuadEdgeTessfactor Float32 w +# CHECK-NEXT:; BBB 0 xyz 0 Undefined Float32 +# CHECK-NEXT:; SV_TessFactor 1 w 1 FinalQuadEdgeTessfactor Float32 w +# CHECK-NEXT:; BBB 1 xyz 1 Undefined Float32 +# CHECK-NEXT:; SV_TessFactor 2 w 2 FinalQuadEdgeTessfactor Float32 w +# CHECK-NEXT:; BBB 2 xyz 2 Undefined Float32 +# CHECK-NEXT:; SV_TessFactor 3 w 3 FinalQuadEdgeTessfactor Float32 w +# CHECK-NEXT:; SV_InsideTessFactor 0 w 4 FinalQuadInsideTessfactor Float32 +# CHECK-NEXT:; SV_InsideTessFactor 1 w 5 FinalQuadInsideTessfactor Float32 +# CHECK-NEXT:; AVeryLongStringThatWillForceWidening 0 xyzw 6 Undefined Float32 z diff --git a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s new file mode 100644 index 0000000..99a4df3 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s @@ -0,0 +1,121 @@ +;; Test disassembly for gfx1250 kernel descriptor. + +; RUN: rm -rf %t && split-file %s %t && cd %t + +;--- 1.s +; RUN: llvm-mc --triple=amdgcn-amd-amdhsa -filetype=obj -mcpu=gfx1250 < 1.s > 1.o +; RUN: llvm-objdump --disassemble-symbols=kernel.kd 1.o | tail -n +7 | tee 1-disasm.s | FileCheck 1.s +; RUN: llvm-mc --triple=amdgcn-amd-amdhsa -filetype=obj -mcpu=gfx1250 < 1-disasm.s > 1-disasm.o +; RUN: cmp 1.o 1-disasm.o +; CHECK: .amdhsa_kernel kernel +; CHECK-NEXT: .amdhsa_group_segment_fixed_size 0 +; CHECK-NEXT: .amdhsa_private_segment_fixed_size 0 +; CHECK-NEXT: .amdhsa_kernarg_size 0 +; CHECK-NEXT: .amdhsa_inst_pref_size 0 +; CHECK-NEXT: ; GLG_EN 0 +; CHECK-NEXT: .amdhsa_named_barrier_count 0 +; CHECK-NEXT: ; ENABLE_DYNAMIC_VGPR 0 +; CHECK-NEXT: ; TCP_SPLIT 0 +; CHECK-NEXT: ; ENABLE_DIDT_THROTTLE 0 +; CHECK-NEXT: ; IMAGE_OP 0 +; CHECK-NEXT: .amdhsa_next_free_vgpr 32 +; CHECK-NEXT: .amdhsa_reserve_vcc 0 +; CHECK-NEXT: .amdhsa_reserve_xnack_mask 0 +; CHECK-NEXT: .amdhsa_next_free_sgpr 8 +; CHECK-NEXT: .amdhsa_float_round_mode_32 0 +; CHECK-NEXT: .amdhsa_float_round_mode_16_64 0 +; CHECK-NEXT: .amdhsa_float_denorm_mode_32 0 +; CHECK-NEXT: .amdhsa_float_denorm_mode_16_64 3 +; CHECK-NEXT: .amdhsa_fp16_overflow 0 +; CHECK-NEXT: ; FLAT_SCRATCH_IS_NV 0 +; CHECK-NEXT: .amdhsa_memory_ordered 1 +; CHECK-NEXT: .amdhsa_forward_progress 1 +; CHECK-NEXT: .amdhsa_round_robin_scheduling 0 +; CHECK-NEXT: .amdhsa_enable_private_segment 0 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_info 0 +; CHECK-NEXT: .amdhsa_system_vgpr_workitem_id 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0 +; CHECK-NEXT: .amdhsa_exception_fp_denorm_src 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_div_zero 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_overflow 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_underflow 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_inexact 0 +; CHECK-NEXT: .amdhsa_exception_int_div_zero 0 +; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 +; CHECK-NEXT: .amdhsa_user_sgpr_queue_ptr 0 +; CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 +; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 0 +; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 0 +; CHECK-NEXT: .amdhsa_uses_cu_stores 1 +; CHECK-NEXT: .amdhsa_wavefront_size32 1 +; CHECK-NEXT: .amdhsa_uses_dynamic_stack 0 +; CHECK-NEXT: .end_amdhsa_kernel +.amdhsa_kernel kernel + .amdhsa_next_free_vgpr 32 + .amdhsa_next_free_sgpr 32 + .amdhsa_inst_pref_size 0 + .amdhsa_uses_cu_stores 1 +.end_amdhsa_kernel + +;--- 2.s +; RUN: llvm-mc --triple=amdgcn-amd-amdhsa -filetype=obj -mcpu=gfx1250 < 2.s > 2.o +; RUN: llvm-objdump --disassemble-symbols=kernel.kd 2.o | tail -n +7 | tee 2-disasm.s | FileCheck 2.s +; RUN: llvm-mc --triple=amdgcn-amd-amdhsa -filetype=obj -mcpu=gfx1250 < 2-disasm.s > 2-disasm.o +; RUN: cmp 2.o 2-disasm.o +; CHECK: .amdhsa_kernel kernel +; CHECK-NEXT: .amdhsa_group_segment_fixed_size 393216 +; CHECK-NEXT: .amdhsa_private_segment_fixed_size 0 +; CHECK-NEXT: .amdhsa_kernarg_size 0 +; CHECK-NEXT: .amdhsa_inst_pref_size 63 +; CHECK-NEXT: ; GLG_EN 0 +; CHECK-NEXT: .amdhsa_named_barrier_count 7 +; CHECK-NEXT: ; ENABLE_DYNAMIC_VGPR 0 +; CHECK-NEXT: ; TCP_SPLIT 0 +; CHECK-NEXT: ; ENABLE_DIDT_THROTTLE 0 +; CHECK-NEXT: ; IMAGE_OP 0 +; CHECK-NEXT: .amdhsa_next_free_vgpr 32 +; CHECK-NEXT: .amdhsa_reserve_vcc 0 +; CHECK-NEXT: .amdhsa_reserve_xnack_mask 0 +; CHECK-NEXT: .amdhsa_next_free_sgpr 8 +; CHECK-NEXT: .amdhsa_float_round_mode_32 0 +; CHECK-NEXT: .amdhsa_float_round_mode_16_64 0 +; CHECK-NEXT: .amdhsa_float_denorm_mode_32 0 +; CHECK-NEXT: .amdhsa_float_denorm_mode_16_64 3 +; CHECK-NEXT: .amdhsa_fp16_overflow 0 +; CHECK-NEXT: ; FLAT_SCRATCH_IS_NV 0 +; CHECK-NEXT: .amdhsa_memory_ordered 1 +; CHECK-NEXT: .amdhsa_forward_progress 1 +; CHECK-NEXT: .amdhsa_round_robin_scheduling 0 +; CHECK-NEXT: .amdhsa_enable_private_segment 0 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 +; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_info 0 +; CHECK-NEXT: .amdhsa_system_vgpr_workitem_id 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0 +; CHECK-NEXT: .amdhsa_exception_fp_denorm_src 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_div_zero 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_overflow 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_underflow 0 +; CHECK-NEXT: .amdhsa_exception_fp_ieee_inexact 0 +; CHECK-NEXT: .amdhsa_exception_int_div_zero 0 +; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 +; CHECK-NEXT: .amdhsa_user_sgpr_queue_ptr 0 +; CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 +; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 0 +; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 0 +; CHECK-NEXT: .amdhsa_uses_cu_stores 0 +; CHECK-NEXT: .amdhsa_wavefront_size32 1 +; CHECK-NEXT: .amdhsa_uses_dynamic_stack 0 +; CHECK-NEXT: .end_amdhsa_kernel +.amdhsa_kernel kernel + .amdhsa_group_segment_fixed_size 393216 + .amdhsa_next_free_vgpr 32 + .amdhsa_next_free_sgpr 32 + .amdhsa_named_barrier_count 7 + .amdhsa_uses_cu_stores 0 + .amdhsa_inst_pref_size 63 +.end_amdhsa_kernel diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/undefined-in-it.s b/llvm/test/tools/llvm-objdump/ELF/ARM/undefined-in-it.s new file mode 100644 index 0000000..c5dc5cb --- /dev/null +++ b/llvm/test/tools/llvm-objdump/ELF/ARM/undefined-in-it.s @@ -0,0 +1,45 @@ +@RUN: llvm-mc -triple arm-none-eabi -mcpu=cortex-m33 -filetype=obj %s | llvm-objdump -d --mcpu=cortex-m3 - | FileCheck %s + +@ Check that instructions that are disassembled as <undefined> within an IT +@ block advance the IT state. This prevents the IT state spilling over into +@ the next instruction. + +@ The vldmiaeq instruction is disassembled as <undefined> with +@ -mcpu=cortex-m3 as this does not have a fpu. +.text +.fpu fp-armv8 +.thumb + ite eq + vldmiaeq r0!, {s16-s31} + addne r0, r0, r0 + add r1, r1, r1 + + itet eq + vldmiaeq r0!, {s16-s31} + vldmiane r0!, {s16-s31} + vldmiaeq r0!, {s16-s31} + add r0, r0, r0 + add r1, r1, r1 + add r2, r2, r2 + + it eq + vldmiaeq r0!, {s16-s31} + + it ne + addne r0, r0, r0 + +@ CHECK: 0: bf0c ite eq +@ CHECK-NEXT: 2: ecb0 8a10 <unknown> +@ CHECK-NEXT: 6: 1800 addne r0, r0, r0 +@ CHECK-NEXT: 8: 4409 add r1, r1 +@ CHECK-NEXT: a: bf0a itet eq +@ CHECK-NEXT: c: ecb0 8a10 <unknown> +@ CHECK-NEXT: 10: ecb0 8a10 <unknown> +@ CHECK-NEXT: 14: ecb0 8a10 <unknown> +@ CHECK-NEXT: 18: 4400 add r0, r0 +@ CHECK-NEXT: 1a: 4409 add r1, r1 +@ CHECK-NEXT: 1c: 4412 add r2, r2 +@ CHECK-NEXT: 1e: bf08 it eq +@ CHECK-NEXT: 20: ecb0 8a10 <unknown> +@ CHECK-NEXT: 24: bf18 it ne +@ CHECK-NEXT: 26: 1800 addne r0, r0, r0 diff --git a/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin-reduced.html b/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin-reduced.html new file mode 100644 index 0000000..c419744 --- /dev/null +++ b/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin-reduced.html @@ -0,0 +1,124 @@ + <html> + <head> + <style> + table, th, td { + border: 1px solid black; + } + table.center { + margin-left: auto; + margin-right: auto; + } + </style> + </head> + <body> + <table> + <caption><b>Location Bugs found by the Debugify</b></caption> + <tr> + <th>File</th> + <th>LLVM Pass Name</th> + <th>LLVM IR Instruction</th> + <th>Function Name</th> + <th>Basic Block Name</th> + <th>Action</th> + <th>Origin</th> + </tr> + </tr> + <tr> + <td>test.ll</td> + <td>LoopVectorizePass</td> + <td>add</td> + <td>fn</td> + <td>no-name</td> + <td>not-generate</td> + <td><details><summary>View Origin StackTrace</summary><pre>Stack Trace 0: + #0 0x00005895d035c935 llvm::DbgLocOrigin::DbgLocOrigin(bool) /tmp/llvm-project/llvm/lib/IR/DebugLoc.cpp:22:9 + #1 0x00005895d03af013 llvm::DILocAndCoverageTracking::DILocAndCoverageTracking() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:90:11 + #2 0x00005895d03af013 llvm::DebugLoc::DebugLoc() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:133:5 + #3 0x00005895d03af013 llvm::Instruction::Instruction(llvm::Type*, unsigned int, llvm::User::AllocInfo, llvm::InsertPosition) /tmp/llvm-project/llvm/lib/IR/Instruction.cpp:37:14 + #4 0x00005895d06862b5 llvm::PHINode::PHINode(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:0:9 + #5 0x00005895d06862b5 llvm::PHINode::Create(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:2651:9 + #6 0x00005895d06862b5 llvm::InstCombinerImpl::foldPHIArgGEPIntoPHI(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:617:9 + #7 0x00005895d0688fe0 llvm::InstCombinerImpl::visitPHINode(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:1456:22 + #8 0x00005895d05cd21f llvm::InstCombinerImpl::run() /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5327:22 + #9 0x00005895d05d067e combineInstructionsOverFunction(llvm::Function&, llvm::InstructionWorklist&, llvm::AAResults*, llvm::AssumptionCache&, llvm::TargetLibraryInfo&, llvm::TargetTransformInfo&, llvm::DominatorTree&, llvm::OptimizationRemarkEmitter&, llvm::BlockFrequencyInfo*, llvm::BranchProbabilityInfo*, llvm::ProfileSummaryInfo*, llvm::InstCombineOptions const&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5643:31 +#10 0x00005895d05cf9a9 llvm::InstCombinePass::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5706:8 +#11 0x00005895d107d07d llvm::detail::PassModel>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#12 0x00005895d04204a7 llvm::PassManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerImpl.h:85:8 +#13 0x00005895ce4cb09d llvm::detail::PassModel>, llvm::AnalysisManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#14 0x00005895cfae2865 llvm::CGSCCToFunctionPassAdaptor::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38 +#15 0x00005895ce4cad5d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#16 0x00005895cfade813 llvm::PassManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:93:12 +#17 0x00005895d1e3968d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>, llvm::AnalysisManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#18 0x00005895cfae1224 llvm::DevirtSCCRepeatedPass::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38 +#19 0x00005895d1e5067d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5</pre></details></td> + </tr> + <tr> +</table> +<br> +<table> + <caption><b>Summary of Location Bugs</b></caption> + <tr> + <th>LLVM Pass Name</th> + <th>Number of bugs</th> + </tr> + <tr> + <td>LoopVectorizePass</td> + <td>2</td> + </tr> + <tr> +</table> +<br> +<br> +<table> + <caption><b>SP Bugs found by the Debugify</b></caption> + <tr> + <th>File</th> + <th>LLVM Pass Name</th> + <th>Function Name</th> + <th>Action</th> + </tr> +<tr> + <td colspan='4'> No bugs found </td> + </tr> + </table> +<br> +<table> + <caption><b>Summary of SP Bugs</b></caption> + <tr> + <th>LLVM Pass Name</th> + <th>Number of bugs</th> + </tr> + <tr> +<tr> + <td colspan='2'> No bugs found </td> + </tr> + </table> +<br> +<br> +<table> + <caption><b>Variable Location Bugs found by the Debugify</b></caption> + <tr> + <th>File</th> + <th>LLVM Pass Name</th> + <th>Variable</th> + <th>Function</th> + <th>Action</th> + </tr> +<tr> + <td colspan='4'> No bugs found </td> + </tr> + </table> +<br> +<table> + <caption><b>Summary of Variable Location Bugs</b></caption> + <tr> + <th>LLVM Pass Name</th> + <th>Number of bugs</th> + </tr> + <tr> +<tr> + <td colspan='2'> No bugs found </td> + </tr> + </table> +</body> + </html>
\ No newline at end of file diff --git a/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin.html b/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin.html index ed08c85..4de4642 100644 --- a/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin.html +++ b/llvm/test/tools/llvm-original-di-preservation/Inputs/expected-origin.html @@ -53,6 +53,37 @@ #19 0x00005895d1e5067d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5</pre></details></td> </tr> <tr> + </tr> + <tr> + <td>test2.ll</td> + <td>LoopVectorizePass</td> + <td>add</td> + <td>foo</td> + <td>no-name</td> + <td>not-generate</td> + <td><details><summary>View Origin StackTrace</summary><pre>Stack Trace 0: + #0 0x000046afd035c935 llvm::DbgLocOrigin::DbgLocOrigin(bool) /tmp/llvm-project/llvm/lib/IR/DebugLoc.cpp:22:9 + #1 0x000046afd03af013 llvm::DILocAndCoverageTracking::DILocAndCoverageTracking() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:90:11 + #2 0x000046afd03af013 llvm::DebugLoc::DebugLoc() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:133:5 + #3 0x000046afd03af013 llvm::Instruction::Instruction(llvm::Type*, unsigned int, llvm::User::AllocInfo, llvm::InsertPosition) /tmp/llvm-project/llvm/lib/IR/Instruction.cpp:37:14 + #4 0x000046afd06862b5 llvm::PHINode::PHINode(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:0:9 + #5 0x000046afd06862b5 llvm::PHINode::Create(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:2651:9 + #6 0x000046afd06862b5 llvm::InstCombinerImpl::foldPHIArgGEPIntoPHI(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:617:9 + #7 0x000046afd0688fe0 llvm::InstCombinerImpl::visitPHINode(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:1456:22 + #8 0x000046afd05cd21f llvm::InstCombinerImpl::run() /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5327:22 + #9 0x000046afd05d067e combineInstructionsOverFunction(llvm::Function&, llvm::InstructionWorklist&, llvm::AAResults*, llvm::AssumptionCache&, llvm::TargetLibraryInfo&, llvm::TargetTransformInfo&, llvm::DominatorTree&, llvm::OptimizationRemarkEmitter&, llvm::BlockFrequencyInfo*, llvm::BranchProbabilityInfo*, llvm::ProfileSummaryInfo*, llvm::InstCombineOptions const&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5643:31 +#10 0x000046afd05cf9a9 llvm::InstCombinePass::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5706:8 +#11 0x000046afd107d07d llvm::detail::PassModel>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#12 0x000046afd04204a7 llvm::PassManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerImpl.h:85:8 +#13 0x000046afce4cb09d llvm::detail::PassModel>, llvm::AnalysisManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#14 0x000046afcfae2865 llvm::CGSCCToFunctionPassAdaptor::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38 +#15 0x000046afce4cad5d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#16 0x000046afcfade813 llvm::PassManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:93:12 +#17 0x000046afd1e3968d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>, llvm::AnalysisManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5 +#18 0x000046afcfae1224 llvm::DevirtSCCRepeatedPass::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38 +#19 0x000046afd1e5067d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5</pre></details></td> + </tr> + <tr> </table> <br> <table> @@ -63,7 +94,7 @@ </tr> <tr> <td>LoopVectorizePass</td> - <td>1</td> + <td>2</td> </tr> <tr> </table> diff --git a/llvm/test/tools/llvm-original-di-preservation/Inputs/origin.json b/llvm/test/tools/llvm-original-di-preservation/Inputs/origin.json index ab59bc2..5a06a1f 100644 --- a/llvm/test/tools/llvm-original-di-preservation/Inputs/origin.json +++ b/llvm/test/tools/llvm-original-di-preservation/Inputs/origin.json @@ -1 +1,2 @@ {"file":"test.ll", "pass":"LoopVectorizePass", "bugs": [[{"action":"not-generate","bb-name":"no-name","fn-name":"fn","instr":"add","metadata":"DILocation", "origin": "Stack Trace 0:\n #0 0x00005895d035c935 llvm::DbgLocOrigin::DbgLocOrigin(bool) /tmp/llvm-project/llvm/lib/IR/DebugLoc.cpp:22:9\n #1 0x00005895d03af013 llvm::DILocAndCoverageTracking::DILocAndCoverageTracking() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:90:11\n #2 0x00005895d03af013 llvm::DebugLoc::DebugLoc() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:133:5\n #3 0x00005895d03af013 llvm::Instruction::Instruction(llvm::Type*, unsigned int, llvm::User::AllocInfo, llvm::InsertPosition) /tmp/llvm-project/llvm/lib/IR/Instruction.cpp:37:14\n #4 0x00005895d06862b5 llvm::PHINode::PHINode(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:0:9\n #5 0x00005895d06862b5 llvm::PHINode::Create(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:2651:9\n #6 0x00005895d06862b5 llvm::InstCombinerImpl::foldPHIArgGEPIntoPHI(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:617:9\n #7 0x00005895d0688fe0 llvm::InstCombinerImpl::visitPHINode(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:1456:22\n #8 0x00005895d05cd21f llvm::InstCombinerImpl::run() /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5327:22\n #9 0x00005895d05d067e combineInstructionsOverFunction(llvm::Function&, llvm::InstructionWorklist&, llvm::AAResults*, llvm::AssumptionCache&, llvm::TargetLibraryInfo&, llvm::TargetTransformInfo&, llvm::DominatorTree&, llvm::OptimizationRemarkEmitter&, llvm::BlockFrequencyInfo*, llvm::BranchProbabilityInfo*, llvm::ProfileSummaryInfo*, llvm::InstCombineOptions const&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5643:31\n#10 0x00005895d05cf9a9 llvm::InstCombinePass::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5706:8\n#11 0x00005895d107d07d llvm::detail::PassModel>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#12 0x00005895d04204a7 llvm::PassManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerImpl.h:85:8\n#13 0x00005895ce4cb09d llvm::detail::PassModel>, llvm::AnalysisManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#14 0x00005895cfae2865 llvm::CGSCCToFunctionPassAdaptor::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38\n#15 0x00005895ce4cad5d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#16 0x00005895cfade813 llvm::PassManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:93:12\n#17 0x00005895d1e3968d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>, llvm::AnalysisManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#18 0x00005895cfae1224 llvm::DevirtSCCRepeatedPass::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38\n#19 0x00005895d1e5067d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5"}]]} +{"file":"test2.ll", "pass":"LoopVectorizePass", "bugs": [[{"action":"not-generate","bb-name":"no-name","fn-name":"foo","instr":"add","metadata":"DILocation", "origin": "Stack Trace 0:\n #0 0x000046afd035c935 llvm::DbgLocOrigin::DbgLocOrigin(bool) /tmp/llvm-project/llvm/lib/IR/DebugLoc.cpp:22:9\n #1 0x000046afd03af013 llvm::DILocAndCoverageTracking::DILocAndCoverageTracking() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:90:11\n #2 0x000046afd03af013 llvm::DebugLoc::DebugLoc() /tmp/llvm-project/llvm/include/llvm/IR/DebugLoc.h:133:5\n #3 0x000046afd03af013 llvm::Instruction::Instruction(llvm::Type*, unsigned int, llvm::User::AllocInfo, llvm::InsertPosition) /tmp/llvm-project/llvm/lib/IR/Instruction.cpp:37:14\n #4 0x000046afd06862b5 llvm::PHINode::PHINode(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:0:9\n #5 0x000046afd06862b5 llvm::PHINode::Create(llvm::Type*, unsigned int, llvm::Twine const&, llvm::InsertPosition) /tmp/llvm-project/llvm/include/llvm/IR/Instructions.h:2651:9\n #6 0x000046afd06862b5 llvm::InstCombinerImpl::foldPHIArgGEPIntoPHI(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:617:9\n #7 0x000046afd0688fe0 llvm::InstCombinerImpl::visitPHINode(llvm::PHINode&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp:1456:22\n #8 0x000046afd05cd21f llvm::InstCombinerImpl::run() /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5327:22\n #9 0x000046afd05d067e combineInstructionsOverFunction(llvm::Function&, llvm::InstructionWorklist&, llvm::AAResults*, llvm::AssumptionCache&, llvm::TargetLibraryInfo&, llvm::TargetTransformInfo&, llvm::DominatorTree&, llvm::OptimizationRemarkEmitter&, llvm::BlockFrequencyInfo*, llvm::BranchProbabilityInfo*, llvm::ProfileSummaryInfo*, llvm::InstCombineOptions const&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5643:31\n#10 0x000046afd05cf9a9 llvm::InstCombinePass::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:5706:8\n#11 0x000046afd107d07d llvm::detail::PassModel>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#12 0x000046afd04204a7 llvm::PassManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerImpl.h:85:8\n#13 0x000046afce4cb09d llvm::detail::PassModel>, llvm::AnalysisManager>::run(llvm::Function&, llvm::AnalysisManager&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#14 0x000046afcfae2865 llvm::CGSCCToFunctionPassAdaptor::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38\n#15 0x000046afce4cad5d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#16 0x000046afcfade813 llvm::PassManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:93:12\n#17 0x000046afd1e3968d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>, llvm::AnalysisManager, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5\n#18 0x000046afcfae1224 llvm::DevirtSCCRepeatedPass::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/lib/Analysis/CGSCCPassManager.cpp:0:38\n#19 0x000046afd1e5067d llvm::detail::PassModel, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&>::run(llvm::LazyCallGraph::SCC&, llvm::AnalysisManager&, llvm::LazyCallGraph&, llvm::CGSCCUpdateResult&) /tmp/llvm-project/llvm/include/llvm/IR/PassManagerInternal.h:91:5"}]]} diff --git a/llvm/test/tools/llvm-original-di-preservation/basic.test b/llvm/test/tools/llvm-original-di-preservation/basic.test index df43fbb..5bd7e13 100644 --- a/llvm/test/tools/llvm-original-di-preservation/basic.test +++ b/llvm/test/tools/llvm-original-di-preservation/basic.test @@ -15,3 +15,6 @@ REDUCE-NOT: Skipped lines: RUN: %llvm-original-di-preservation %p/Inputs/origin.json --report-html-file %t4.html | FileCheck %s RUN: diff -w %p/Inputs/expected-origin.html %t4.html + +RUN: %llvm-original-di-preservation --reduce %p/Inputs/origin.json --report-html-file %t5.html | FileCheck %s +RUN: diff -w %p/Inputs/expected-origin-reduced.html %t5.html diff --git a/llvm/test/tools/llvm-profdata/memprof-yaml.test b/llvm/test/tools/llvm-profdata/memprof-yaml.test index 2e52b796..6fbfbdb 100644 --- a/llvm/test/tools/llvm-profdata/memprof-yaml.test +++ b/llvm/test/tools/llvm-profdata/memprof-yaml.test @@ -13,11 +13,28 @@ ; RUN: llvm-profdata show --memory %t/memprof-out-v3.indexed > %t/memprof-out-v3.yaml ; RUN: diff -b %t/memprof-out-v3.yaml %t/memprof-in-v3.yaml +; Make sure we can ingest a YAML profile containing AllocSites only. +; That is, CallSites are missing. +; RUN: llvm-profdata merge --memprof-version=4 %t/memprof-in-alloc-sites-only.yaml -o %t/memprof-out-alloc-sites-only.indexed +; RUN: llvm-profdata show --memory %t/memprof-out-alloc-sites-only.indexed > %t/memprof-out-alloc-sites-only.yaml +; RUN: diff -b %t/memprof-out-alloc-sites-only.yaml %t/memprof-in-alloc-sites-only.yaml + +; Make sure we can ingest a YAML profile containing CallSites only. +; That is, AllocSites are missing. +; RUN: llvm-profdata merge --memprof-version=4 %t/memprof-in-call-sites-only.yaml -o %t/memprof-out-call-sites-only.indexed +; RUN: llvm-profdata show --memory %t/memprof-out-call-sites-only.indexed > %t/memprof-out-call-sites-only.yaml +; RUN: diff -b %t/memprof-out-call-sites-only.yaml %t/memprof-in-call-sites-only.yaml + ; memprof-in-no-dap.yaml has empty data access profiles. ; RUN: llvm-profdata merge --memprof-version=4 %t/memprof-in-no-dap.yaml -o %t/memprof-out.indexed ; RUN: llvm-profdata show --memory %t/memprof-out.indexed > %t/memprof-out-no-dap.yaml ; RUN: diff -b %t/memprof-in-no-dap.yaml %t/memprof-out-no-dap.yaml +; memprof-in-no-heap.yaml has empty heap access profiles. +; RUN: llvm-profdata merge --memprof-version=4 %t/memprof-in-no-heap.yaml -o %t/memprof-out-no-heap.indexed +; RUN: llvm-profdata show --memory %t/memprof-out-no-heap.indexed > %t/memprof-out-no-heap.yaml +; RUN: diff -b %t/memprof-in-no-heap.yaml %t/memprof-out-no-heap.yaml + ;--- memprof-in.yaml --- # MemProfSummary: @@ -112,6 +129,58 @@ HeapProfileRecords: - { Function: 0x7777777777777777, LineOffset: 77, Column: 70, IsInlineFrame: true } - { Function: 0x8888888888888888, LineOffset: 88, Column: 80, IsInlineFrame: false } ... +;--- memprof-in-alloc-sites-only.yaml +--- +# MemProfSummary: +# Total contexts: 2 +# Total cold contexts: 0 +# Total hot contexts: 0 +# Maximum cold context total size: 0 +# Maximum warm context total size: 666 +# Maximum hot context total size: 0 +--- +HeapProfileRecords: + - GUID: 0xdeadbeef12345678 + AllocSites: + - Callstack: + - { Function: 0x1111111111111111, LineOffset: 11, Column: 10, IsInlineFrame: true } + - { Function: 0x2222222222222222, LineOffset: 22, Column: 20, IsInlineFrame: false } + MemInfoBlock: + AllocCount: 111 + TotalSize: 222 + TotalLifetime: 333 + TotalLifetimeAccessDensity: 444 + - Callstack: + - { Function: 0x3333333333333333, LineOffset: 33, Column: 30, IsInlineFrame: false } + - { Function: 0x4444444444444444, LineOffset: 44, Column: 40, IsInlineFrame: true } + MemInfoBlock: + AllocCount: 555 + TotalSize: 666 + TotalLifetime: 777 + TotalLifetimeAccessDensity: 888 +... +;--- memprof-in-call-sites-only.yaml +--- +# MemProfSummary: +# Total contexts: 0 +# Total cold contexts: 0 +# Total hot contexts: 0 +# Maximum cold context total size: 0 +# Maximum warm context total size: 0 +# Maximum hot context total size: 0 +--- +HeapProfileRecords: + - GUID: 0xdeadbeef12345678 + CallSites: + - Frames: + - { Function: 0x5555555555555555, LineOffset: 55, Column: 50, IsInlineFrame: true } + - { Function: 0x6666666666666666, LineOffset: 66, Column: 60, IsInlineFrame: false } + CalleeGuids: [ 0x100, 0x200 ] + - Frames: + - { Function: 0x7777777777777777, LineOffset: 77, Column: 70, IsInlineFrame: true } + - { Function: 0x8888888888888888, LineOffset: 88, Column: 80, IsInlineFrame: false } + CalleeGuids: [ 0x300 ] +... ;--- memprof-in-no-dap.yaml --- # MemProfSummary: @@ -151,3 +220,32 @@ HeapProfileRecords: - { Function: 0x8888888888888888, LineOffset: 88, Column: 80, IsInlineFrame: false } CalleeGuids: [ 0x300 ] ... +;--- memprof-in-no-heap.yaml +--- +# MemProfSummary: +# Total contexts: 0 +# Total cold contexts: 0 +# Total hot contexts: 0 +# Maximum cold context total size: 0 +# Maximum warm context total size: 0 +# Maximum hot context total size: 0 +--- +DataAccessProfiles: + SampledRecords: + - Symbol: abcde + AccessCount: 100 + Locations: + - FileName: file2.h + Line: 123 + - FileName: file3.cpp + Line: 456 + - Hash: 101010 + AccessCount: 200 + Locations: + - FileName: file.cpp + Line: 233 + KnownColdSymbols: + - foo + - bar + KnownColdStrHashes: [ 999, 1001 ] +... diff --git a/llvm/test/tools/llvm-profdata/merge-traces.proftext b/llvm/test/tools/llvm-profdata/merge-traces.proftext index bcf29ba..3512f33 100644 --- a/llvm/test/tools/llvm-profdata/merge-traces.proftext +++ b/llvm/test/tools/llvm-profdata/merge-traces.proftext @@ -1,24 +1,36 @@ -# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s -o %t.profdata -# RUN: llvm-profdata show --temporal-profile-traces %t.profdata | FileCheck %s --check-prefixes=SAMPLE1,SEEN1 -# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %t.profdata -o %t.profdata -# RUN: llvm-profdata show --temporal-profile-traces %t.profdata | FileCheck %s --check-prefixes=SAMPLE2,SEEN2 -# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %t.profdata -o %t.profdata -# RUN: llvm-profdata show --temporal-profile-traces %t.profdata | FileCheck %s --check-prefixes=SAMPLE2,SEEN3 -# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %t.profdata -o %t.profdata -# RUN: llvm-profdata show --temporal-profile-traces %t.profdata | FileCheck %s --check-prefixes=SAMPLE2,SEEN4 - -# SEEN1: Temporal Profile Traces (samples=1 seen=1): -# SEEN2: Temporal Profile Traces (samples=2 seen=2): -# SEEN3: Temporal Profile Traces (samples=2 seen=3): -# SEEN4: Temporal Profile Traces (samples=2 seen=4): -# SAMPLE1: Temporal Profile Trace 0 (weight=1 count=3): -# SAMPLE1: a -# SAMPLE1: b -# SAMPLE1: c -# SAMPLE2: Temporal Profile Trace 1 (weight=1 count=3): -# SAMPLE2: a -# SAMPLE2: b -# SAMPLE2: c +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s --text | FileCheck %s --check-prefixes=CHECK,SEEN1,SAMPLE1 + +# Merge %s twice so it has two traces +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %s --text | FileCheck %s --check-prefixes=CHECK,SEEN2,SAMPLE2 +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %s -o %t-2.profdata + +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %s %s --text | FileCheck %s --check-prefixes=CHECK,SEEN3,SAMPLE2 +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %t-2.profdata %s --text | FileCheck %s --check-prefixes=CHECK,SEEN3,SAMPLE2 +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %t-2.profdata --text | FileCheck %s --check-prefixes=CHECK,SEEN3,SAMPLE2 + +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %s %s %s --text | FileCheck %s --check-prefixes=CHECK,SEEN4,SAMPLE2 +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %t-2.profdata %s %s --text | FileCheck %s --check-prefixes=CHECK,SEEN4,SAMPLE2 +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %t-2.profdata %t-2.profdata --text | FileCheck %s --check-prefixes=CHECK,SEEN4,SAMPLE2 + +# Test that we can increase the reservoir size, even if inputs are sampled +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=2 %s %s %s %s -o %t-4.profdata +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=4 %t-4.profdata %t-4.profdata --text | FileCheck %s --check-prefixes=CHECK,SEEN8,SAMPLE4 + +# Test that decreasing the reservoir size truncates traces +# RUN: llvm-profdata merge --temporal-profile-trace-reservoir-size=1 %t-4.profdata --text | FileCheck %s --check-prefixes=CHECK,SEEN4,SAMPLE1 + +# CHECK: :temporal_prof_traces +# CHECK: # Num Temporal Profile Traces: +# SAMPLE1: 1 +# SAMPLE2: 2 +# SAMPLE4: 4 +# CHECK: # Temporal Profile Trace Stream Size: +# SEEN1: 1 +# SEEN2: 2 +# SEEN3: 3 +# SEEN4: 4 +# SEEN8: 8 +# CHECK: a,b,c, # Header :ir diff --git a/llvm/test/tools/llvm-profdata/overlap.test b/llvm/test/tools/llvm-profdata/overlap.test index 91379d57..6470e3f 100644 --- a/llvm/test/tools/llvm-profdata/overlap.test +++ b/llvm/test/tools/llvm-profdata/overlap.test @@ -9,7 +9,7 @@ MAINFUNC: # of edge counters overlap: 2 MAINFUNC: Edge profile overlap: 100.000% MAINFUNC: Edge profile base count sum: 200000 MAINFUNC: Edge profile test count sum: 20000 -OVERLAP: Profile overlap infomation for base_profile: {{.*}} and test_profile: +OVERLAP: Profile overlap information for base_profile: {{.*}} and test_profile: OVERLAP: Program level: OVERLAP: # of functions overlap: 2 OVERLAP: # of functions mismatch: 1 diff --git a/llvm/test/tools/llvm-profdata/overlap_cs.test b/llvm/test/tools/llvm-profdata/overlap_cs.test index 3f2086a2..ba15418 100644 --- a/llvm/test/tools/llvm-profdata/overlap_cs.test +++ b/llvm/test/tools/llvm-profdata/overlap_cs.test @@ -2,7 +2,7 @@ RUN: llvm-profdata overlap -cs %p/Inputs/overlap_1_cs.proftext %p/Inputs/overlap RUN: llvm-profdata merge %p/Inputs/overlap_1_cs.proftext -o %t_1_cs.profdata RUN: llvm-profdata merge %p/Inputs/overlap_2_cs.proftext -o %t_2_cs.profdata RUN: llvm-profdata overlap -cs %t_1_cs.profdata %t_2_cs.profdata | FileCheck %s -check-prefix=OVERLAP -OVERLAP: Profile overlap infomation for base_profile: {{.*}} and test_profile: +OVERLAP: Profile overlap information for base_profile: {{.*}} and test_profile: OVERLAP: Program level: OVERLAP: # of functions overlap: 1 OVERLAP: Edge profile overlap: 80.000% diff --git a/llvm/test/tools/llvm-profdata/overlap_vp.test b/llvm/test/tools/llvm-profdata/overlap_vp.test index 228b809..4425696 100644 --- a/llvm/test/tools/llvm-profdata/overlap_vp.test +++ b/llvm/test/tools/llvm-profdata/overlap_vp.test @@ -2,7 +2,7 @@ RUN: llvm-profdata overlap %p/Inputs/overlap_1_vp.proftext %p/Inputs/overlap_2_v RUN: llvm-profdata merge %p/Inputs/overlap_1_vp.proftext -o %t_1_vp.profdata RUN: llvm-profdata merge %p/Inputs/overlap_2_vp.proftext -o %t_2_vp.profdata RUN: llvm-profdata overlap %t_1_vp.profdata %t_2_vp.profdata | FileCheck %s -check-prefix=OVERLAP -OVERLAP: Profile overlap infomation for base_profile: {{.*}} and test_profile: +OVERLAP: Profile overlap information for base_profile: {{.*}} and test_profile: OVERLAP: Program level: OVERLAP: # of functions overlap: 1 OVERLAP: Edge profile overlap: 80.000% diff --git a/llvm/test/tools/llvm-profdata/read-traces.proftext b/llvm/test/tools/llvm-profdata/read-traces.proftext index 87f69fe..5e822a9 100644 --- a/llvm/test/tools/llvm-profdata/read-traces.proftext +++ b/llvm/test/tools/llvm-profdata/read-traces.proftext @@ -3,19 +3,16 @@ # RUN: llvm-profdata merge -text %t.2.profdata -o %t.3.proftext # RUN: diff %t.1.proftext %t.3.proftext -# RUN: llvm-profdata show --temporal-profile-traces %t.1.proftext | FileCheck %s +# RUN: llvm-profdata merge -text %s | FileCheck %s -# CHECK: Temporal Profile Traces (samples=3 seen=3): -# CHECK: Temporal Profile Trace 0 (weight=1 count=3): -# CHECK: foo -# CHECK: bar -# CHECK: goo -# CHECK: Temporal Profile Trace 1 (weight=3 count=3): -# CHECK: foo -# CHECK: goo -# CHECK: bar -# CHECK: Temporal Profile Trace 2 (weight=1 count=1): -# CHECK: goo +# CHECK: :temporal_prof_traces +# CHECK: # Num Temporal Profile Traces: +# CHECK-NEXT: 3 +# CHECK: # Temporal Profile Trace Stream Size: +# CHECK-NEXT: 3 +# CHECK-DAG: foo,bar,goo, +# CHECK-DAG: foo,goo,bar, +# CHECK-DAG: goo, # Header :ir diff --git a/llvm/test/tools/llvm-profdata/trace-limit.proftext b/llvm/test/tools/llvm-profdata/trace-limit.proftext index e246ee8..6b4f974 100644 --- a/llvm/test/tools/llvm-profdata/trace-limit.proftext +++ b/llvm/test/tools/llvm-profdata/trace-limit.proftext @@ -11,7 +11,7 @@ # RUN: llvm-profdata merge --temporal-profile-max-trace-length=1000 %s -o %t.profdata # RUN: llvm-profdata show --temporal-profile-traces %t.profdata | FileCheck %s --check-prefixes=CHECK,ALL -# NONE: Temporal Profile Traces (samples=0 +# NONE: Temporal Profile Traces (samples=0 seen=0): # CHECK: Temporal Profile Traces (samples=1 seen=1): # SOME: Trace 0 (weight=1 count=2): # ALL: Trace 0 (weight=1 count=3): diff --git a/llvm/test/tools/llvm-readobj/COFF/Inputs/pseudoreloc.i386.yaml b/llvm/test/tools/llvm-readobj/COFF/Inputs/pseudoreloc.i386.yaml new file mode 100644 index 0000000..9eb56dd --- /dev/null +++ b/llvm/test/tools/llvm-readobj/COFF/Inputs/pseudoreloc.i386.yaml @@ -0,0 +1,123 @@ +--- !COFF +OptionalHeader: + AddressOfEntryPoint: 4096 + ImageBase: 4194304 + SectionAlignment: 4096 + FileAlignment: 512 + MajorOperatingSystemVersion: 6 + MinorOperatingSystemVersion: 0 + MajorImageVersion: 0 + MinorImageVersion: 0 + MajorSubsystemVersion: 6 + MinorSubsystemVersion: 0 + Subsystem: IMAGE_SUBSYSTEM_WINDOWS_CUI + DLLCharacteristics: [ IMAGE_DLL_CHARACTERISTICS_NX_COMPAT, IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE ] + SizeOfStackReserve: 1048576 + SizeOfStackCommit: 4096 + SizeOfHeapReserve: 1048576 + SizeOfHeapCommit: 4096 + ExportTable: + RelativeVirtualAddress: 0 + Size: 0 + ImportTable: + RelativeVirtualAddress: 8288 + Size: 60 + ResourceTable: + RelativeVirtualAddress: 0 + Size: 0 + ExceptionTable: + RelativeVirtualAddress: 0 + Size: 0 + CertificateTable: + RelativeVirtualAddress: 0 + Size: 0 + BaseRelocationTable: + RelativeVirtualAddress: 0 + Size: 0 + Debug: + RelativeVirtualAddress: 0 + Size: 0 + Architecture: + RelativeVirtualAddress: 0 + Size: 0 + GlobalPtr: + RelativeVirtualAddress: 0 + Size: 0 + TlsTable: + RelativeVirtualAddress: 0 + Size: 0 + LoadConfigTable: + RelativeVirtualAddress: 0 + Size: 0 + BoundImport: + RelativeVirtualAddress: 0 + Size: 0 + IAT: + RelativeVirtualAddress: 8368 + Size: 20 + DelayImportDescriptor: + RelativeVirtualAddress: 0 + Size: 0 + ClrRuntimeHeader: + RelativeVirtualAddress: 0 + Size: 0 +header: + Machine: IMAGE_FILE_MACHINE_I386 + Characteristics: [ IMAGE_FILE_RELOCS_STRIPPED, IMAGE_FILE_EXECUTABLE_IMAGE, IMAGE_FILE_32BIT_MACHINE ] +sections: + - Name: .text + Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ] + VirtualAddress: 4096 + VirtualSize: 60 + SectionData: A1003040000FBE008B0D043040000FBE0901C1A1083040000FBE10A1103040000FBE0001D001C8C39090909090909090A1502040002B0508204000C3 + SizeOfRawData: 512 + - Name: .rdata + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ] + VirtualAddress: 8192 + VirtualSize: 254 + SectionData: 3377115566228844000000000000000001000000[[SYMBOL0=B0200000]]0030000020000000[[SYMBOL1=B4200000]]0430000020000000[[SYMBOL2=BC200000]]0830000020000000BC2000000C30000020000000B02000001030000020000000FFFFFFFF00000000FFFFFFFF000000009C2000000000000000000000DC200000B0200000A82000000000000000000000ED200000BC2000000000000000000000000000000000000000000000C4200000CC20000000000000D420000000000000C4200000CC20000000000000D420000000000000000073796D310000000073796D320000000073796D3300006578706F7274312E693338362E646C6C006578706F7274322E693338362E646C6C00 + SizeOfRawData: 512 + - Name: .data + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ] + VirtualAddress: 12288 + VirtualSize: 20 + SectionData: B1204000B6204000BD204000BD204000B2204000 + SizeOfRawData: 512 +symbols: + - Name: _start + Value: 0 + SectionNumber: 1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_FUNCTION + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: _local2a + Value: 4 + SectionNumber: [[SECTION_OF_LOCAL2A=3]] + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: _local3a + Value: 8 + SectionNumber: 3 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: __pei386_runtime_relocator + Value: 48 + SectionNumber: 1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_FUNCTION + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: ___RUNTIME_PSEUDO_RELOC_LIST_END__ + Value: [[END=80]] + SectionNumber: 2 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: ___RUNTIME_PSEUDO_RELOC_LIST__ + Value: [[BEGIN=8]] + SectionNumber: [[SECTION_OF_BEGIN=2]] + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL +... diff --git a/llvm/test/tools/llvm-readobj/COFF/Inputs/pseudoreloc.x86_64.yaml b/llvm/test/tools/llvm-readobj/COFF/Inputs/pseudoreloc.x86_64.yaml new file mode 100644 index 0000000..e31f61c --- /dev/null +++ b/llvm/test/tools/llvm-readobj/COFF/Inputs/pseudoreloc.x86_64.yaml @@ -0,0 +1,123 @@ +--- !COFF +OptionalHeader: + AddressOfEntryPoint: 4096 + ImageBase: 5368709120 + SectionAlignment: 4096 + FileAlignment: 512 + MajorOperatingSystemVersion: 6 + MinorOperatingSystemVersion: 0 + MajorImageVersion: 0 + MinorImageVersion: 0 + MajorSubsystemVersion: 6 + MinorSubsystemVersion: 0 + Subsystem: IMAGE_SUBSYSTEM_WINDOWS_CUI + DLLCharacteristics: [ IMAGE_DLL_CHARACTERISTICS_HIGH_ENTROPY_VA, IMAGE_DLL_CHARACTERISTICS_NX_COMPAT, IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE ] + SizeOfStackReserve: 1048576 + SizeOfStackCommit: 4096 + SizeOfHeapReserve: 1048576 + SizeOfHeapCommit: 4096 + ExportTable: + RelativeVirtualAddress: 0 + Size: 0 + ImportTable: + RelativeVirtualAddress: 8304 + Size: 60 + ResourceTable: + RelativeVirtualAddress: 0 + Size: 0 + ExceptionTable: + RelativeVirtualAddress: 0 + Size: 0 + CertificateTable: + RelativeVirtualAddress: 0 + Size: 0 + BaseRelocationTable: + RelativeVirtualAddress: 0 + Size: 0 + Debug: + RelativeVirtualAddress: 0 + Size: 0 + Architecture: + RelativeVirtualAddress: 0 + Size: 0 + GlobalPtr: + RelativeVirtualAddress: 0 + Size: 0 + TlsTable: + RelativeVirtualAddress: 0 + Size: 0 + LoadConfigTable: + RelativeVirtualAddress: 0 + Size: 0 + BoundImport: + RelativeVirtualAddress: 0 + Size: 0 + IAT: + RelativeVirtualAddress: 8408 + Size: 40 + DelayImportDescriptor: + RelativeVirtualAddress: 0 + Size: 0 + ClrRuntimeHeader: + RelativeVirtualAddress: 0 + Size: 0 +header: + Machine: IMAGE_FILE_MACHINE_AMD64 + Characteristics: [ IMAGE_FILE_RELOCS_STRIPPED, IMAGE_FILE_EXECUTABLE_IMAGE, IMAGE_FILE_LARGE_ADDRESS_AWARE ] +sections: + - Name: .text + Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ] + VirtualAddress: 4096 + VirtualSize: 61 + SectionData: 488B05F91F00000FBE00488B0DF71F00000FBE0901C1488B05F31F00000FBE10488B05F91F00000FBE0001D001C8C3908B051A1000002B05CC0F0000C3 + SizeOfRawData: 512 + - Name: .rdata + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ] + VirtualAddress: 8192 + VirtualSize: 318 + SectionData: 3377115566228844000000000000000001000000[[SYMBOL0=E8200000]]0030000040000000[[SYMBOL1=F0200000]]0830000040000000[[SYMBOL2=D8200000]]1030000040000000D82000001830000040000000E82000002030000040000000FFFFFFFFFFFFFFFF0000000000000000FFFFFFFFFFFFFFFF0000000000000000B0200000000000000000000018210000D8200000C020000000000000000000002B210000E82000000000000000000000000000000000000000000000000000000021000000000000000000000000000008210000000000001021000000000000000000000000000000210000000000000000000000000000082100000000000010210000000000000000000000000000000073796D330000000073796D310000000073796D3200006578706F7274322E7838365F36342E646C6C006578706F7274312E7838365F36342E646C6C00 + SizeOfRawData: 512 + - Name: .data + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ] + VirtualAddress: 12288 + VirtualSize: 40 + SectionData: E920004001000000F220004001000000D920004001000000D920004001000000EA20004001000000 + SizeOfRawData: 512 +symbols: + - Name: start + Value: 0 + SectionNumber: 1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_FUNCTION + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: local2a + Value: 8 + SectionNumber: [[SECTION_OF_LOCAL2A=3]] + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: local3a + Value: 16 + SectionNumber: 3 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: _pei386_runtime_relocator + Value: 48 + SectionNumber: 1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_FUNCTION + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: __RUNTIME_PSEUDO_RELOC_LIST_END__ + Value: [[END=80]] + SectionNumber: 2 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: __RUNTIME_PSEUDO_RELOC_LIST__ + Value: [[BEGIN=8]] + SectionNumber: [[SECTION_OF_BEGIN=2]] + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL +... diff --git a/llvm/test/tools/llvm-readobj/COFF/pseudoreloc.test b/llvm/test/tools/llvm-readobj/COFF/pseudoreloc.test new file mode 100644 index 0000000..1c5c3cc --- /dev/null +++ b/llvm/test/tools/llvm-readobj/COFF/pseudoreloc.test @@ -0,0 +1,274 @@ +DEFINE: %{local1a_386} = 0x3000 +DEFINE: %{sym1_386} = 0x20B0 +DEFINE: %{sym3_386} = 0x20BC +DEFINE: %{local1a_x64} = 0x3000 +DEFINE: %{sym1_x64} = 0x20E8 +DEFINE: %{sym3_x64} = 0x20D8 +DEFINE: %{relocbegin} = 8 +DEFINE: %{relocend} = 80 +DEFINE: %{rdatasize} = 254 + +RUN: yaml2obj -o %t.exe-x86_64 %p/Inputs/pseudoreloc.x86_64.yaml +RUN: llvm-readobj %t.exe-x86_64 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=CHECK,CHECK-X64 --match-full-lines --implicit-check-not=warning \ +RUN: -D#WORD=8 -D#SYM1=%{sym1_x64} -D#SYM3=%{sym3_x64} -D#LOCAL1A=%{local1a_x64} -DPREFIX= + +RUN: yaml2obj -o %t.exe-i386 %p/Inputs/pseudoreloc.i386.yaml +RUN: llvm-readobj %t.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=CHECK,CHECK-386 --match-full-lines --implicit-check-not=warning \ +RUN: -D#WORD=4 -D#SYM1=%{sym1_386} -D#SYM3=%{sym3_386} -D#LOCAL1A=%{local1a_386} -DPREFIX=_ + +CHECK-X64: Format: COFF-x86-64 +CHECK-X64-NEXT: Arch: x86_64 +CHECK-386: Format: COFF-i386 +CHECK-386-NEXT: Arch: i386 +CHECK-NEXT: AddressSize: [[#%u,BW:mul(WORD,8)]]bit +CHECK-NEXT: PseudoReloc [ +CHECK-NEXT: Entry { +CHECK-NEXT: Symbol: 0x[[#%X,SYM1]] +CHECK-NEXT: SymbolName: sym1 +CHECK-NEXT: Target: 0x[[#%X,LOCAL1A]] +CHECK-NEXT: TargetSymbol: .data+0x0 +CHECK-NEXT: BitWidth: [[#BW]] +CHECK-NEXT: } +CHECK-NEXT: Entry { +CHECK-NEXT: Symbol: 0x[[#%X,SYM1+mul(1,WORD)]] +CHECK-NEXT: SymbolName: sym2 +CHECK-NEXT: Target: 0x[[#%X,LOCAL1A+mul(1,WORD)]] +CHECK-NEXT: TargetSymbol: [[PREFIX]]local2a +CHECK-NEXT: BitWidth: [[#BW]] +CHECK-NEXT: } +CHECK-NEXT: Entry { +CHECK-NEXT: Symbol: 0x[[#%X,SYM3]] +CHECK-NEXT: SymbolName: sym3 +CHECK-NEXT: Target: 0x[[#%X,LOCAL1A+mul(2,WORD)]] +CHECK-NEXT: TargetSymbol: [[PREFIX]]local3a +CHECK-NEXT: BitWidth: [[#BW]] +CHECK-NEXT: } +CHECK-NEXT: Entry { +CHECK-NEXT: Symbol: 0x[[#%X,SYM3]] +CHECK-NEXT: SymbolName: sym3 +CHECK-NEXT: Target: 0x[[#%X,LOCAL1A+mul(3,WORD)]] +CHECK-NEXT: TargetSymbol: [[PREFIX]]local3a+0x[[#%X,mul(1,WORD)]] +CHECK-NEXT: BitWidth: [[#BW]] +CHECK-NEXT: } +CHECK-NEXT: Entry { +CHECK-NEXT: Symbol: 0x[[#%X,SYM1]] +CHECK-NEXT: SymbolName: sym1 +CHECK-NEXT: Target: 0x[[#%X,LOCAL1A+mul(4,WORD)]] +CHECK-NEXT: TargetSymbol: [[PREFIX]]local3a+0x[[#%X,mul(2,WORD)]] +CHECK-NEXT: BitWidth: [[#BW]] +CHECK-NEXT: } +CHECK-NEXT: ] + +; Test that llvm-readobj warns about missing imported symbol names. +RUN: yaml2obj -o %t.corrupted-iat.exe-i386 %p/Inputs/pseudoreloc.i386.yaml \ +RUN: -DSYMBOL0=30000000 -DSYMBOL1=B2200000 -DSYMBOL2=00FFFF00 +RUN: llvm-readobj %t.corrupted-iat.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefix=INVALIDSYMBOL --match-full-lines -D#LOCAL1A=%{local1a_386} --implicit-check-not=warning + +INVALIDSYMBOL: Symbol: 0x[[#%X,ADDR:0x0030]] +INVALIDSYMBOL-NEXT: {{.*}}warning: {{.*}}: the address referenced by pseudo-relocation is not a valid import entry: 0x[[#%x,ADDR]] +INVALIDSYMBOL-NEXT: SymbolName: (missing) +INVALIDSYMBOL-NEXT: Target: 0x[[#%X,LOCAL1A]] +INVALIDSYMBOL: Symbol: 0x[[#%X,ADDR:0x20B2]] +INVALIDSYMBOL-NEXT: {{.*}}warning: {{.*}}: the address referenced by pseudo-relocation is not a valid import entry: 0x[[#%x,ADDR]] +INVALIDSYMBOL-NEXT: SymbolName: (missing) +INVALIDSYMBOL-NEXT: Target: 0x[[#%X,LOCAL1A+4]] +INVALIDSYMBOL: Symbol: 0x[[#%X,ADDR:0xFFFF00]] +INVALIDSYMBOL-NEXT: {{.*}}warning: {{.*}}: the address referenced by pseudo-relocation is not a valid import entry: 0x[[#%x,ADDR]] +INVALIDSYMBOL-NEXT: SymbolName: (missing) +INVALIDSYMBOL-NEXT: Target: 0x[[#%X,LOCAL1A+8]] + +; Assume the position of the section and the relocation list for further tests. +RUN: FileCheck --input-file=%p/Inputs/pseudoreloc.i386.yaml %s --check-prefix=RELOCPOS --match-full-lines \ +RUN: -D#RDATASIZE=%{rdatasize} -DTHEBEGIN=%{relocbegin} -DTHEEND=%{relocend} + +RELOCPOS: sections: +RELOCPOS-NOT: - Name: +RELOCPOS: - Name: .text +RELOCPOS-NOT: - Name: +RELOCPOS: - Name: .rdata +RELOCPOS-NEXT: Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ] +RELOCPOS-NEXT: VirtualAddress: 8192 +RELOCPOS-NEXT: VirtualSize: [[#%d,RDATASIZE]] +RELOCPOS: - Name: .data +RELOCPOS-NEXT: Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ] +RELOCPOS-NEXT: VirtualAddress: 12288 +RELOCPOS: - Name: ___RUNTIME_PSEUDO_RELOC_LIST_END__ +RELOCPOS-NEXT: Value: [{{\[}}END=[[THEEND]]{{]}}] +RELOCPOS: - Name: ___RUNTIME_PSEUDO_RELOC_LIST__ +RELOCPOS-NEXT: Value: [{{\[}}BEGIN=[[THEBEGIN]]{{]}}] +RELOCPOS-NEXT: SectionNumber: {{\[\[SECTION_OF_BEGIN=2\]\]}} + +; Test that llvm-readobj warns if a symbol belongs to a nonexistent section. +RUN: yaml2obj -o %t.nosection.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DSECTION_OF_LOCAL2A=999 +RUN: llvm-readobj %t.nosection.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=WARN-NOSECTION --match-full-lines + +WARN-NOSECTION: {{.*}} warning:{{.*}}: section index out of bounds + +; Test that llvm-readobj shows an empty list if the relocation list has no contents. +RUN: yaml2obj -o %t.empty-list.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DEND=20 +RUN: llvm-readobj %t.empty-list.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefix=EMPTY --match-full-lines --implicit-check-not=warning + +; Test that llvm-readobj shows an empty list if the relocation list has no header. +RUN: yaml2obj -o %t.no-header.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DEND=%{relocbegin} +RUN: llvm-readobj %t.no-header.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefix=EMPTY --match-full-lines --implicit-check-not=warning + +; Test that llvm-readobj shows an empty list if the image is stripped. +RUN: llvm-readobj --coff-pseudoreloc %p/Inputs/imports.exe.coff-i386 2>&1 | \ +RUN: FileCheck %s --check-prefix=EMPTY --match-full-lines --implicit-check-not=warning + +; Test that llvm-readobj warns if the marker symbol of the relocation list is absent from the symbol table. +RUN: sed -e 's/__RUNTIME//' %p/Inputs/pseudoreloc.i386.yaml | \ +RUN: yaml2obj -o %t.nosymbol.exe-i386 +RUN: llvm-readobj %t.nosymbol.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=EMPTY,WARN-MISSINGMARKER --match-full-lines + +; Test that llvm-readobj shows an empty list if a .obj is specified. +RUN: llvm-readobj --coff-pseudoreloc %p/Inputs/trivial.obj.coff-i386 2>&1 | \ +RUN: FileCheck %s --check-prefix=EMPTY --match-full-lines --implicit-check-not=warning + +; Test that llvm-readobj warns if the header of the relocation list is broken. +RUN: yaml2obj -o %t.broken-header.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DBEGIN=1%{relocbegin} +RUN: llvm-readobj %t.broken-header.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=EMPTY,WARN-INVALIDHEADER --match-full-lines + +; Test that llvm-readobj warns if end < start. +RUN: yaml2obj -o %t.negative-size.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DBEGIN=%{relocend} -DEND=%{relocbegin} +RUN: llvm-readobj %t.negative-size.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=EMPTY,WARN-LOWEREND -D#BEGIN=%{relocend} -D#END=%{relocbegin} --match-full-lines + +; Test that llvm-readobj warns if the marker symbol points out of the section space. +RUN: yaml2obj -o %t.outofrange-both.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DBEGIN=8888 -DEND=9999 +RUN: llvm-readobj %t.outofrange-both.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=EMPTY,WARN-OUTOFRANGE --match-full-lines -D#RDATASIZE=%{rdatasize} + +RUN: yaml2obj -o %t.outofrange-end.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DEND=8888 +RUN: llvm-readobj %t.outofrange-end.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=EMPTY,WARN-OUTOFRANGE --match-full-lines -D#RDATASIZE=%{rdatasize} + +; Test that llvm-readobj warns if the marker symbols point different sections. +RUN: yaml2obj -o %t.section-differs.exe-i386 %p/Inputs/pseudoreloc.i386.yaml -DSECTION_OF_BEGIN=1 +RUN: llvm-readobj %t.section-differs.exe-i386 --coff-pseudoreloc 2>&1 | \ +RUN: FileCheck %s --check-prefixes=EMPTY,WARN-SECTIONDIFFERS --match-full-lines + +EMPTY: Format: COFF-i386 +EMPTY-NEXT: Arch: i386 +EMPTY-NEXT: AddressSize: 32bit +EMPTY-NEXT: PseudoReloc [ +WARN-MISSINGMARKER-NEXT: {{.*}}warning: {{.*}}: the marker symbols for runtime pseudo-relocation were not found +WARN-INVALIDHEADER-NEXT: {{.*}}warning: {{.*}}: invalid runtime pseudo-relocation records +WARN-LOWEREND-NEXT: {{.*}}warning: {{.*}}: the end marker symbol for runtime pseudo-relocation must point to a higher address than where the begin marker points to: expected >=0x[[#%x,BEGIN]], but got 0x[[#%x,END]] +WARN-OUTOFRANGE-NEXT: {{.*}}warning: {{.*}}: the marker symbol of runtime pseudo-relocation points past the end of the section 0x[[#%x,RDATASIZE]]: got 0x[[#%x,8888]] +WARN-SECTIONDIFFERS-NEXT: {{.*}}warning: {{.*}}: the end marker symbol for runtime pseudo-relocation must point to the same section where the begin marker points to: expected 1, but got {{[2-9]}} +EMPTY-NEXT: ] + +;; +;; To regenerate Inputs/pseudoreloc.*.yaml, run following one-liner and review actual address map: +;; +;; $ split-file pseudoreloc.test /tmp/pseudoreloc && bash /tmp/pseudoreloc/generate.sh && cp /tmp/pseudoreloc/*.yaml Inputs/ +;; + +#--- generate.sh +cd "$(dirname $0)" +set -e + +generate() { + LANG=C + local arch=$1 + local emul=$2 + + llc -mtriple $arch-mingw32 -filetype obj export1.ll -o export1.$arch.o + ld.lld -m $emul --dll export1.$arch.o -o export1.$arch.dll -entry= + llc -mtriple $arch-mingw32 -filetype obj export2.ll -o export2.$arch.o + ld.lld -m $emul --dll export2.$arch.o -o export2.$arch.dll -entry= + llc -mtriple $arch-mingw32 -filetype obj import.ll -o import.$arch.o + ld.lld -m $emul -S import.$arch.o export1.$arch.dll export2.$arch.dll -o pseudoreloc.$arch.exe -entry=start \ + --disable-dynamicbase --disable-reloc-section + + obj2yaml pseudoreloc.$arch.exe -o pseudoreloc.$arch.yaml.orig + + llvm-readobj --coff-imports --syms --section-headers pseudoreloc.$arch.exe > dump.$arch.txt + local begin=$(sed -n -e '/__RUNTIME_PSEUDO_RELOC_LIST__/,/Value:/{/Value:/{s/ *Value: *//p;q}}' dump.$arch.txt) + + # Make these parameterizable: + # - the referenced symbol in 1st, 2nd, and 3rd relocation entry + # - the marker symbols' value + # - a section which the marker symbol belongs to + # - a section which the symbol of the relocation target belongs to + sed -E -f - pseudoreloc.$arch.yaml.orig <<EOT > pseudoreloc.$arch.yaml +/- Name: *\\.rdata/,/SectionData:/{ + s/( *SectionData: *[0-9A-F]{$(($begin * 2 + 24))})(.{8})(.{16})(.{8})(.{16})(.{8})/\\1[[SYMBOL0=\\2]]\\3[[SYMBOL1=\\4]]\\5[[SYMBOL2=\\6]]/ +} +/__RUNTIME_PSEUDO_RELOC_LIST_END__/,/Value:/{ + /Value:/s/([0-9]+)/[[END=\1]]/ +} +/__RUNTIME_PSEUDO_RELOC_LIST__/,/Value:/{ + /Value:/s/([0-9]+)/[[BEGIN=\1]]/ +} +/__RUNTIME_PSEUDO_RELOC_LIST__/,/SectionNumber:/{ + /SectionNumber:/s/([0-9]+)/[[SECTION_OF_BEGIN=\1]]/ +} +/local2a/,/SectionNumber:/{ + /SectionNumber:/s/([0-9]+)/[[SECTION_OF_LOCAL2A=\1]]/ +} +EOT + + # Ensure the binaries generated from the parameterized yaml and original one are exactly the same. + diff <(yaml2obj pseudoreloc.$arch.yaml.orig -o -) <(yaml2obj pseudoreloc.$arch.yaml -o -) +} + +generate i386 i386pe +generate x86_64 i386pep + +#--- export1.ll +@sym1 = dso_local dllexport global [4 x i8] c"\11\22\33\44" +@sym2 = dso_local dllexport global [4 x i8] c"\55\66\77\88" + +#--- export2.ll +@sym3 = dso_local dllexport global [4 x i8] c"\AA\BB\CC\DD" + +#--- import.ll +@__RUNTIME_PSEUDO_RELOC_LIST__ = external dso_local constant ptr +@__RUNTIME_PSEUDO_RELOC_LIST_END__ = external dso_local constant ptr +@sym1 = external dso_local global [4 x i8] +@sym2 = external dso_local global [4 x i8] +@sym3 = external dso_local global [4 x i8] +@dummy_to_bump_address = private constant i64 u0x4488226655117733 +@local1a = private global ptr getelementptr (i8, ptr @sym1, i32 1) +@local2a = dso_local global ptr getelementptr (i8, ptr @sym2, i32 2) +@local3a = dso_local global [2 x ptr] [ptr getelementptr (i8, ptr @sym3, i32 1), ptr getelementptr (i8, ptr @sym3, i32 1)] +@local1b = private global ptr getelementptr (i8, ptr @sym1, i32 2) + +define dso_local i32 @start() noinline nounwind { + %p1a = load ptr, ptr @local1a + %v1a = load i8, ptr %p1a + %x1a = sext i8 %v1a to i32 + %p2a = load ptr, ptr @local2a + %v2a = load i8, ptr %p2a + %x2a = sext i8 %v2a to i32 + %p3a = load ptr, ptr @local3a + %v3a = load i8, ptr %p3a + %x3a = sext i8 %v3a to i32 + %p1b = load ptr, ptr @local1b + %v1b = load i8, ptr %p1b + %x1b = sext i8 %v1b to i32 + %1 = add nsw i32 %x1a, %x2a + %2 = add nsw i32 %x3a, %x1b + %3 = add nsw i32 %1, %2 + ret i32 %3 +} + +define dso_local i32 @_pei386_runtime_relocator() noinline nounwind { + %1 = load ptr, ptr @__RUNTIME_PSEUDO_RELOC_LIST_END__ + %2 = load ptr, ptr @__RUNTIME_PSEUDO_RELOC_LIST__ + %3 = ptrtoint ptr %1 to i64 + %4 = ptrtoint ptr %2 to i64 + %5 = sub i64 %3, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} diff --git a/llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test b/llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test index 5d7bc8b..fd1492f 100644 --- a/llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test +++ b/llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test @@ -49,7 +49,7 @@ # CHECK-NEXT: { # CHECK-NEXT: ID: 2 # CHECK-NEXT: Offset: 0x3 -# CHECK-NEXT: Callsite Offsets: [1, 3] +# CHECK-NEXT: Callsite End Offsets: [1, 3] # CHECK-NEXT: Size: 0x7 # CHECK-NEXT: HasReturn: Yes # CHECK-NEXT: HasTailCall: No @@ -159,7 +159,7 @@ Sections: AddressOffset: 0x3 Size: 0x4 Metadata: 0x15 - CallsiteOffsets: [ 0x1 , 0x2 ] + CallsiteEndOffsets: [ 0x1 , 0x2 ] - Version: 2 BBRanges: - BaseAddress: 0x22222 diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test index d7fe77c..d97cb70 100644 --- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test +++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test @@ -57,6 +57,7 @@ # CHECK: Type: R_AARCH64_LD64_GOT_LO12_NC (312) # CHECK: Type: R_AARCH64_LD64_GOTPAGE_LO15 (313) # CHECK: Type: R_AARCH64_PLT32 (314) +# CHECK: Type: R_AARCH64_PATCHINST (316) # CHECK: Type: R_AARCH64_TLSGD_ADR_PREL21 (512) # CHECK: Type: R_AARCH64_TLSGD_ADR_PAGE21 (513) # CHECK: Type: R_AARCH64_TLSGD_ADD_LO12_NC (514) @@ -214,6 +215,7 @@ Sections: - Type: R_AARCH64_LD64_GOT_LO12_NC - Type: R_AARCH64_LD64_GOTPAGE_LO15 - Type: R_AARCH64_PLT32 + - Type: R_AARCH64_PATCHINST - Type: R_AARCH64_TLSGD_ADR_PREL21 - Type: R_AARCH64_TLSGD_ADR_PAGE21 - Type: R_AARCH64_TLSGD_ADD_LO12_NC diff --git a/llvm/test/tools/llvm-readobj/ELF/sframe-fde.test b/llvm/test/tools/llvm-readobj/ELF/sframe-fde.test index dee4018..b9075a8 100644 --- a/llvm/test/tools/llvm-readobj/ELF/sframe-fde.test +++ b/llvm/test/tools/llvm-readobj/ELF/sframe-fde.test @@ -108,6 +108,8 @@ Sections: # CASE1-NEXT: } # CASE1-NEXT: Repetitive block size: 0xDE # CASE1-NEXT: Padding2: 0xAD +# CASE1-NEXT: FREs [ +# CASE1-NEXT: ] # CASE1-NEXT: } # CASE1-NEXT: ] # CASE1-NEXT:} @@ -169,6 +171,8 @@ Sections: # CASE1-NEXT: } # CASE1-NEXT: Repetitive block size (unused): 0xDE # CASE1-NEXT: Padding2: 0xAD +# CASE1-NEXT: FREs [ +# CASE1-NEXT: ] # CASE1-NEXT: } # CASE1-NEXT: ] # CASE1-NEXT:} @@ -196,7 +200,7 @@ Sections: 0x00, 0xde, 0xad, 0x00, # Start Address 0x00, 0x00, 0x01, 0xbe, # Size 0x00, 0x00, 0x00, 0x10, # Start FRE Offset - 0x00, 0x00, 0x00, 0x10, # Number of FREs + 0x00, 0x00, 0x00, 0x00, # Number of FREs 0x02, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 ] # CASE2-LABEL:SFrame section '.sframe' { @@ -223,7 +227,7 @@ Sections: # CASE2-NEXT: PC: 0xDEAD1C # CASE2-NEXT: Size: 0x1BE # CASE2-NEXT: Start FRE Offset: 0x10 -# CASE2-NEXT: Num FREs: 16 +# CASE2-NEXT: Num FREs: 0 # CASE2-NEXT: Info { # CASE2-NEXT: FRE Type: Addr4 (0x2) # CASE2-NEXT: FDE Type: PCInc (0x0) @@ -232,6 +236,8 @@ Sections: # CASE2-NEXT: } # CASE2-NEXT: Repetitive block size (unused): 0xDE # CASE2-NEXT: Padding2: 0xAD00 +# CASE2-NEXT: FREs [ +# CASE2-NEXT: ] # CASE2-NEXT: } # CASE2-NEXT: ] # CASE2-NEXT:} diff --git a/llvm/test/tools/llvm-readobj/ELF/sframe-fre.test b/llvm/test/tools/llvm-readobj/ELF/sframe-fre.test new file mode 100644 index 0000000..3f1e7d6 --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/sframe-fre.test @@ -0,0 +1,303 @@ +# RUN: yaml2obj --docnum=1 %s -o %t.1 +# RUN: llvm-readobj --sframe=.sframe_eof_address --sframe=.sframe_eof_offset --sframe \ +# RUN: %t.1 2>&1 | \ +# RUN: FileCheck %s --strict-whitespace --match-full-lines \ +# RUN: -DFILE=%t.1 --check-prefix=CASE1 + +# RUN: yaml2obj --docnum=2 %s -o %t.2 +# RUN: llvm-readobj --sframe %t.2 2>&1 | \ +# RUN: FileCheck %s --strict-whitespace --match-full-lines \ +# RUN: -DFILE=%t.2 --check-prefix=CASE2 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC +Sections: + - Name: .sframe_eof_address + Type: SHT_GNU_SFRAME + Flags: [ SHF_ALLOC ] + ContentArray: [ + 0xe2, 0xde, 0x02, 0x04, # Preamble (magic, version, flags) + # Header: + 0x03, 0x42, 0x47, 0x00, # ABI, Fixed FP offset, Fixed RA Offset, AUX header length + 0x01, 0x00, 0x00, 0x00, # Number of FDEs + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0x10, 0x00, 0x00, # FRE length + 0x00, 0x00, 0x00, 0x00, # FDE offset + 0x00, 0x00, 0x00, 0x00, # FRE offset + + # FDE[0]: + 0x00, 0xde, 0xad, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FRE[0]: + 0x00 # Start Address, (missing) Info + ] +# CASE1-LABEL:SFrame section '.sframe_eof_address' { +# CASE1: FuncDescEntry [0] { +# CASE1: Info { +# CASE1-NEXT: FRE Type: Addr1 (0x0) +# CASE1-NEXT: FDE Type: PCInc (0x0) +# CASE1: FREs [ +# CASE1-NEXT:{{.*}}: warning: '[[FILE]]': unexpected end of data at offset 0x31 while reading [0x30, 0x32) +# CASE1-NEXT: ] + + - Name: .sframe_eof_offset + Type: SHT_GNU_SFRAME + Flags: [ SHF_ALLOC ] + ContentArray: [ + 0xe2, 0xde, 0x02, 0x04, # Preamble (magic, version, flags) + # Header: + 0x03, 0x42, 0x47, 0x00, # ABI, Fixed FP offset, Fixed RA Offset, AUX header length + 0x01, 0x00, 0x00, 0x00, # Number of FDEs + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0x10, 0x00, 0x00, # FRE length + 0x00, 0x00, 0x00, 0x00, # FDE offset + 0x00, 0x00, 0x00, 0x00, # FRE offset + + # FDE[0]: + 0x00, 0xde, 0xad, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FRE[0]: + 0x00, 0x02 # Start Address, Info, (missing) Offsets + ] +# CASE1-LABEL:SFrame section '.sframe_eof_offset' { +# CASE1: FuncDescEntry [0] { +# CASE1: Info { +# CASE1-NEXT: FRE Type: Addr1 (0x0) +# CASE1-NEXT: FDE Type: PCInc (0x0) +# CASE1: FREs [ +# CASE1-NEXT:{{.*}}: warning: '[[FILE]]': unexpected end of data at offset 0x32 while reading [0x32, 0x33) +# CASE1-NEXT: ] + + - Name: .sframe + Type: SHT_GNU_SFRAME + Flags: [ SHF_ALLOC ] + ContentArray: [ + 0xe2, 0xde, 0x02, 0x04, # Preamble (magic, version, flags) + # Header: + 0x03, 0x42, 0x40, 0x00, # ABI, Fixed FP offset, Fixed RA Offset, AUX header length + 0x03, 0x00, 0x00, 0x00, # Number of FDEs + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0x10, 0x00, 0x00, # FRE length + 0x00, 0x00, 0x00, 0x00, # FDE offset + 0x00, 0x00, 0x00, 0x00, # FRE offset + + # FDE[0]: + 0x00, 0x00, 0xde, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x02, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FDE[1]: + 0x00, 0x00, 0xad, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x08, 0x00, 0x00, 0x00, # Start FRE Offset + 0x03, 0x00, 0x00, 0x00, # Number of FREs + 0x11, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FDE[2]: + 0x00, 0x00, 0xbe, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x08, 0x00, 0x00, 0x00, # Start FRE Offset + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x03, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FRE[0,0]: Zero offsets + 0x00, 0x00, # Start Address, Info + + # FRE[0,1]: One four-byte offset, SP-based + 0x01, 0x43, # Start Address, Info + 0x74, 0x00, 0x00, 0x00, # Offset[0] + + # FRE[1,0]: Two two-byte offsets, FP-based + 0x00, 0x00, 0x24, # Start Address, Info + 0x10, 0x00, 0x20, 0x00, # Offset[0], Offset[1] + + # FRE[1,1]: Four one-byte offsets, FP-based + 0x00, 0x01, 0x08, # Start Address, Info + 0x10, 0x20, 0x30, 0x40, # Offset[0-3] + ] +## Testing: +## - little-endian support +## - AMD64 ABI +## - one and two byte address sizes +## - PCInc and PCMask FDE types +## - all offset sizes +## - various offset counts +## - hitting EOF after printing some number of FREs +## - invalid FRE type +# CASE1-LABEL:SFrame section '.sframe' { +# CASE1: ABI: AMD64EndianLittle (0x3) +# CASE1: CFA fixed RA offset: 64 +# CASE1: FuncDescEntry [0] { +# CASE1-NEXT: PC: 0xDE007F +# CASE1: Info { +# CASE1-NEXT: FRE Type: Addr1 (0x0) +# CASE1-NEXT: FDE Type: PCInc (0x0) +# CASE1: FREs [ +# CASE1-NEXT: Frame Row Entry { +# CASE1-NEXT: Start Address: 0xDE007F +# CASE1-NEXT: Return Address Signed: No +# CASE1-NEXT: Offset Size: B1 (0x0) +# CASE1-NEXT: Base Register: FP (0x0) +# CASE1-NEXT: RA Offset: 64 +# CASE1-NEXT: } +# CASE1-NEXT: Frame Row Entry { +# CASE1-NEXT: Start Address: 0xDE0080 +# CASE1-NEXT: Return Address Signed: No +# CASE1-NEXT: Offset Size: B4 (0x2) +# CASE1-NEXT: Base Register: SP (0x1) +# CASE1-NEXT: CFA Offset: 116 +# CASE1-NEXT: RA Offset: 64 +# CASE1-NEXT: } +# CASE1-NEXT: ] +# CASE1: FuncDescEntry [1] { +# CASE1-NEXT: PC: 0xAD0093 +# CASE1: Info { +# CASE1-NEXT: FRE Type: Addr2 (0x1) +# CASE1-NEXT: FDE Type: PCMask (0x1) +# CASE1: FREs [ +# CASE1-NEXT: Frame Row Entry { +# CASE1-NEXT: Start Address: 0x0 +# CASE1-NEXT: Return Address Signed: No +# CASE1-NEXT: Offset Size: B2 (0x1) +# CASE1-NEXT: Base Register: FP (0x0) +# CASE1-NEXT: CFA Offset: 16 +# CASE1-NEXT: RA Offset: 64 +# CASE1-NEXT: FP Offset: 32 +# CASE1-NEXT: } +# CASE1-NEXT: Frame Row Entry { +# CASE1-NEXT: Start Address: 0x100 +# CASE1-NEXT: Return Address Signed: No +# CASE1-NEXT: Offset Size: B1 (0x0) +# CASE1-NEXT: Base Register: FP (0x0) +# CASE1-NEXT: CFA Offset: 16 +# CASE1-NEXT: RA Offset: 64 +# CASE1-NEXT: FP Offset: 32 +# CASE1-NEXT: Extra Offsets: [48, 64] +# CASE1-NEXT: } +# CASE1-NEXT:{{.*}}: warning: '[[FILE]]': unexpected end of data at offset 0x6e while reading [0x6e, 0x71) +# CASE1: FuncDescEntry [2] { +# CASE1: Info { +# CASE1-NEXT: FRE Type: 0x3 +# CASE1: FREs [ +# CASE1-NEXT:{{.*}}: warning: '[[FILE]]': unsupported FRE type 3 at offset 0x60 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2MSB + Type: ET_EXEC +Sections: + - Name: .sframe + Type: SHT_GNU_SFRAME + Flags: [ SHF_ALLOC ] + ContentArray: [ + 0xde, 0xe2, 0x02, 0x05, # Preamble (magic, version, flags) + # Header: + 0x01, 0x42, 0x47, 0x00, # ABI, Fixed FP offset, Fixed RA Offset, AUX header length + 0x00, 0x00, 0x00, 0x01, # Number of FDEs + 0x00, 0x00, 0x00, 0x10, # Number of FREs + 0x00, 0x00, 0x10, 0x00, # FRE length + 0x00, 0x00, 0x00, 0x00, # FDE offset + 0x00, 0x00, 0x01, 0x00, # FRE offset + + # FDE: + 0x00, 0xde, 0x00, 0x00, # Start Address + 0x00, 0x00, 0x01, 0xbe, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x00, 0x00, 0x00, 0x06, # Number of FREs + 0x02, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FRE[0]: Zero offsets + 0x00, 0x00, 0x00, 0x00, # Start Address + 0x00, # Info + + # FRE[1]: One offset + 0x00, 0x00, 0x00, 0x01, # Start Address + 0x82, 0x10, # Info, Offset[0] + + # FRE[2]: Two offsets + 0x00, 0x00, 0x00, 0x02, # Start Address + 0x04, 0x10, 0x20, # Info, Offset[0-1] + + # FRE[3]: Three offsets + 0x00, 0x00, 0x00, 0x03, # Start Address + 0x86, 0x10, 0x20, 0x30, # Info, Offset[0-2] + + # FRE[4]: Four offsets + 0x00, 0x00, 0x00, 0x04, # Start Address + 0x08, # Info + 0x10, 0x20, 0x30, 0x40, # Offset[0-3] + + # FRE[4]: Invalid offset size + 0x00, 0x00, 0x00, 0x05, # Start Address + 0x60, # Info + ] +## Testing: +## - big-endian support +## - ARM64 ABI +## - four-byte address sizes +## - return address signing +## - various offset counts +## - invalid offset size +# CASE2-LABEL:SFrame section '.sframe' { +# CASE2: ABI: AArch64EndianBig (0x1) +# CASE2: FuncDescEntry [0] { +# CASE2-NEXT: PC: 0xDE001C +# CASE2: Info { +# CASE2-NEXT: FRE Type: Addr4 (0x2) +# CASE2-NEXT: FDE Type: PCInc (0x0) +# CASE2: FREs [ +# CASE2-NEXT: Frame Row Entry { +# CASE2-NEXT: Start Address: 0xDE001C +# CASE2-NEXT: Return Address Signed: No +# CASE2-NEXT: Offset Size: B1 (0x0) +# CASE2-NEXT: Base Register: FP (0x0) +# CASE2-NEXT: } +# CASE2-NEXT: Frame Row Entry { +# CASE2-NEXT: Start Address: 0xDE001D +# CASE2-NEXT: Return Address Signed: Yes +# CASE2-NEXT: Offset Size: B1 (0x0) +# CASE2-NEXT: Base Register: FP (0x0) +# CASE2-NEXT: CFA Offset: 16 +# CASE2-NEXT: } +# CASE2-NEXT: Frame Row Entry { +# CASE2-NEXT: Start Address: 0xDE001E +# CASE2-NEXT: Return Address Signed: No +# CASE2-NEXT: Offset Size: B1 (0x0) +# CASE2-NEXT: Base Register: FP (0x0) +# CASE2-NEXT: CFA Offset: 16 +# CASE2-NEXT: RA Offset: 32 +# CASE2-NEXT: } +# CASE2-NEXT: Frame Row Entry { +# CASE2-NEXT: Start Address: 0xDE001F +# CASE2-NEXT: Return Address Signed: Yes +# CASE2-NEXT: Offset Size: B1 (0x0) +# CASE2-NEXT: Base Register: FP (0x0) +# CASE2-NEXT: CFA Offset: 16 +# CASE2-NEXT: RA Offset: 32 +# CASE2-NEXT: FP Offset: 48 +# CASE2-NEXT: } +# CASE2-NEXT: Frame Row Entry { +# CASE2-NEXT: Start Address: 0xDE0020 +# CASE2-NEXT: Return Address Signed: No +# CASE2-NEXT: Offset Size: B1 (0x0) +# CASE2-NEXT: Base Register: FP (0x0) +# CASE2-NEXT: CFA Offset: 16 +# CASE2-NEXT: RA Offset: 32 +# CASE2-NEXT: FP Offset: 48 +# CASE2-NEXT: Extra Offsets: [64] +# CASE2-NEXT: } +# CASE2-NEXT:{{.*}}: warning: '[[FILE]]': unsupported FRE offset size 3 at offset 0x58 diff --git a/llvm/test/tools/llvm-readobj/ELF/sframe-reloc.test b/llvm/test/tools/llvm-readobj/ELF/sframe-reloc.test new file mode 100644 index 0000000..e96ae02 --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/sframe-reloc.test @@ -0,0 +1,93 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-readobj --sframe %t 2>&1 | \ +# RUN: FileCheck %s --strict-whitespace --match-full-lines -DFILE=%t + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_X86_64 +Sections: + - Name: .text + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Size: 0x1000 + - Name: .sframe + Type: SHT_GNU_SFRAME + Flags: [ SHF_ALLOC ] + ContentArray: [ + 0xe2, 0xde, 0x02, 0x04, # Preamble (magic, version, flags) + # Header: + 0x03, 0x42, 0x40, 0x00, # ABI, Fixed FP offset, Fixed RA Offset, AUX header length + 0x03, 0x00, 0x00, 0x00, # Number of FDEs + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0x10, 0x00, 0x00, # FRE length + 0x00, 0x00, 0x00, 0x00, # FDE offset + 0x00, 0x00, 0x00, 0x00, # FRE offset + + # FDE[0]: + 0x00, 0x00, 0xde, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x01, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FDE[1]: + 0x00, 0x00, 0xad, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x00, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FDE[2]: + 0x00, 0x00, 0xbe, 0x00, # Start Address + 0xbe, 0x01, 0x00, 0x00, # Size + 0x00, 0x00, 0x00, 0x00, # Start FRE Offset + 0x00, 0x00, 0x00, 0x00, # Number of FREs + 0x00, 0xde, 0xad, 0x00, # Info, RepSize, Padding2 + + # FRE[0]: + 0x05, 0x02, 0x10, # Start Address, Info, Offset[0] + + ] + - Name: .rela.sframe + Type: SHT_RELA + Flags: [ SHF_INFO_LINK ] + Link: .symtab + AddressAlign: 0x8 + Info: .sframe + Relocations: + - Offset: 0x1c + Symbol: .text + Type: R_X86_64_PC32 + Addend: 0x42 + - Offset: 0x30 + Symbol: .text + Type: R_X86_64_PC32 + - Offset: 0x30 + Symbol: .text + Type: R_X86_64_PC32 + - Offset: 0x44 + Symbol: 4747 + Type: R_X86_64_PC32 +Symbols: + - Name: .text + Type: STT_SECTION + Section: .text +# CHECK-LABEL:SFrame section '.sframe' { +# CHECK: ABI: AMD64EndianLittle (0x3) +# CHECK: FuncDescEntry [0] { +# CHECK-NEXT: PC { +# CHECK-NEXT: Relocation: R_X86_64_PC32 +# CHECK-NEXT: Symbol Name: .text +# CHECK-NEXT: Start Address: 0xDE0042 +# CHECK-NEXT: } +# CHECK: FREs [ +# CHECK-NEXT: Frame Row Entry { +# CHECK-NEXT: Start Address: 0xDE0047 +# CHECK: FuncDescEntry [1] { +# CHECK-NEXT:{{.*}}: warning: '[[FILE]]': more than one relocation at offset 0x30 +# CHECK-NEXT: PC: 0xAD0030 +# CHECK: FuncDescEntry [2] { +# CHECK-NEXT:{{.*}}: warning: '[[FILE]]': unable to read an entry with index 4747 from SHT_SYMTAB section with index {{[0-9]*}}: can't read an entry at 0x{{[0-9a-f]*}}: it goes past the end of the section (0x30) diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir b/llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir index d7ad5f8..9af4ac38 100644 --- a/llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir +++ b/llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir @@ -20,8 +20,10 @@ # RESULT-NEXT: hasVAStart: true # RESULT-NEXT: hasMustTailInVarArgFunc: true # RESULT-NEXT: hasTailCall: true -# RESULT-NEXT: savePoint: '%bb.1' -# RESULT-NEXT: restorePoint: '%bb.2' +# RESULT-NEXT: savePoint: +# RESULT-NEXT: - point: '%bb.1' +# RESULT-NEXT: restorePoint: +# RESULT-NEXT: - point: '%bb.2' # RESULT-NEXT: fixedStack: # RESULT-NEXT: - { id: 0, offset: 56, size: 4, alignment: 8, callee-saved-register: '$sgpr44', @@ -116,8 +118,10 @@ frameInfo: hasMustTailInVarArgFunc: true hasTailCall: true localFrameSize: 0 - savePoint: '%bb.1' - restorePoint: '%bb.2' + savePoint: + - point: '%bb.1' + restorePoint: + - point: '%bb.2' fixedStack: - { id: 0, offset: 0, size: 8, alignment: 4, isImmutable: true, isAliased: false } diff --git a/llvm/test/tools/llvm-reduce/operands-to-args-lifetimes.ll b/llvm/test/tools/llvm-reduce/operands-to-args-lifetimes.ll index d9ed9df..5db1989 100644 --- a/llvm/test/tools/llvm-reduce/operands-to-args-lifetimes.ll +++ b/llvm/test/tools/llvm-reduce/operands-to-args-lifetimes.ll @@ -4,15 +4,15 @@ ; INTERESTING: store ; REDUCED: define void @test(ptr %a) { ; REDUCED-NEXT: %a1 = alloca i32 -; REDUCED-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr %a1) +; REDUCED-NEXT: call void @llvm.lifetime.start.p0(ptr %a1) ; REDUCED-NEXT: store i32 0, ptr %a ; REDUCED-NEXT: store i32 1, ptr %a -; REDUCED-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr %a1) +; REDUCED-NEXT: call void @llvm.lifetime.end.p0(ptr %a1) define void @test() { %a = alloca i32 - call void @llvm.lifetime.start.p0(i64 4, ptr %a) + call void @llvm.lifetime.start.p0(ptr %a) store i32 0, ptr %a store i32 1, ptr %a - call void @llvm.lifetime.end.p0(i64 4, ptr %a) + call void @llvm.lifetime.end.p0(ptr %a) ret void } diff --git a/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll b/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll index b68f718..75b152f 100644 --- a/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll +++ b/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll @@ -69,13 +69,13 @@ define void @alloca_constexpr_elt() { } ; CHECK-LABEL: @alloca_lifetimes( -; ZERO: call void @llvm.lifetime.start.p0(i64 4, ptr %alloca) -; ONE: call void @llvm.lifetime.start.p0(i64 4, ptr %alloca) -; POISON: call void @llvm.lifetime.start.p0(i64 4, ptr %alloca) +; ZERO: call void @llvm.lifetime.start.p0(ptr %alloca) +; ONE: call void @llvm.lifetime.start.p0(ptr %alloca) +; POISON: call void @llvm.lifetime.start.p0(ptr %alloca) define void @alloca_lifetimes() { %alloca = alloca i32 - call void @llvm.lifetime.start.p0(i64 4, ptr %alloca) + call void @llvm.lifetime.start.p0(ptr %alloca) store i32 0, ptr %alloca - call void @llvm.lifetime.end.p0(i64 4, ptr %alloca) + call void @llvm.lifetime.end.p0(ptr %alloca) ret void } diff --git a/llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml b/llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml index 861cb94..dc14025 100644 --- a/llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml +++ b/llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml @@ -39,7 +39,7 @@ # VALID-NEXT: AddressOffset: 0xA # VALID-NEXT: Size: 0xB # VALID-NEXT: Metadata: 0xC -# VALID-NEXT: CallsiteOffsets: [ 0x1, 0x2 ] +# VALID-NEXT: CallsiteEndOffsets: [ 0x1, 0x2 ] --- !ELF FileHeader: @@ -79,7 +79,7 @@ Sections: AddressOffset: 0xA Size: 0xB Metadata: 0xC - CallsiteOffsets: [ 0x1, 0x2 ] + CallsiteEndOffsets: [ 0x1, 0x2 ] ## Check obj2yaml can dump empty .llvm_bb_addr_map sections. diff --git a/llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml b/llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml index 9fd0577..418f90f 100644 --- a/llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml +++ b/llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml @@ -66,7 +66,7 @@ # CHECK-NEXT: 0000: 030800 # CHECK-NEXT: ) -# Case 9: Specify empty CallsiteOffsets. +# Case 9: Specify empty CallsiteEndOffsets. # CHECK: Name: .llvm_bb_addr_map (1) # CHECK: SectionData ( # CHECK-NEXT: 0000: 03202000 00000000 0000010E 01000203 @@ -113,7 +113,7 @@ Sections: AddressOffset: 0x00000001 Size: 0x00000002 Metadata: 0x00000003 - CallsiteOffsets: [0x1, 0x2] + CallsiteEndOffsets: [0x1, 0x2] ## 5) When specifying the description with Entries, the 'Address' field will be ## zero when omitted. @@ -174,7 +174,7 @@ Sections: AddressOffset: 0x00000001 Size: 0x00000002 Metadata: 0x00000003 - CallsiteOffsets: [] + CallsiteEndOffsets: [] ## Check we can't use Entries at the same time as either Content or Size. # RUN: not yaml2obj --docnum=2 -DCONTENT="00" %s 2>&1 | FileCheck %s --check-prefix=INVALID |