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-rw-r--r--llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll13
-rw-r--r--llvm/test/CodeGen/SystemZ/int-cmp-65.ll259
-rw-r--r--llvm/test/CodeGen/SystemZ/int-max-02.ll16
-rw-r--r--llvm/test/CodeGen/SystemZ/int-min-02.ll16
-rw-r--r--llvm/test/CodeGen/SystemZ/saturating-truncation.ll95
-rw-r--r--llvm/test/CodeGen/SystemZ/shift-17.ll51
6 files changed, 386 insertions, 64 deletions
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
index c088f6d..9271dc7 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
@@ -363,10 +363,11 @@ define i128 @atomicrmw_uinc_wrap(ptr %src, i128 %b) {
define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
; CHECK-LABEL: atomicrmw_udec_wrap:
; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI12_0
; CHECK-NEXT: vl %v0, 0(%r4), 3
; CHECK-NEXT: vl %v3, 0(%r3), 4
-; CHECK-NEXT: vgbm %v1, 65535
-; CHECK-NEXT: vgbm %v2, 0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vgbm %v2, 65535
; CHECK-NEXT: j .LBB12_2
; CHECK-NEXT: .LBB12_1: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
@@ -379,6 +380,9 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
; CHECK-NEXT: je .LBB12_8
; CHECK-NEXT: .LBB12_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vscbiq %v4, %v3, %v1
+; CHECK-NEXT: vlgvf %r0, %v4, 3
+; CHECK-NEXT: xilf %r0, 1
; CHECK-NEXT: veclg %v0, %v3
; CHECK-NEXT: jlh .LBB12_4
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
@@ -390,12 +394,11 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
; CHECK-NEXT: jl .LBB12_6
; CHECK-NEXT: # %bb.5: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
-; CHECK-NEXT: vaq %v4, %v3, %v1
+; CHECK-NEXT: vaq %v4, %v3, %v2
; CHECK-NEXT: .LBB12_6: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
-; CHECK-NEXT: vceqgs %v5, %v3, %v2
; CHECK-NEXT: vlr %v5, %v0
-; CHECK-NEXT: je .LBB12_1
+; CHECK-NEXT: cijlh %r0, 0, .LBB12_1
; CHECK-NEXT: # %bb.7: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
; CHECK-NEXT: vlr %v5, %v4
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-65.ll b/llvm/test/CodeGen/SystemZ/int-cmp-65.ll
index b06ab3c..f1d8502 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-65.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-65.ll
@@ -1,42 +1,110 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test usage of VACC/VSCBI.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=BASELINE
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
define i128 @i128_subc_1(i128 %a, i128 %b) unnamed_addr {
-; CHECK-LABEL: i128_subc_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vscbiq %v0, %v1, %v0
-; CHECK-NEXT: vst %v0, 0(%r2), 3
-; CHECK-NEXT: br %r14
+; BASELINE-LABEL: i128_subc_1:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)
+; BASELINE-NEXT: .cfi_offset %r14, -48
+; BASELINE-NEXT: .cfi_offset %r15, -40
+; BASELINE-NEXT: lg %r5, 0(%r4)
+; BASELINE-NEXT: lg %r14, 0(%r3)
+; BASELINE-NEXT: lg %r1, 8(%r3)
+; BASELINE-NEXT: clgr %r14, %r5
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: clg %r1, 8(%r4)
+; BASELINE-NEXT: ipm %r1
+; BASELINE-NEXT: cgrjlh %r14, %r5, .LBB0_2
+; BASELINE-NEXT: # %bb.1:
+; BASELINE-NEXT: xilf %r1, 4294967295
+; BASELINE-NEXT: risbg %r0, %r1, 63, 191, 36
+; BASELINE-NEXT: j .LBB0_3
+; BASELINE-NEXT: .LBB0_2:
+; BASELINE-NEXT: xilf %r0, 4294967295
+; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 36
+; BASELINE-NEXT: .LBB0_3:
+; BASELINE-NEXT: llgfr %r0, %r0
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_subc_1:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r4), 3
+; Z13-NEXT: vl %v1, 0(%r3), 3
+; Z13-NEXT: vscbiq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
%cmp = icmp uge i128 %a, %b
%ext = zext i1 %cmp to i128
ret i128 %ext
}
define i128 @i128_subc_2(i128 %a, i128 %b) unnamed_addr {
-; CHECK-LABEL: i128_subc_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r4), 3
-; CHECK-NEXT: vscbiq %v0, %v1, %v0
-; CHECK-NEXT: vst %v0, 0(%r2), 3
-; CHECK-NEXT: br %r14
+; BASELINE-LABEL: i128_subc_2:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)
+; BASELINE-NEXT: .cfi_offset %r14, -48
+; BASELINE-NEXT: .cfi_offset %r15, -40
+; BASELINE-NEXT: lg %r5, 0(%r4)
+; BASELINE-NEXT: lg %r14, 0(%r3)
+; BASELINE-NEXT: lg %r0, 8(%r3)
+; BASELINE-NEXT: clgr %r14, %r5
+; BASELINE-NEXT: ipm %r1
+; BASELINE-NEXT: clg %r0, 8(%r4)
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: cgrjlh %r14, %r5, .LBB1_2
+; BASELINE-NEXT: # %bb.1:
+; BASELINE-NEXT: afi %r0, -536870912
+; BASELINE-NEXT: srl %r0, 31
+; BASELINE-NEXT: j .LBB1_3
+; BASELINE-NEXT: .LBB1_2:
+; BASELINE-NEXT: afi %r1, -536870912
+; BASELINE-NEXT: srl %r1, 31
+; BASELINE-NEXT: lr %r0, %r1
+; BASELINE-NEXT: .LBB1_3:
+; BASELINE-NEXT: llgfr %r0, %r0
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_subc_2:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r3), 3
+; Z13-NEXT: vl %v1, 0(%r4), 3
+; Z13-NEXT: vscbiq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
%cmp = icmp ule i128 %a, %b
%ext = zext i1 %cmp to i128
ret i128 %ext
}
define i128 @i128_addc_1(i128 %a, i128 %b) {
-; CHECK-LABEL: i128_addc_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vaccq %v0, %v1, %v0
-; CHECK-NEXT: vst %v0, 0(%r2), 3
-; CHECK-NEXT: br %r14
+; BASELINE-LABEL: i128_addc_1:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: lg %r0, 8(%r3)
+; BASELINE-NEXT: lg %r1, 0(%r3)
+; BASELINE-NEXT: alg %r0, 8(%r4)
+; BASELINE-NEXT: alcg %r1, 0(%r4)
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_addc_1:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r4), 3
+; Z13-NEXT: vl %v1, 0(%r3), 3
+; Z13-NEXT: vaccq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
%sum = add i128 %a, %b
%cmp = icmp ult i128 %sum, %a
%ext = zext i1 %cmp to i128
@@ -44,13 +112,25 @@ define i128 @i128_addc_1(i128 %a, i128 %b) {
}
define i128 @i128_addc_2(i128 %a, i128 %b) {
-; CHECK-LABEL: i128_addc_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vaccq %v0, %v1, %v0
-; CHECK-NEXT: vst %v0, 0(%r2), 3
-; CHECK-NEXT: br %r14
+; BASELINE-LABEL: i128_addc_2:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: lg %r0, 8(%r3)
+; BASELINE-NEXT: lg %r1, 0(%r3)
+; BASELINE-NEXT: alg %r0, 8(%r4)
+; BASELINE-NEXT: alcg %r1, 0(%r4)
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_addc_2:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r4), 3
+; Z13-NEXT: vl %v1, 0(%r3), 3
+; Z13-NEXT: vaccq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
%sum = add i128 %a, %b
%cmp = icmp ult i128 %sum, %b
%ext = zext i1 %cmp to i128
@@ -58,13 +138,25 @@ define i128 @i128_addc_2(i128 %a, i128 %b) {
}
define i128 @i128_addc_3(i128 %a, i128 %b) {
-; CHECK-LABEL: i128_addc_3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vaccq %v0, %v1, %v0
-; CHECK-NEXT: vst %v0, 0(%r2), 3
-; CHECK-NEXT: br %r14
+; BASELINE-LABEL: i128_addc_3:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: lg %r0, 8(%r3)
+; BASELINE-NEXT: lg %r1, 0(%r3)
+; BASELINE-NEXT: alg %r0, 8(%r4)
+; BASELINE-NEXT: alcg %r1, 0(%r4)
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_addc_3:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r4), 3
+; Z13-NEXT: vl %v1, 0(%r3), 3
+; Z13-NEXT: vaccq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
%sum = add i128 %a, %b
%cmp = icmp ugt i128 %a, %sum
%ext = zext i1 %cmp to i128
@@ -72,16 +164,97 @@ define i128 @i128_addc_3(i128 %a, i128 %b) {
}
define i128 @i128_addc_4(i128 %a, i128 %b) {
-; CHECK-LABEL: i128_addc_4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vaccq %v0, %v1, %v0
-; CHECK-NEXT: vst %v0, 0(%r2), 3
-; CHECK-NEXT: br %r14
+; BASELINE-LABEL: i128_addc_4:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: lg %r0, 8(%r3)
+; BASELINE-NEXT: lg %r1, 0(%r3)
+; BASELINE-NEXT: alg %r0, 8(%r4)
+; BASELINE-NEXT: alcg %r1, 0(%r4)
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_addc_4:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r4), 3
+; Z13-NEXT: vl %v1, 0(%r3), 3
+; Z13-NEXT: vaccq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
%sum = add i128 %a, %b
%cmp = icmp ugt i128 %b, %sum
%ext = zext i1 %cmp to i128
ret i128 %ext
}
+define i128 @i128_addc_xor(i128 %a, i128 %b) {
+; BASELINE-LABEL: i128_addc_xor:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: lg %r0, 8(%r4)
+; BASELINE-NEXT: lg %r1, 0(%r4)
+; BASELINE-NEXT: alg %r0, 8(%r3)
+; BASELINE-NEXT: alcg %r1, 0(%r3)
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_addc_xor:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v0, 0(%r3), 3
+; Z13-NEXT: vl %v1, 0(%r4), 3
+; Z13-NEXT: vaccq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
+ %b.not = xor i128 %b, -1
+ %cmp = icmp ugt i128 %a, %b.not
+ %ext = zext i1 %cmp to i128
+ ret i128 %ext
+}
+
+define i128 @i128_addc_xor_inv(i128 %a, i128 %b) {
+; BASELINE-LABEL: i128_addc_xor_inv:
+; BASELINE: # %bb.0:
+; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)
+; BASELINE-NEXT: .cfi_offset %r14, -48
+; BASELINE-NEXT: .cfi_offset %r15, -40
+; BASELINE-NEXT: lg %r5, 0(%r3)
+; BASELINE-NEXT: lghi %r14, -1
+; BASELINE-NEXT: xg %r14, 0(%r4)
+; BASELINE-NEXT: lghi %r1, -1
+; BASELINE-NEXT: xg %r1, 8(%r4)
+; BASELINE-NEXT: clgr %r5, %r14
+; BASELINE-NEXT: ipm %r0
+; BASELINE-NEXT: clg %r1, 8(%r3)
+; BASELINE-NEXT: ipm %r1
+; BASELINE-NEXT: cgrjlh %r5, %r14, .LBB7_2
+; BASELINE-NEXT: # %bb.1:
+; BASELINE-NEXT: xilf %r1, 4294967295
+; BASELINE-NEXT: risbg %r0, %r1, 63, 191, 36
+; BASELINE-NEXT: j .LBB7_3
+; BASELINE-NEXT: .LBB7_2:
+; BASELINE-NEXT: afi %r0, -536870912
+; BASELINE-NEXT: srl %r0, 31
+; BASELINE-NEXT: .LBB7_3:
+; BASELINE-NEXT: llgfr %r0, %r0
+; BASELINE-NEXT: stg %r0, 8(%r2)
+; BASELINE-NEXT: mvghi 0(%r2), 0
+; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)
+; BASELINE-NEXT: br %r14
+;
+; Z13-LABEL: i128_addc_xor_inv:
+; Z13: # %bb.0:
+; Z13-NEXT: vl %v1, 0(%r4), 3
+; Z13-NEXT: vl %v0, 0(%r3), 3
+; Z13-NEXT: vno %v1, %v1, %v1
+; Z13-NEXT: vscbiq %v0, %v1, %v0
+; Z13-NEXT: vst %v0, 0(%r2), 3
+; Z13-NEXT: br %r14
+ %b.not = xor i128 %b, -1
+ %cmp = icmp ule i128 %a, %b.not
+ %ext = zext i1 %cmp to i128
+ ret i128 %ext
+}
diff --git a/llvm/test/CodeGen/SystemZ/int-max-02.ll b/llvm/test/CodeGen/SystemZ/int-max-02.ll
index 5f5188c..00fd01a 100644
--- a/llvm/test/CodeGen/SystemZ/int-max-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-max-02.ll
@@ -7,8 +7,8 @@
define i128 @f1(i128 %val1, i128 %val2) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vmxq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -49,8 +49,8 @@ define i128 @f3(i128 %val1, i128 %val2) {
define i128 @f4(i128 %val1, i128 %val2) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vmxq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -63,8 +63,8 @@ define i128 @f4(i128 %val1, i128 %val2) {
define i128 @f5(i128 %val1, i128 %val2) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vmxlq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -105,8 +105,8 @@ define i128 @f7(i128 %val1, i128 %val2) {
define i128 @f8(i128 %val1, i128 %val2) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vmxlq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-min-02.ll b/llvm/test/CodeGen/SystemZ/int-min-02.ll
index 3066af9..f13db7c4 100644
--- a/llvm/test/CodeGen/SystemZ/int-min-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-min-02.ll
@@ -7,8 +7,8 @@
define i128 @f1(i128 %val1, i128 %val2) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vmnq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -49,8 +49,8 @@ define i128 @f3(i128 %val1, i128 %val2) {
define i128 @f4(i128 %val1, i128 %val2) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vmnq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -63,8 +63,8 @@ define i128 @f4(i128 %val1, i128 %val2) {
define i128 @f5(i128 %val1, i128 %val2) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vmnlq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -105,8 +105,8 @@ define i128 @f7(i128 %val1, i128 %val2) {
define i128 @f8(i128 %val1, i128 %val2) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vmnlq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/saturating-truncation.ll b/llvm/test/CodeGen/SystemZ/saturating-truncation.ll
new file mode 100644
index 0000000..0ea2920
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/saturating-truncation.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
+
+declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>) #2
+declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>) #2
+
+define <16 x i8> @i16_signed(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: i16_signed:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpksh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %1 = tail call <16 x i16> @llvm.smax.v16i16(<16 x i16> %0, <16 x i16> splat (i16 -128))
+ %2 = tail call <16 x i16> @llvm.smin.v16i16(<16 x i16> %1, <16 x i16> splat (i16 127))
+ %3 = trunc nsw <16 x i16> %2 to <16 x i8>
+ ret <16 x i8> %3
+ ret <16 x i8> %3
+}
+
+define <8 x i16> @i32_signed(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: i32_signed:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpksf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %1 = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> %0, <8 x i32> splat (i32 -32768))
+ %2 = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> %1, <8 x i32> splat (i32 32767))
+ %3 = trunc nsw <8 x i32> %2 to <8 x i16>
+ ret <8 x i16> %3
+}
+
+define <4 x i32> @i64_signed(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: i64_signed:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpksg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %1 = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> %0, <4 x i64> splat (i64 -2147483648))
+ %2 = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> %1, <4 x i64> splat (i64 2147483647))
+ %3 = trunc nsw <4 x i64> %2 to <4 x i32>
+ ret <4 x i32> %3
+}
+
+define <4 x i32> @i64_signed_flipped(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: i64_signed_flipped:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpksg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %1 = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> splat (i64 2147483647), <4 x i64> %0)
+ %2 = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> splat (i64 -2147483648), <4 x i64> %1)
+ %3 = trunc nsw <4 x i64> %2 to <4 x i32>
+ ret <4 x i32> %3
+}
+
+define <16 x i8> @i16_unsigned(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: i16_unsigned:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpklsh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %1 = tail call <16 x i16> @llvm.umin.v16i16(<16 x i16> %0, <16 x i16> splat (i16 255))
+ %2 = trunc nuw <16 x i16> %1 to <16 x i8>
+ ret <16 x i8> %2
+}
+
+define <8 x i16> @i32_unsigned(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: i32_unsigned:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpklsf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %1 = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> %0, <8 x i32> splat (i32 65535))
+ %2 = trunc nsw <8 x i32> %1 to <8 x i16>
+ ret <8 x i16> %2
+}
+
+define <4 x i32> @i64_unsigned(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: i64_unsigned:
+; CHECK: # %bb.0: # %bb2
+; CHECK-NEXT: vpklsg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
+bb2:
+ %0 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %1 = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> %0, <4 x i64> splat (i64 4294967295))
+ %2 = trunc nuw <4 x i64> %1 to <4 x i32>
+ ret <4 x i32> %2
+}
diff --git a/llvm/test/CodeGen/SystemZ/shift-17.ll b/llvm/test/CodeGen/SystemZ/shift-17.ll
index 45f4ed4..8f5f9ab 100644
--- a/llvm/test/CodeGen/SystemZ/shift-17.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-17.ll
@@ -249,3 +249,54 @@ define i128 @f8(i128 %a, i128 %b, i128 %sh) {
ret i128 %res
}
+; Funnel shift left by constant N in 121..128, in such cases fshl N == fshr (128 - N)
+define i128 @f9(i128 %a, i128 %b) {
+; CHECK-LABEL: f9:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepib %v2, 5
+; CHECK-NEXT: vsrl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 123
+; CHECK-NEXT: vslb %v0, %v0, %v2
+; CHECK-NEXT: vsl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v0, %v1
+; CHECK-NEXT: vst %v0, 0(%r2), 3
+; CHECK-NEXT: br %r14
+;
+; Z15-LABEL: f9:
+; Z15: # %bb.0:
+; Z15-NEXT: vl %v0, 0(%r4), 3
+; Z15-NEXT: vl %v1, 0(%r3), 3
+; Z15-NEXT: vsrd %v0, %v1, %v0, 5
+; Z15-NEXT: vst %v0, 0(%r2), 3
+; Z15-NEXT: br %r14
+ %res = tail call i128 @llvm.fshl.i128(i128 %a, i128 %b, i128 123)
+ ret i128 %res
+}
+
+; Funnel shift right by constant N in 121..128, in such cases fshr N == fshl (128 - N)
+define i128 @f10(i128 %a, i128 %b) {
+; CHECK-LABEL: f10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vrepib %v2, 5
+; CHECK-NEXT: vsl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 123
+; CHECK-NEXT: vsrlb %v0, %v0, %v2
+; CHECK-NEXT: vsrl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v1, %v0
+; CHECK-NEXT: vst %v0, 0(%r2), 3
+; CHECK-NEXT: br %r14
+;
+; Z15-LABEL: f10:
+; Z15: # %bb.0:
+; Z15-NEXT: vl %v0, 0(%r4), 3
+; Z15-NEXT: vl %v1, 0(%r3), 3
+; Z15-NEXT: vsld %v0, %v1, %v0, 5
+; Z15-NEXT: vst %v0, 0(%r2), 3
+; Z15-NEXT: br %r14
+ %res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %b, i128 123)
+ ret i128 %res
+}
generated by cgit v1.1 at 2025-09-02 18:13:30 +0000