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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rv64zbb.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rv64zbb.ll62
1 files changed, 31 insertions, 31 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index e640727..d133f9d 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -347,7 +347,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB6_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: negw a1, a0
+; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 6
; RV64I-NEXT: slli a2, a0, 8
@@ -355,16 +355,16 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a4, a0, 12
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: subw a3, a3, a4
+; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: subw a2, a2, a4
+; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: subw a4, a0, a4
+; RV64I-NEXT: sub a4, a0, a4
; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: slli a4, a0, 14
-; RV64I-NEXT: subw a3, a3, a4
+; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: subw a2, a2, a4
+; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a0, a0, 27
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a0, a2, a0
@@ -390,7 +390,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-LABEL: cttz_zero_undef_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: negw a1, a0
+; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 6
; RV64I-NEXT: slli a2, a0, 8
@@ -398,16 +398,16 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a4, a0, 12
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: subw a3, a3, a4
+; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: subw a2, a2, a4
+; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: subw a4, a0, a4
+; RV64I-NEXT: sub a4, a0, a4
; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: slli a4, a0, 14
-; RV64I-NEXT: subw a3, a3, a4
+; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: subw a2, a2, a4
+; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a0, a0, 27
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a0, a2, a0
@@ -430,7 +430,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-LABEL: findFirstSet_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: negw a1, a0
+; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a1, 6
; RV64I-NEXT: slli a3, a1, 8
@@ -438,16 +438,16 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a5, a1, 12
; RV64I-NEXT: add a2, a2, a3
; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: subw a4, a4, a5
+; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: subw a3, a3, a5
+; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: subw a5, a1, a5
+; RV64I-NEXT: sub a5, a1, a5
; RV64I-NEXT: add a2, a5, a2
; RV64I-NEXT: slli a5, a1, 14
-; RV64I-NEXT: subw a4, a4, a5
+; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
-; RV64I-NEXT: subw a3, a3, a5
+; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: add a1, a3, a1
@@ -478,7 +478,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-LABEL: ffs_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: negw a1, a0
+; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a1, 6
; RV64I-NEXT: slli a3, a1, 8
@@ -486,16 +486,16 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a5, a1, 12
; RV64I-NEXT: add a2, a2, a3
; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: subw a4, a4, a5
+; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: subw a3, a3, a5
+; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: subw a5, a1, a5
+; RV64I-NEXT: sub a5, a1, a5
; RV64I-NEXT: add a2, a5, a2
; RV64I-NEXT: slli a5, a1, 14
-; RV64I-NEXT: subw a4, a4, a5
+; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
-; RV64I-NEXT: subw a3, a3, a5
+; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: lui a4, %hi(.LCPI9_0)
; RV64I-NEXT: addi a4, a4, %lo(.LCPI9_0)
@@ -701,7 +701,7 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind {
;
; RV64ZBB-LABEL: ctpop_i32_load:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: lwu a0, 0(a0)
+; RV64ZBB-NEXT: lw a0, 0(a0)
; RV64ZBB-NEXT: cpopw a0, a0
; RV64ZBB-NEXT: ret
%a = load i32, ptr %p
@@ -1741,7 +1741,7 @@ define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
; RV64ZBB-LABEL: sub_if_uge_i8:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.b a2, a0
-; RV64ZBB-NEXT: subw a0, a0, a1
+; RV64ZBB-NEXT: sub a0, a0, a1
; RV64ZBB-NEXT: zext.b a0, a0
; RV64ZBB-NEXT: minu a0, a2, a0
; RV64ZBB-NEXT: ret
@@ -1767,7 +1767,7 @@ define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
; RV64ZBB-LABEL: sub_if_uge_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a2, a0
-; RV64ZBB-NEXT: subw a0, a0, a1
+; RV64ZBB-NEXT: sub a0, a0, a1
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: minu a0, a2, a0
; RV64ZBB-NEXT: ret
@@ -1852,7 +1852,7 @@ define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
; CHECK-NEXT: sltu a2, a3, a2
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a1, a2, a1
-; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: sllw a0, a0, a1
; CHECK-NEXT: ret
%cmp = icmp ult i32 %x, %y
@@ -1870,7 +1870,7 @@ define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
; RV64I-NEXT: sltu a4, a3, a2
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: and a1, a4, a1
-; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: bltu a3, a2, .LBB68_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a1, 4
@@ -1980,7 +1980,7 @@ define i32 @sub_if_uge_C_i32(i32 signext %x) {
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: addi a1, a1, -16
; RV64I-NEXT: sltu a1, a1, a0
-; RV64I-NEXT: negw a1, a1
+; RV64I-NEXT: neg a1, a1
; RV64I-NEXT: addi a2, a2, 15
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: addw a0, a0, a1
@@ -2036,7 +2036,7 @@ define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
; RV64I-NEXT: lui a3, 1048560
; RV64I-NEXT: addi a2, a2, -16
; RV64I-NEXT: sltu a2, a2, a0
-; RV64I-NEXT: negw a4, a2
+; RV64I-NEXT: neg a4, a2
; RV64I-NEXT: addi a3, a3, 15
; RV64I-NEXT: and a3, a4, a3
; RV64I-NEXT: addw a0, a0, a3
generated by cgit v1.1 at 2025-08-02 04:15:08 +0000