diff options
Diffstat (limited to 'llvm/test/CodeGen/MIR')
6 files changed, 206 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir b/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir new file mode 100644 index 0000000..4179ff2 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: not llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s + +--- | + define void @expect_id(ptr %ptr, float %data) #0 { + %1 = atomicrmw fadd ptr %ptr, float %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !0 + ret void + } + + attributes #0 = { "target-cpu"="gfx1200" } + + !0 = !{i32 5, i32 6} +... + +--- +name: expect_id + +body: | + bb.1 (%ir-block.0): + liveins: $vgpr0, $vgpr1, $vgpr2 + + ; CHECK: expected metadata id after '!' + %2:vgpr_32 = COPY $vgpr0 + %3:vgpr_32 = COPY $vgpr1 + %0:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1 + %1:vgpr_32 = COPY $vgpr2 + FLAT_ATOMIC_ADD_F32 %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !!) + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir b/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir new file mode 100644 index 0000000..7fe6aa9 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -o - %s | FileCheck %s + + +--- | + define void @test_parsing_printing(ptr %ptr, float %data) { + %1 = atomicrmw fadd ptr %ptr, float %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !0 + ret void + } + + !0 = !{i32 5, i32 6} +... + +--- +name: test_parsing_printing + +body: | + bb.1 (%ir-block.0): + liveins: $vgpr0, $vgpr1, $vgpr2 + + ; CHECK-LABEL: name: test_parsing_printing + ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-NEXT: FLAT_ATOMIC_ADD_F32 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !0) + ; CHECK-NEXT: S_ENDPGM 0 + %2:vgpr_32 = COPY $vgpr0 + %3:vgpr_32 = COPY $vgpr1 + %0:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1 + %1:vgpr_32 = COPY $vgpr2 + FLAT_ATOMIC_ADD_F32 %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !0) + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir b/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir new file mode 100644 index 0000000..505b514 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: not llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s + + +--- | + define void @undefined_metadata(ptr %ptr, float %data) { + %1 = atomicrmw fadd ptr %ptr, float %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !0 + ret void + } + + !0 = !{i32 5, i32 6} +... + +--- +name: undefined_metadata + +body: | + bb.1 (%ir-block.0): + liveins: $vgpr0, $vgpr1, $vgpr2 + + ; CHECK: use of undefined metadata '!3' + %2:vgpr_32 = COPY $vgpr0 + %3:vgpr_32 = COPY $vgpr1 + %0:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1 + %1:vgpr_32 = COPY $vgpr2 + FLAT_ATOMIC_ADD_F32 %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !3) + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir new file mode 100644 index 0000000..cb78898 --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir @@ -0,0 +1,31 @@ +# Test MIR printer and parser to check if a call instruction with multiple +# callee types are handled correctly. + +# RUN: llc -mtriple=x86_64 --call-graph-section %s -run-pass=none -o - | FileCheck --match-full-lines %s +# CHECK: name: ambiguous_caller +# CHECK: callSites: +# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: {{.*}}, calleeTypeIds: +# CHECK-NEXT: [ 1234, 5678 ] } + +--- | + define ptr @ambiguous_caller() { + entry: + %fn = alloca ptr, align 8 + %call1 = call ptr %fn(i64 4), !callee_type !0 + ret ptr %call1 + } + + !0 = !{!1, !2} + !1 = !{i64 0, !"callee_type0.generalized"} + !2 = !{i64 0, !"callee_type2.generalized"} +... +--- +name: ambiguous_caller +callSites: + - { bb: 0, offset: 1, fwdArgRegs: [], calleeTypeIds: [ 1234, 5678 ] } +body: | + bb.0.entry: + %0:gr64 = MOV32ri64 4 + CALL64r killed %0, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax + RET 0, $rax +... diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir new file mode 100644 index 0000000..faa021c --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir @@ -0,0 +1,54 @@ +# Test MIR printer and parser to NOT have `CalleeTypeIds` field in callSites. +# `CalleeTypeId` is used for propagating call site type identifiers for +# indirect targets only. This test does not contain any indirect targets. + +# RUN: llc -mtriple=x86_64 --call-graph-section %s -run-pass=none -o - | FileCheck --match-full-lines %s +# CHECK-NOT: calleeTypeIds +# CHECK: name: bar +# CHECK: callSites: +# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [] } +# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [] } +# CHECK: name: foo +# CHECK: callSites: +# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [] } + +--- | + declare i32 @fizz(i32, i32) + + declare i32 @buzz(i32, i32) + + define i32 @bar(i32 %x, i32 %y) !type !0 { + entry: + %call = call i32 @buzz(i32 %x, i32 %x) + %call1 = call i32 @fizz(i32 %x, i32 %x) + ret i32 0 + } + + define i32 @foo(i32 %x, i32 %y) !type !0 { + entry: + %call1 = call i32 @bar(i32 %x, i32 %x) + ret i32 0 + } + + !0 = !{i64 0, !"_ZTSFiiiE.generalized"} +... +--- +name: bar +callSites: + - { bb: 0, offset: 0, fwdArgRegs: [] } + - { bb: 0, offset: 1, fwdArgRegs: [] } +body: | + bb.0.entry: + CALL64pcrel32 target-flags(x86-plt) @buzz, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax + CALL64pcrel32 target-flags(x86-plt) @fizz, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax + +... +--- +name: foo +callSites: + - { bb: 0, offset: 0, fwdArgRegs: [] } +body: | + bb.0.entry: + CALL64pcrel32 target-flags(x86-plt) @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax + +... diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir new file mode 100644 index 0000000..303b8fa --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir @@ -0,0 +1,28 @@ +# Test MIR printer and parser for type id field in callSites. It is used +# for propagating call site type identifiers to emit in the call graph section. + +# RUN: llc -mtriple=x86_64 --call-graph-section %s -run-pass=none -o - | FileCheck --match-full-lines %s +# CHECK: name: call_foo +# CHECK: callSites: +# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], calleeTypeIds: +# CHECK-NEXT: [ 123456789 ] } + +--- | + define i32 @call_foo() { + entry: + %0 = load ptr, ptr null, align 8 + call void %0(i8 0), !callee_type !0 + ret i32 0 + } + + !0 = !{!1} + !1 = !{i64 0, !"_ZTSFvcE.generalized"} +... +--- +name: call_foo +callSites: + - { bb: 0, offset: 0, fwdArgRegs: [], calleeTypeIds: [ 123456789 ] } +body: | + bb.0.entry: + CALL64m $noreg, 1, $noreg, 0, $noreg, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp :: (load (s64) from `ptr null`) +... |