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-rw-r--r--llvm/test/CodeGen/DirectX/Binding/binding-overlap-7.ll35
-rw-r--r--llvm/test/CodeGen/DirectX/imad.ll102
-rw-r--r--llvm/test/CodeGen/DirectX/umad.ll102
3 files changed, 227 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/DirectX/Binding/binding-overlap-7.ll b/llvm/test/CodeGen/DirectX/Binding/binding-overlap-7.ll
new file mode 100644
index 0000000..25f81dd
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/Binding/binding-overlap-7.ll
@@ -0,0 +1,35 @@
+; Use llc for this test so that we don't abort after the first error.
+; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s
+
+; Check that there is no overlap with unbounded array in different space
+
+ ; Buffer<double> A[2] : register(t2, space4);
+ ; Buffer<double> B : register(t20, space5); // does not overlap
+ ; Buffer<double> C[] : register(t2, space4); // overlaps with A
+
+; CHECK: error: resource A at register 2 overlaps with resource C at register 2 in space 4
+; CHECK-NOT: error: resource C at register 2 overlaps with resource B at register 20 in space 5
+
+target triple = "dxil-pc-shadermodel6.3-library"
+
+@A.str = private unnamed_addr constant [2 x i8] c"A\00", align 1
+@B.str = private unnamed_addr constant [2 x i8] c"B\00", align 1
+@C.str = private unnamed_addr constant [2 x i8] c"C\00", align 1
+
+define void @test_not_overlapping_in_different_spaces() {
+entry:
+
+ ; Buffer<double> A[2] : register(t2, space4);
+ %h0 = call target("dx.TypedBuffer", double, 0, 0, 0)
+ @llvm.dx.resource.handlefrombinding(i32 4, i32 2, i32 2, i32 10, i1 false, ptr @A.str)
+
+ ; Buffer<double> B : register(t20, space5);
+ %h1 = call target("dx.TypedBuffer", i64, 0, 0, 0)
+ @llvm.dx.resource.handlefrombinding(i32 5, i32 20, i32 1, i32 0, i1 false, ptr @B.str)
+
+ ; Buffer<double> C[] : register(t2, space4);
+ %h2 = call target("dx.TypedBuffer", double, 0, 0, 0)
+ @llvm.dx.resource.handlefrombinding(i32 4, i32 2, i32 -1, i32 10, i1 false, ptr @C.str)
+
+ ret void
+}
diff --git a/llvm/test/CodeGen/DirectX/imad.ll b/llvm/test/CodeGen/DirectX/imad.ll
index 5d9463d..2e612f0 100644
--- a/llvm/test/CodeGen/DirectX/imad.ll
+++ b/llvm/test/CodeGen/DirectX/imad.ll
@@ -1,17 +1,13 @@
-; RUN: opt -S -dxil-op-lower < %s | FileCheck %s
+; RUN: opt -S -scalarizer -dxil-op-lower < %s | FileCheck %s
; Make sure dxil operation function calls for round are generated for float and half.
-; CHECK:call i16 @dx.op.tertiary.i16(i32 48, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR:]]
-; CHECK:call i32 @dx.op.tertiary.i32(i32 48, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
-; CHECK:call i64 @dx.op.tertiary.i64(i32 48, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
-
-; CHECK: attributes #[[#ATTR]] = {{{.*}} memory(none) {{.*}}}
target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"
target triple = "dxil-pc-shadermodel6.7-library"
; Function Attrs: noinline nounwind optnone
define noundef i16 @imad_short(i16 noundef %p0, i16 noundef %p1, i16 noundef %p2) #0 {
entry:
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 48, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR:]]
%p2.addr = alloca i16, align 2
%p1.addr = alloca i16, align 2
%p0.addr = alloca i16, align 2
@@ -31,6 +27,7 @@ declare i16 @llvm.dx.imad.i16(i16, i16, i16) #1
; Function Attrs: noinline nounwind optnone
define noundef i32 @imad_int(i32 noundef %p0, i32 noundef %p1, i32 noundef %p2) #0 {
entry:
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 48, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
%p2.addr = alloca i32, align 4
%p1.addr = alloca i32, align 4
%p0.addr = alloca i32, align 4
@@ -50,6 +47,7 @@ declare i32 @llvm.dx.imad.i32(i32, i32, i32) #1
; Function Attrs: noinline nounwind optnone
define noundef i64 @imad_int64(i64 noundef %p0, i64 noundef %p1, i64 noundef %p2) #0 {
entry:
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 48, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
%p2.addr = alloca i64, align 8
%p1.addr = alloca i64, align 8
%p0.addr = alloca i64, align 8
@@ -65,3 +63,95 @@ entry:
; Function Attrs: nocallback nofree nosync nounwind willreturn
declare i64 @llvm.dx.imad.i64(i64, i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define noundef <4 x i16> @imad_int16_t4(<4 x i16> noundef %p0, <4 x i16> noundef %p1, <4 x i16> noundef %p2) #0 {
+entry:
+ ; CHECK: extractelement <4 x i16> %p0, i64 0
+ ; CHECK: extractelement <4 x i16> %p1, i64 0
+ ; CHECK: extractelement <4 x i16> %p2, i64 0
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 48, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i16> %p0, i64 1
+ ; CHECK: extractelement <4 x i16> %p1, i64 1
+ ; CHECK: extractelement <4 x i16> %p2, i64 1
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 48, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i16> %p0, i64 2
+ ; CHECK: extractelement <4 x i16> %p1, i64 2
+ ; CHECK: extractelement <4 x i16> %p2, i64 2
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 48, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i16> %p0, i64 3
+ ; CHECK: extractelement <4 x i16> %p1, i64 3
+ ; CHECK: extractelement <4 x i16> %p2, i64 3
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 48, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: insertelement <4 x i16> poison, i16 %{{.*}}, i64 0
+ ; CHECK: insertelement <4 x i16> %{{.*}}, i16 %{{.*}}, i64 1
+ ; CHECK: insertelement <4 x i16> %{{.*}}, i16 %{{.*}}, i64 2
+ ; CHECK: insertelement <4 x i16> %{{.*}}, i16 %{{.*}}, i64 3
+ %dx.imad = call <4 x i16> @llvm.dx.imad.v4i16(<4 x i16> %p0, <4 x i16> %p1, <4 x i16> %p2)
+ ret <4 x i16> %dx.imad
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn
+declare <4 x i16> @llvm.dx.imad.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) #1
+
+; Function Attrs: noinline nounwind optnone
+define noundef <4 x i32> @imad_int4(<4 x i32> noundef %p0, <4 x i32> noundef %p1, <4 x i32> noundef %p2) #0 {
+entry:
+ ; CHECK: extractelement <4 x i32> %p0, i64 0
+ ; CHECK: extractelement <4 x i32> %p1, i64 0
+ ; CHECK: extractelement <4 x i32> %p2, i64 0
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 48, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i32> %p0, i64 1
+ ; CHECK: extractelement <4 x i32> %p1, i64 1
+ ; CHECK: extractelement <4 x i32> %p2, i64 1
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 48, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i32> %p0, i64 2
+ ; CHECK: extractelement <4 x i32> %p1, i64 2
+ ; CHECK: extractelement <4 x i32> %p2, i64 2
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 48, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i32> %p0, i64 3
+ ; CHECK: extractelement <4 x i32> %p1, i64 3
+ ; CHECK: extractelement <4 x i32> %p2, i64 3
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 48, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: insertelement <4 x i32> poison, i32 %{{.*}}, i64 0
+ ; CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i64 1
+ ; CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i64 2
+ ; CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i64 3
+ %dx.imad = call <4 x i32> @llvm.dx.imad.v4i32(<4 x i32> %p0, <4 x i32> %p1, <4 x i32> %p2)
+ ret <4 x i32> %dx.imad
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn
+declare <4 x i32> @llvm.dx.imad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
+
+; Function Attrs: noinline nounwind optnone
+define noundef <4 x i64> @imad_int64_t4(<4 x i64> noundef %p0, <4 x i64> noundef %p1, <4 x i64> noundef %p2) #0 {
+entry:
+ ; CHECK: extractelement <4 x i64> %p0, i64 0
+ ; CHECK: extractelement <4 x i64> %p1, i64 0
+ ; CHECK: extractelement <4 x i64> %p2, i64 0
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 48, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i64> %p0, i64 1
+ ; CHECK: extractelement <4 x i64> %p1, i64 1
+ ; CHECK: extractelement <4 x i64> %p2, i64 1
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 48, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i64> %p0, i64 2
+ ; CHECK: extractelement <4 x i64> %p1, i64 2
+ ; CHECK: extractelement <4 x i64> %p2, i64 2
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 48, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i64> %p0, i64 3
+ ; CHECK: extractelement <4 x i64> %p1, i64 3
+ ; CHECK: extractelement <4 x i64> %p2, i64 3
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 48, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: insertelement <4 x i64> poison, i64 %{{.*}}, i64 0
+ ; CHECK: insertelement <4 x i64> %{{.*}}, i64 %{{.*}}, i64 1
+ ; CHECK: insertelement <4 x i64> %{{.*}}, i64 %{{.*}}, i64 2
+ ; CHECK: insertelement <4 x i64> %{{.*}}, i64 %{{.*}}, i64 3
+ %dx.imad = call <4 x i64> @llvm.dx.imad.v4i64(<4 x i64> %p0, <4 x i64> %p1, <4 x i64> %p2)
+ ret <4 x i64> %dx.imad
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn
+declare <4 x i64> @llvm.dx.imad.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) #1
+
+; CHECK: attributes #[[#ATTR]] = {{{.*}} memory(none) {{.*}}}
diff --git a/llvm/test/CodeGen/DirectX/umad.ll b/llvm/test/CodeGen/DirectX/umad.ll
index 104d238..76516a2 100644
--- a/llvm/test/CodeGen/DirectX/umad.ll
+++ b/llvm/test/CodeGen/DirectX/umad.ll
@@ -1,17 +1,13 @@
-; RUN: opt -S -dxil-op-lower < %s | FileCheck %s
+; RUN: opt -S -scalarizer -dxil-op-lower < %s | FileCheck %s
; Make sure dxil operation function calls for round are generated for float and half.
-; CHECK:call i16 @dx.op.tertiary.i16(i32 49, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR:]]
-; CHECK:call i32 @dx.op.tertiary.i32(i32 49, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
-; CHECK:call i64 @dx.op.tertiary.i64(i32 49, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
-
-; CHECK: attributes #[[#ATTR]] = {{{.*}} memory(none) {{.*}}}
target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"
target triple = "dxil-pc-shadermodel6.7-library"
; Function Attrs: noinline nounwind optnone
define noundef i16 @umad_ushort(i16 noundef %p0, i16 noundef %p1, i16 noundef %p2) #0 {
entry:
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 49, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR:]]
%p2.addr = alloca i16, align 2
%p1.addr = alloca i16, align 2
%p0.addr = alloca i16, align 2
@@ -31,6 +27,7 @@ declare i16 @llvm.dx.umad.i16(i16, i16, i16) #1
; Function Attrs: noinline nounwind optnone
define noundef i32 @umad_uint(i32 noundef %p0, i32 noundef %p1, i32 noundef %p2) #0 {
entry:
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 49, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
%p2.addr = alloca i32, align 4
%p1.addr = alloca i32, align 4
%p0.addr = alloca i32, align 4
@@ -50,6 +47,7 @@ declare i32 @llvm.dx.umad.i32(i32, i32, i32) #1
; Function Attrs: noinline nounwind optnone
define noundef i64 @umad_uint64(i64 noundef %p0, i64 noundef %p1, i64 noundef %p2) #0 {
entry:
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 49, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
%p2.addr = alloca i64, align 8
%p1.addr = alloca i64, align 8
%p0.addr = alloca i64, align 8
@@ -65,3 +63,95 @@ entry:
; Function Attrs: nocallback nofree nosync nounwind willreturn
declare i64 @llvm.dx.umad.i64(i64, i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define noundef <4 x i16> @umad_uint16_t4(<4 x i16> noundef %p0, <4 x i16> noundef %p1, <4 x i16> noundef %p2) #0 {
+entry:
+ ; CHECK: extractelement <4 x i16> %p0, i64 0
+ ; CHECK: extractelement <4 x i16> %p1, i64 0
+ ; CHECK: extractelement <4 x i16> %p2, i64 0
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 49, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i16> %p0, i64 1
+ ; CHECK: extractelement <4 x i16> %p1, i64 1
+ ; CHECK: extractelement <4 x i16> %p2, i64 1
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 49, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i16> %p0, i64 2
+ ; CHECK: extractelement <4 x i16> %p1, i64 2
+ ; CHECK: extractelement <4 x i16> %p2, i64 2
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 49, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i16> %p0, i64 3
+ ; CHECK: extractelement <4 x i16> %p1, i64 3
+ ; CHECK: extractelement <4 x i16> %p2, i64 3
+ ; CHECK: call i16 @dx.op.tertiary.i16(i32 49, i16 %{{.*}}, i16 %{{.*}}, i16 %{{.*}}) #[[#ATTR]]
+ ; CHECK: insertelement <4 x i16> poison, i16 %{{.*}}, i64 0
+ ; CHECK: insertelement <4 x i16> %{{.*}}, i16 %{{.*}}, i64 1
+ ; CHECK: insertelement <4 x i16> %{{.*}}, i16 %{{.*}}, i64 2
+ ; CHECK: insertelement <4 x i16> %{{.*}}, i16 %{{.*}}, i64 3
+ %dx.umad = call <4 x i16> @llvm.dx.umad.v4i16(<4 x i16> %p0, <4 x i16> %p1, <4 x i16> %p2)
+ ret <4 x i16> %dx.umad
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn
+declare <4 x i16> @llvm.dx.umad.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) #1
+
+; Function Attrs: noinline nounwind optnone
+define noundef <4 x i32> @umad_uint4(<4 x i32> noundef %p0, <4 x i32> noundef %p1, <4 x i32> noundef %p2) #0 {
+entry:
+ ; CHECK: extractelement <4 x i32> %p0, i64 0
+ ; CHECK: extractelement <4 x i32> %p1, i64 0
+ ; CHECK: extractelement <4 x i32> %p2, i64 0
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 49, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i32> %p0, i64 1
+ ; CHECK: extractelement <4 x i32> %p1, i64 1
+ ; CHECK: extractelement <4 x i32> %p2, i64 1
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 49, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i32> %p0, i64 2
+ ; CHECK: extractelement <4 x i32> %p1, i64 2
+ ; CHECK: extractelement <4 x i32> %p2, i64 2
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 49, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i32> %p0, i64 3
+ ; CHECK: extractelement <4 x i32> %p1, i64 3
+ ; CHECK: extractelement <4 x i32> %p2, i64 3
+ ; CHECK: call i32 @dx.op.tertiary.i32(i32 49, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) #[[#ATTR]]
+ ; CHECK: insertelement <4 x i32> poison, i32 %{{.*}}, i64 0
+ ; CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i64 1
+ ; CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i64 2
+ ; CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i64 3
+ %dx.umad = call <4 x i32> @llvm.dx.umad.v4i32(<4 x i32> %p0, <4 x i32> %p1, <4 x i32> %p2)
+ ret <4 x i32> %dx.umad
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn
+declare <4 x i32> @llvm.dx.umad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
+
+; Function Attrs: noinline nounwind optnone
+define noundef <4 x i64> @umad_uint64_t4(<4 x i64> noundef %p0, <4 x i64> noundef %p1, <4 x i64> noundef %p2) #0 {
+entry:
+ ; CHECK: extractelement <4 x i64> %p0, i64 0
+ ; CHECK: extractelement <4 x i64> %p1, i64 0
+ ; CHECK: extractelement <4 x i64> %p2, i64 0
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 49, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i64> %p0, i64 1
+ ; CHECK: extractelement <4 x i64> %p1, i64 1
+ ; CHECK: extractelement <4 x i64> %p2, i64 1
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 49, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i64> %p0, i64 2
+ ; CHECK: extractelement <4 x i64> %p1, i64 2
+ ; CHECK: extractelement <4 x i64> %p2, i64 2
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 49, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: extractelement <4 x i64> %p0, i64 3
+ ; CHECK: extractelement <4 x i64> %p1, i64 3
+ ; CHECK: extractelement <4 x i64> %p2, i64 3
+ ; CHECK: call i64 @dx.op.tertiary.i64(i32 49, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}) #[[#ATTR]]
+ ; CHECK: insertelement <4 x i64> poison, i64 %{{.*}}, i64 0
+ ; CHECK: insertelement <4 x i64> %{{.*}}, i64 %{{.*}}, i64 1
+ ; CHECK: insertelement <4 x i64> %{{.*}}, i64 %{{.*}}, i64 2
+ ; CHECK: insertelement <4 x i64> %{{.*}}, i64 %{{.*}}, i64 3
+ %dx.umad = call <4 x i64> @llvm.dx.umad.v4i64(<4 x i64> %p0, <4 x i64> %p1, <4 x i64> %p2)
+ ret <4 x i64> %dx.umad
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn
+declare <4 x i64> @llvm.dx.umad.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) #1
+
+; CHECK: attributes #[[#ATTR]] = {{{.*}} memory(none) {{.*}}}
generated by cgit v1.1 at 2025-08-08 03:32:23 +0000