diff options
Diffstat (limited to 'llvm/test/CodeGen/DirectX')
9 files changed, 281 insertions, 20 deletions
diff --git a/llvm/test/CodeGen/DirectX/Binding/binding-overlap-6.ll b/llvm/test/CodeGen/DirectX/Binding/binding-overlap-6.ll new file mode 100644 index 0000000..3c37e63 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/Binding/binding-overlap-6.ll @@ -0,0 +1,24 @@ +; RUN: not opt -S -passes='dxil-post-optimization-validation' -mtriple=dxil-pc-shadermodel6.3-library %s 2>&1 | FileCheck %s + +; Check overlap with unbounded array + +; A overlaps with B +; RWBuffer<float> A[3] : register(u0); +; RWBuffer<float> B[] : register(u4); +; RWBuffer<float> C : register(u17); + +; CHECK: error: resource B at register 4 overlaps with resource C at register 17 in space 0 + +target triple = "dxil-pc-shadermodel6.3-library" + +@A.str = private unnamed_addr constant [2 x i8] c"A\00", align 1 +@B.str = private unnamed_addr constant [2 x i8] c"B\00", align 1 +@C.str = private unnamed_addr constant [2 x i8] c"C\00", align 1 + +define void @test_overlapping() { +entry: + %h1 = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 3, i32 0, i1 false, ptr @A.str) + %h2 = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 4, i32 -1, i32 0, i1 false, ptr @B.str) + %h3 = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 17, i32 1, i32 0, i1 false, ptr @C.str) + ret void +} diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/lifetimes-noint64op.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/lifetimes-noint64op.ll new file mode 100644 index 0000000..736c86e --- /dev/null +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/lifetimes-noint64op.ll @@ -0,0 +1,36 @@ +; RUN: opt -S --passes="print-dx-shader-flags" 2>&1 %s | FileCheck %s +; RUN: llc %s --filetype=obj -o - | obj2yaml | FileCheck %s --check-prefix=DXC + +target triple = "dxil-pc-shadermodel6.7-library" + +; CHECK: ; Combined Shader Flags for Module +; CHECK-NEXT: ; Shader Flags Value: 0x00000000 +; CHECK-NEXT: ; +; CHECK-NOT: ; Note: shader requires additional functionality: +; CHECK-NOT: ; 64-Bit integer +; CHECK-NOT: ; Note: extra DXIL module flags: +; CHECK-NOT: ; +; CHECK-NEXT: ; Shader Flags for Module Functions +; CHECK-NEXT: ; Function lifetimes : 0x00000000 + +define void @lifetimes() #0 { + %a = alloca [4 x i32], align 8 + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %a) + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %a) + ret void +} + +; Function Attrs: nounwind memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64, ptr) #1 + +; Function Attrs: nounwind memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64, ptr) #1 + +attributes #0 = { convergent norecurse nounwind "hlsl.export"} +attributes #1 = { nounwind memory(argmem: readwrite) } + +; DXC: - Name: SFI0 +; DXC-NEXT: Size: 8 +; DXC-NOT: Flags: +; DXC-NOT: Int64Ops: true +; DXC: ... diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-doubles.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-doubles.ll new file mode 100644 index 0000000..5e44b93 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-doubles.ll @@ -0,0 +1,37 @@ +; RUN: opt -S --passes="print-dx-shader-flags" 2>&1 %s | FileCheck %s +; RUN: llc %s --filetype=obj -o - | obj2yaml | FileCheck %s --check-prefix=DXC + +target triple = "dxil-pc-shadermodel6.7-library" + +; CHECK: ; Combined Shader Flags for Module +; CHECK-NEXT: ; Shader Flags Value: 0x00000014 +; CHECK-NEXT: ; +; CHECK-NEXT: ; Note: shader requires additional functionality: +; CHECK-NEXT: ; Double-precision floating point +; CHECK-NEXT: ; Note: extra DXIL module flags: +; CHECK-NEXT: ; Raw and structured buffers +; CHECK-NEXT: ; +; CHECK-NEXT: ; Shader Flags for Module Functions + +; CHECK: Function rawbuf : 0x00000014 +define void @rawbuf() "hlsl.export" { + %rb = tail call target("dx.RawBuffer", <4 x double>, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f16_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null) + %load = call { <4 x double>, i1 } + @llvm.dx.resource.load.rawbuffer.v4double.tdx.RawBuffer_v4f16_0_0t(target("dx.RawBuffer", <4 x double>, 0, 0) %rb, i32 0, i32 0) + %extract = extractvalue { <4 x double>, i1 } %load, 0 + ret void +} + +; Metadata to avoid adding flags not currently of interest to this test +!dx.valver = !{!0} +!0 = !{i32 1, i32 8} +!llvm.module.flags = !{!1} +!1 = !{i32 1, !"dx.resmayalias", i32 1} + +; DXC: - Name: SFI0 +; DXC-NEXT: Size: 8 +; DXC-NEXT: Flags: +; DXC-NEXT: Doubles: true +; DXC: ... + diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-int64.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-int64.ll new file mode 100644 index 0000000..517147a --- /dev/null +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-int64.ll @@ -0,0 +1,36 @@ +; RUN: opt -S --passes="print-dx-shader-flags" 2>&1 %s | FileCheck %s +; RUN: llc %s --filetype=obj -o - | obj2yaml | FileCheck %s --check-prefix=DXC + +target triple = "dxil-pc-shadermodel6.7-library" + +; CHECK: ; Combined Shader Flags for Module +; CHECK-NEXT: ; Shader Flags Value: 0x00100010 +; CHECK-NEXT: ; +; CHECK-NEXT: ; Note: shader requires additional functionality: +; CHECK-NEXT: ; 64-Bit integer +; CHECK-NEXT: ; Note: extra DXIL module flags: +; CHECK-NEXT: ; Raw and structured buffers +; CHECK-NEXT: ; +; CHECK-NEXT: ; Shader Flags for Module Functions + +; CHECK: Function rawbuf : 0x00100010 +define void @rawbuf() "hlsl.export" { + %rb = tail call target("dx.RawBuffer", <4 x i64>, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f16_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null) + %load = call { <4 x i64>, i1 } + @llvm.dx.resource.load.rawbuffer.v4i64.tdx.RawBuffer_v4f16_0_0t(target("dx.RawBuffer", <4 x i64>, 0, 0) %rb, i32 0, i32 0) + %extract = extractvalue { <4 x i64>, i1 } %load, 0 + ret void +} + +; Metadata to avoid adding flags not currently of interest to this test +!dx.valver = !{!0} +!0 = !{i32 1, i32 8} +!llvm.module.flags = !{!1} +!1 = !{i32 1, !"dx.resmayalias", i32 1} + +; DXC: - Name: SFI0 +; DXC-NEXT: Size: 8 +; DXC-NEXT: Flags: +; DXC: Int64Ops: true +; DXC: ... diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-low-precision.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-low-precision.ll new file mode 100644 index 0000000..cb4a3e9 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/rawbuffer-low-precision.ll @@ -0,0 +1,44 @@ +; RUN: opt -S --passes="print-dx-shader-flags" 2>&1 %s | FileCheck %s +; RUN: llc %s --filetype=obj -o - | obj2yaml | FileCheck %s --check-prefix=DXC + +target triple = "dxil-pc-shadermodel6.7-library" + +; CHECK: ; Combined Shader Flags for Module +; CHECK-NEXT: ; Shader Flags Value: 0x00800030 +; CHECK-NEXT: ; +; CHECK-NEXT: ; Note: shader requires additional functionality: +; CHECK-NEXT: ; Native low-precision data types +; CHECK-NEXT: ; Note: extra DXIL module flags: +; CHECK-NEXT: ; Raw and structured buffers +; CHECK-NEXT: ; Low-precision data types present +; CHECK-NEXT: ; Enable native low-precision data types +; CHECK-NEXT: ; +; CHECK-NEXT: ; Shader Flags for Module Functions + +; CHECK: Function rawbuf : 0x00800030 +define void @rawbuf() "hlsl.export" { + %halfrb = tail call target("dx.RawBuffer", <4 x half>, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f16_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null) + %i16rb = tail call target("dx.RawBuffer", <4 x i16>, 1, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4i16_1_0t(i32 0, i32 1, i32 1, i32 0, i1 false, ptr null) + %loadhalfrb = call { <4 x i16>, i1 } + @llvm.dx.resource.load.rawbuffer.v4i16.tdx.RawBuffer_v4f16_0_0t(target("dx.RawBuffer", <4 x half>, 0, 0) %halfrb, i32 0, i32 0) + %extracti16vec = extractvalue { <4 x i16>, i1 } %loadhalfrb, 0 + call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v4i16_1_0t.v4i16(target("dx.RawBuffer", <4 x i16>, 1, 0) %i16rb, i32 0, i32 0, <4 x i16> %extracti16vec) + ret void +} + +; Metadata to avoid adding flags not currently of interest to this test, and +; enable native low precision data types +!dx.valver = !{!0} +!0 = !{i32 1, i32 8} +!llvm.module.flags = !{!1, !2} +!1 = !{i32 1, !"dx.nativelowprec", i32 1} +!2 = !{i32 1, !"dx.resmayalias", i32 1} + +; DXC: - Name: SFI0 +; DXC-NEXT: Size: 8 +; DXC-NEXT: Flags: +; DXC: MinimumPrecision: false +; DXC: NativeLowPrecision: true +; DXC: ... diff --git a/llvm/test/CodeGen/DirectX/UAddc.ll b/llvm/test/CodeGen/DirectX/UAddc.ll index 4b46b56..dd7aa23 100644 --- a/llvm/test/CodeGen/DirectX/UAddc.ll +++ b/llvm/test/CodeGen/DirectX/UAddc.ll @@ -35,14 +35,10 @@ define noundef <2 x i32> @test_UAddc_vec2(<2 x i32> noundef %a, <2 x i32> nounde ; CHECK-NEXT: [[UADDC_I1:%.*]] = call [[DX_TYPES_I32C]] @dx.op.binaryWithCarryOrBorrow.i32(i32 44, i32 [[A_I1]], i32 [[B_I1]]) #[[ATTR0]] ; CHECK-NEXT: [[CARRY_ELEM0:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I0]], 1 ; CHECK-NEXT: [[CARRY_ELEM1:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I1]], 1 -; CHECK-NEXT: [[CARRY_UPTO0:%.*]] = insertelement <2 x i1> poison, i1 [[CARRY_ELEM0]], i64 0 -; CHECK-NEXT: [[CARRY:%.*]] = insertelement <2 x i1> [[CARRY_UPTO0]], i1 [[CARRY_ELEM1]], i64 1 -; CHECK-NEXT: [[CARRY_I0:%.*]] = extractelement <2 x i1> [[CARRY]], i64 0 -; CHECK-NEXT: [[CARRY_I1:%.*]] = extractelement <2 x i1> [[CARRY]], i64 1 ; CHECK-NEXT: [[SUM_ELEM0:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I0]], 0 ; CHECK-NEXT: [[SUM_ELEM1:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I1]], 0 -; CHECK-NEXT: [[CARRY_ZEXT_I0:%.*]] = zext i1 [[CARRY_I0]] to i32 -; CHECK-NEXT: [[CARRY_ZEXT_I1:%.*]] = zext i1 [[CARRY_I1]] to i32 +; CHECK-NEXT: [[CARRY_ZEXT_I0:%.*]] = zext i1 [[CARRY_ELEM0]] to i32 +; CHECK-NEXT: [[CARRY_ZEXT_I1:%.*]] = zext i1 [[CARRY_ELEM1]] to i32 ; CHECK-NEXT: [[RESULT_I0:%.*]] = add i32 [[SUM_ELEM0]], [[CARRY_ZEXT_I0]] ; CHECK-NEXT: [[RESULT_I1:%.*]] = add i32 [[SUM_ELEM1]], [[CARRY_ZEXT_I1]] ; CHECK-NEXT: [[RESULT_UPTO0:%.*]] = insertelement <2 x i32> poison, i32 [[RESULT_I0]], i64 0 diff --git a/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll b/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll new file mode 100644 index 0000000..156a8e7 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll @@ -0,0 +1,80 @@ +; RUN: opt -S -passes='dxil-data-scalarization' -mtriple=dxil-pc-shadermodel6.4-library %s | FileCheck %s --check-prefixes=SCHECK,CHECK +; RUN: opt -S -passes='dxil-data-scalarization,function(scalarizer<load-store>),dxil-flatten-arrays' -mtriple=dxil-pc-shadermodel6.4-library %s | FileCheck %s --check-prefixes=FCHECK,CHECK + +@aTile = hidden addrspace(3) global [10 x [10 x <4 x i32>]] zeroinitializer, align 16 +@bTile = hidden addrspace(3) global [10 x [10 x i32]] zeroinitializer, align 16 +@cTile = internal global [2 x [2 x <2 x i32>]] zeroinitializer, align 16 +@dTile = internal global [2 x [2 x [2 x <2 x i32>]]] zeroinitializer, align 16 + +define void @CSMain() { +; CHECK-LABEL: define void @CSMain() { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE:%.*]] = alloca [4 x i32], align 16 +; +; SCHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [10 x <4 x i32>], ptr addrspace(3) getelementptr inbounds ([10 x [10 x [4 x i32]]], ptr addrspace(3) @aTile.scalarized, i32 0, i32 1), i32 0, i32 2 +; SCHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(3) [[TMP0]], align 16 +; SCHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[AFRAGPACKED_I_SCALARIZE]], align 16 +; +; FCHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE_I14:%.*]] = getelementptr [4 x i32], ptr [[AFRAGPACKED_I_SCALARIZE]], i32 0, i32 1 +; FCHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE_I25:%.*]] = getelementptr [4 x i32], ptr [[AFRAGPACKED_I_SCALARIZE]], i32 0, i32 2 +; FCHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE_I36:%.*]] = getelementptr [4 x i32], ptr [[AFRAGPACKED_I_SCALARIZE]], i32 0, i32 3 +; FCHECK-NEXT: [[DOTI07:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 48), align 16 +; FCHECK-NEXT: [[DOTI119:%.*]] = load i32, ptr addrspace(3) getelementptr ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 49), align 4 +; FCHECK-NEXT: [[DOTI2211:%.*]] = load i32, ptr addrspace(3) getelementptr ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 50), align 8 +; FCHECK-NEXT: [[DOTI3313:%.*]] = load i32, ptr addrspace(3) getelementptr ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 51), align 4 +; FCHECK-NEXT: store i32 [[DOTI07]], ptr [[AFRAGPACKED_I_SCALARIZE]], align 16 +; FCHECK-NEXT: store i32 [[DOTI119]], ptr [[AFRAGPACKED_I_SCALARIZE_I14]], align 4 +; FCHECK-NEXT: store i32 [[DOTI2211]], ptr [[AFRAGPACKED_I_SCALARIZE_I25]], align 8 +; FCHECK-NEXT: store i32 [[DOTI3313]], ptr [[AFRAGPACKED_I_SCALARIZE_I36]], align 4 +; +; CHECK-NEXT: ret void +entry: + %aFragPacked.i = alloca <4 x i32>, align 16 + %0 = load <4 x i32>, ptr addrspace(3) getelementptr inbounds ([10 x <4 x i32>], ptr addrspace(3) getelementptr inbounds ([10 x [10 x <4 x i32>]], ptr addrspace(3) @aTile, i32 0, i32 1), i32 0, i32 2), align 16 + store <4 x i32> %0, ptr %aFragPacked.i, align 16 + ret void +} + +define void @Main() { +; CHECK-LABEL: define void @Main() { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[BFRAGPACKED_I:%.*]] = alloca i32, align 16 +; +; SCHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [10 x i32], ptr addrspace(3) getelementptr inbounds ([10 x [10 x i32]], ptr addrspace(3) @bTile, i32 0, i32 1), i32 0, i32 1 +; SCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(3) [[TMP0]], align 16 +; SCHECK-NEXT: store i32 [[TMP1]], ptr [[BFRAGPACKED_I]], align 16 +; +; FCHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([100 x i32], ptr addrspace(3) @bTile.1dim, i32 0, i32 11), align 16 +; FCHECK-NEXT: store i32 [[TMP0]], ptr [[BFRAGPACKED_I]], align 16 +; +; CHECK-NEXT: ret void +entry: + %bFragPacked.i = alloca i32, align 16 + %0 = load i32, ptr addrspace(3) getelementptr inbounds ([10 x i32], ptr addrspace(3) getelementptr inbounds ([10 x [10 x i32]], ptr addrspace(3) @bTile, i32 0, i32 1), i32 0, i32 1), align 16 + store i32 %0, ptr %bFragPacked.i, align 16 + ret void +} + +define void @global_nested_geps_3d() { +; CHECK-LABEL: define void @global_nested_geps_3d() { +; SCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <2 x i32>, ptr getelementptr inbounds ([2 x <2 x i32>], ptr getelementptr inbounds ([2 x [2 x [2 x i32]]], ptr @cTile.scalarized, i32 0, i32 1), i32 0, i32 1), i32 0, i32 1 +; SCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +; +; FCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @cTile.scalarized.1dim, i32 0, i32 7), align 4 +; +; CHECK-NEXT: ret void + %1 = load i32, i32* getelementptr inbounds (<2 x i32>, <2 x i32>* getelementptr inbounds ([2 x <2 x i32>], [2 x <2 x i32>]* getelementptr inbounds ([2 x [2 x <2 x i32>]], [2 x [2 x <2 x i32>]]* @cTile, i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), align 4 + ret void +} + +define void @global_nested_geps_4d() { +; CHECK-LABEL: define void @global_nested_geps_4d() { +; SCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <2 x i32>, ptr getelementptr inbounds ([2 x <2 x i32>], ptr getelementptr inbounds ([2 x [2 x <2 x i32>]], ptr getelementptr inbounds ([2 x [2 x [2 x [2 x i32]]]], ptr @dTile.scalarized, i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), i32 0, i32 1 +; SCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +; +; FCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([16 x i32], ptr @dTile.scalarized.1dim, i32 0, i32 15), align 4 +; +; CHECK-NEXT: ret void + %1 = load i32, i32* getelementptr inbounds (<2 x i32>, <2 x i32>* getelementptr inbounds ([2 x <2 x i32>], [2 x <2 x i32>]* getelementptr inbounds ([2 x [2 x <2 x i32>]], [2 x [2 x <2 x i32>]]* getelementptr inbounds ([2 x [2 x [2 x <2 x i32>]]], [2 x [2 x [2 x <2 x i32>]]]* @dTile, i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), align 4 + ret void +} diff --git a/llvm/test/CodeGen/DirectX/issue-145408-gep-struct-fix.ll b/llvm/test/CodeGen/DirectX/issue-145408-gep-struct-fix.ll index 40d222c..e6d4c1e 100644 --- a/llvm/test/CodeGen/DirectX/issue-145408-gep-struct-fix.ll +++ b/llvm/test/CodeGen/DirectX/issue-145408-gep-struct-fix.ll @@ -8,10 +8,12 @@ define void @test_no_transform_of_struct() { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: [[OUTPUTSIZESLOCAL_I:%.*]] = alloca [[STRUCT_RAWSTRUCT8D:%.*]], align 4 ; CHECK-NEXT: [[ARRAYINIT_ELEMENT13_I76:%.*]] = getelementptr inbounds nuw [1 x %struct.RawStruct8D], ptr [[OUTPUTSIZESLOCAL_I]], i32 0, i32 0 +; CHECK-NEXT: [[ARRAYINIT_ELEMENT13_I76_I1:%.*]] = getelementptr inbounds nuw [8 x i32], ptr [[ARRAYINIT_ELEMENT13_I76]], i32 0, i32 1 ; CHECK-NEXT: ret void ; entry: %outputSizesLocal.i = alloca %struct.RawStruct8D, align 4 %arrayinit.element13.i76 = getelementptr inbounds nuw [1 x %struct.RawStruct8D], ptr %outputSizesLocal.i, i32 0, i32 0 + %arrayinit.element13.i76.i1 = getelementptr inbounds nuw [8 x i32], ptr %arrayinit.element13.i76, i32 0, i32 1 ret void } diff --git a/llvm/test/CodeGen/DirectX/legalize-lifetimes-valver-1.6.ll b/llvm/test/CodeGen/DirectX/legalize-lifetimes-valver-1.6.ll index 6552ccd..77133eb 100644 --- a/llvm/test/CodeGen/DirectX/legalize-lifetimes-valver-1.6.ll +++ b/llvm/test/CodeGen/DirectX/legalize-lifetimes-valver-1.6.ll @@ -1,21 +1,27 @@ ; RUN: opt -S -passes='dxil-op-lower' -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s --check-prefixes=CHECK,CHECK-SM63 ; RUN: opt -S -passes='dxil-op-lower' -mtriple=dxil-pc-shadermodel6.6-library %s | FileCheck %s --check-prefixes=CHECK,CHECK-SM66 +; RUN: opt -S -dxil-prepare -dxil-embed -mtriple=dxil-pc-shadermodel6.6-library %s | FileCheck %s --check-prefixes=CHECK,CHECK-EMBED + +; Lifetime intrinsics are not valid prior to shader model 6.6 and are instead +; replaced with undef stores, provided the validator version is 1.6 or greater + +; The dxil-embed pass will remove lifetime intrinsics because they transformed +; in a way that is illegal in modern LLVM IR before serializing to DXIL bitcode. +; So we check that no bitcast or lifetime intrinsics remain after dxil-embed ; CHECK-LABEL: define void @test_legal_lifetime() { -; -; CHECK-SM63-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4 -; CHECK-SM63-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0 -; CHECK-SM63-NEXT: store [1 x i32] undef, ptr [[ACCUM_I_FLAT]], align 4 -; CHECK-SM63-NEXT: store i32 0, ptr [[GEP]], align 4 -; CHECK-SM63-NEXT: store [1 x i32] undef, ptr [[ACCUM_I_FLAT]], align 4 -; -; CHECK-SM66-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4 -; CHECK-SM66-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0 -; CHECK-SM66-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[ACCUM_I_FLAT]]) -; CHECK-SM66-NEXT: store i32 0, ptr [[GEP]], align 4 -; CHECK-SM66-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr nonnull [[ACCUM_I_FLAT]]) -; -; CHECK-NEXT: ret void +; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0 +; CHECK-SM63-NEXT: store [1 x i32] undef, ptr [[ACCUM_I_FLAT]], align 4 +; CHECK-SM66-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[ACCUM_I_FLAT]]) +; CHECK-EMBED-NOT: bitcast +; CHECK-EMBED-NOT: lifetime +; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4 +; CHECK-SM63-NEXT: store [1 x i32] undef, ptr [[ACCUM_I_FLAT]], align 4 +; CHECK-SM66-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr nonnull [[ACCUM_I_FLAT]]) +; CHECK-EMBED-NOT: bitcast +; CHECK-EMBED-NOT: lifetime +; CHECK-NEXT: ret void ; define void @test_legal_lifetime() { %accum.i.flat = alloca [1 x i32], align 4 |