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-rw-r--r--llvm/test/CodeGen/ARM/bad-constraint.ll25
-rw-r--r--llvm/test/CodeGen/ARM/inlineasm-int-to-float.ll17
-rw-r--r--llvm/test/CodeGen/ARM/stack-protector-eh-sjlj.ll164
3 files changed, 206 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/bad-constraint.ll b/llvm/test/CodeGen/ARM/bad-constraint.ll
new file mode 100644
index 0000000..9b8fcd5
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/bad-constraint.ll
@@ -0,0 +1,25 @@
+; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s
+; CHECK: error: couldn't allocate input reg for constraint '{d2}'
+; CHECK-NEXT: error: couldn't allocate input reg for constraint '{s2}'
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv8a-unknown-linux-gnueabihf"
+
+@a = local_unnamed_addr global i32 0, align 4
+
+define void @_Z1bv() local_unnamed_addr {
+entry:
+ %0 = load i32, ptr @a, align 4
+ %conv = sext i32 %0 to i64
+ tail call void asm sideeffect "", "{d2}"(i64 %conv)
+ ret void
+}
+
+define void @_Z1cv() local_unnamed_addr {
+entry:
+ %0 = load i32, ptr @a, align 4
+ %conv = sext i32 %0 to i64
+ tail call void asm sideeffect "", "{s2}"(i64 %conv)
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/ARM/inlineasm-int-to-float.ll b/llvm/test/CodeGen/ARM/inlineasm-int-to-float.ll
new file mode 100644
index 0000000..1c301b6
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/inlineasm-int-to-float.ll
@@ -0,0 +1,17 @@
+; RUN: llc -filetype=asm %s -o - | FileCheck %s
+
+; CHECK: movw r0, :lower16:a
+; CHECK-NEXT: movt r0, :upper16:a
+; CHECK-NEXT: vldr s6, [r0]
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv8a-unknown-linux-gnueabihf"
+
+@a = local_unnamed_addr global i32 0, align 4
+
+define void @_Z1dv() local_unnamed_addr {
+entry:
+ %0 = load i32, ptr @a, align 4
+ tail call void asm sideeffect "", "{s6}"(i32 %0)
+ ret void
+}
diff --git a/llvm/test/CodeGen/ARM/stack-protector-eh-sjlj.ll b/llvm/test/CodeGen/ARM/stack-protector-eh-sjlj.ll
new file mode 100644
index 0000000..fbd01ca
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/stack-protector-eh-sjlj.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -O0 -mtriple=thumbv7s-apple-darwin < %s | FileCheck %s
+target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+
+; Function Attrs: mustprogress noinline optnone ssp
+define ptr @foo() #0 personality ptr @__gxx_personality_sj0 {
+; CHECK-LABEL: foo:
+; CHECK: Lfunc_begin0:
+; CHECK-NEXT: @ %bb.0:
+; CHECK-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-NEXT: add r7, sp, #12
+; CHECK-NEXT: push.w {r8, r10, r11}
+; CHECK-NEXT: sub.w r4, sp, #64
+; CHECK-NEXT: bfc r4, #0, #4
+; CHECK-NEXT: mov sp, r4
+; CHECK-NEXT: vst1.64 {d8, d9, d10, d11}, [r4:128]!
+; CHECK-NEXT: vst1.64 {d12, d13, d14, d15}, [r4:128]
+; CHECK-NEXT: sub sp, #96
+; CHECK-NEXT: movw r0, :lower16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_2+4))
+; CHECK-NEXT: movt r0, :upper16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_2+4))
+; CHECK-NEXT: LPC0_2:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: movw r0, :lower16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_3+4))
+; CHECK-NEXT: movt r0, :upper16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_3+4))
+; CHECK-NEXT: LPC0_3:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: str r0, [sp, #92]
+; CHECK-NEXT: movw r0, :lower16:(L___gxx_personality_sj0$non_lazy_ptr-(LPC0_4+4))
+; CHECK-NEXT: movt r0, :upper16:(L___gxx_personality_sj0$non_lazy_ptr-(LPC0_4+4))
+; CHECK-NEXT: LPC0_4:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: str r0, [sp, #36]
+; CHECK-NEXT: ldr r0, LCPI0_0
+; CHECK-NEXT: LPC0_0:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: str r0, [sp, #40]
+; CHECK-NEXT: str r7, [sp, #44]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: str r0, [sp, #52]
+; CHECK-NEXT: ldr r0, LCPI0_1
+; CHECK-NEXT: orr r0, r0, #1
+; CHECK-NEXT: LPC0_1:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: str r0, [sp, #48]
+; CHECK-NEXT: add r0, sp, #12
+; CHECK-NEXT: bl __Unwind_SjLj_Register
+; CHECK-NEXT: movs r0, #1
+; CHECK-NEXT: str r0, [sp, #16]
+; CHECK-NEXT: movw r0, :lower16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_5+4))
+; CHECK-NEXT: movt r0, :upper16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_5+4))
+; CHECK-NEXT: LPC0_5:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r1, [sp, #92]
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: bne LBB0_7
+; CHECK-NEXT: @ %bb.1: @ %SP_return
+; CHECK-NEXT: Ltmp0:
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bl _foo2
+; CHECK-NEXT: Ltmp1:
+; CHECK-NEXT: b LBB0_2
+; CHECK-NEXT: LBB0_2:
+; CHECK-NEXT: movs r0, #2
+; CHECK-NEXT: str r0, [sp, #16]
+; CHECK-NEXT: movw r0, :lower16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_6+4))
+; CHECK-NEXT: movt r0, :upper16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_6+4))
+; CHECK-NEXT: LPC0_6:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r1, [sp, #92]
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: bne LBB0_7
+; CHECK-NEXT: @ %bb.3: @ %SP_return2
+; CHECK-NEXT: Ltmp2:
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: mov r1, r2
+; CHECK-NEXT: bl _foo3
+; CHECK-NEXT: Ltmp3:
+; CHECK-NEXT: b LBB0_6
+; CHECK-NEXT: LBB0_4:
+; CHECK-NEXT: Ltmp4:
+; CHECK-NEXT: ldr r0, [sp, #20]
+; CHECK-NEXT: ldr r0, [sp, #24]
+; CHECK-NEXT: add r0, sp, #12
+; CHECK-NEXT: bl __Unwind_SjLj_Unregister
+; CHECK-NEXT: movw r0, :lower16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_7+4))
+; CHECK-NEXT: movt r0, :upper16:(L___stack_chk_guard$non_lazy_ptr-(LPC0_7+4))
+; CHECK-NEXT: LPC0_7:
+; CHECK-NEXT: add r0, pc
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: ldr r1, [sp, #92]
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: bne LBB0_7
+; CHECK-NEXT: @ %bb.5: @ %SP_return3
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: add r4, sp, #96
+; CHECK-NEXT: vld1.64 {d8, d9, d10, d11}, [r4:128]!
+; CHECK-NEXT: vld1.64 {d12, d13, d14, d15}, [r4:128]
+; CHECK-NEXT: sub.w r4, r7, #24
+; CHECK-NEXT: mov sp, r4
+; CHECK-NEXT: pop.w {r8, r10, r11}
+; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
+; CHECK-NEXT: LBB0_6:
+; CHECK-NEXT: trap
+; CHECK-NEXT: LBB0_7: @ %CallStackCheckFailBlk
+; CHECK-NEXT: bl ___stack_chk_fail
+; CHECK-NEXT: LBB0_8:
+; CHECK-NEXT: ldr r0, [sp, #16]
+; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: cmp r0, #2
+; CHECK-NEXT: bhi LBB0_12
+; CHECK-NEXT: @ %bb.9:
+; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: LCPI0_2:
+; CHECK-NEXT: tbb [pc, r1]
+; CHECK-NEXT: @ %bb.10:
+; CHECK-NEXT: LJTI0_0:
+; CHECK-NEXT: .data_region jt8
+; CHECK-NEXT: .byte (LBB0_11-(LCPI0_2+4))/2
+; CHECK-NEXT: .byte (LBB0_11-(LCPI0_2+4))/2
+; CHECK-NEXT: .end_data_region
+; CHECK-NEXT: .p2align 1
+; CHECK-NEXT: LBB0_11:
+; CHECK-NEXT: b LBB0_4
+; CHECK-NEXT: LBB0_12:
+; CHECK-NEXT: trap
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.13:
+ %1 = alloca [14 x i8], align 16
+ %2 = invoke i32 @"foo2"(ptr null, ptr null) #1
+ to label %3 unwind label %4
+
+3: ; preds = %0
+ invoke void @"foo3"(ptr null, ptr null, ptr null) #2
+ to label %6 unwind label %4
+
+4: ; preds = %3, %0
+ %5 = landingpad { ptr, i32 }
+ cleanup
+ ret ptr null
+
+6: ; preds = %3
+ unreachable
+}
+
+declare i32 @__gxx_personality_sj0(...)
+declare i32 @foo2(ptr,ptr)
+declare void @foo3(ptr,ptr,ptr)
+; uselistorder directives
+uselistorder ptr null, { 2, 3, 4, 5, 0, 6, 7, 1, 8, 9 }
+
+attributes #0 = { mustprogress ssp "frame-pointer"="all" "no-builtin-calloc" "no-builtin-stpcpy" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #2 = { noreturn }
generated by cgit v1.1 at 2025-07-28 04:11:31 +0000