diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll b/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll index b3eb305..6fb485c 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: opt -S -passes=always-inline -o %t.bc %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1102 -mattr=+wavefrontsize32 -misched=gcn-max-occupancy -verify-machineinstrs < %t.bc | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=amdgcn -mcpu=gfx1102 -mattr=+wavefrontsize32 -misched=gcn-max-occupancy < %t.bc | FileCheck %s --check-prefixes=CHECK ; Provide a long sequence of 32 vec4 load/store pairs that ought to be fully ; overlapped for latency hiding. Doing so requires using (at least) 128 VGPRs, |