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Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.log10.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/llvm.log10.ll278
1 files changed, 101 insertions, 177 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 8006876..058933f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -5590,162 +5590,15 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
}
define float @v_log10_f32_undef() {
-; SI-SDAG-LABEL: v_log10_f32_undef:
-; SI-SDAG: ; %bb.0:
-; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: v_log_f32_e32 v0, s4
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3284fbcf
-; SI-SDAG-NEXT: s_mov_b32 s6, 0x7f800000
-; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-GISEL-LABEL: v_log10_f32_undef:
-; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
-; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
-; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
-; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SDAG-LABEL: v_log10_f32_undef:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_log_f32_e32 v0, s4
-; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
-; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-GISEL-LABEL: v_log10_f32_undef:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-SDAG-LABEL: v_log10_f32_undef:
-; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s4
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3284fbcf
-; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x7f800000
-; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
-; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-GISEL-LABEL: v_log10_f32_undef:
-; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
-; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-SDAG-LABEL: v_log10_f32_undef:
-; GFX1100-SDAG: ; %bb.0:
-; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX689-LABEL: v_log10_f32_undef:
+; GFX689: ; %bb.0:
+; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX689-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-GISEL-LABEL: v_log10_f32_undef:
-; GFX1100-GISEL: ; %bb.0:
-; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, 0x4f800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x800000, s0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_log10_f32_undef:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_undef:
; R600: ; %bb.0:
@@ -6377,28 +6230,99 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_from_fpext_bf16:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX1100-SDAG-TRUE16: ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX1100-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 32, vcc_lo
+; GFX1100-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX1100-SDAG-FAKE16: ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX1100-GISEL-TRUE16: ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX1100-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
+; GFX1100-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 32, vcc_lo
+; GFX1100-GISEL-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-GISEL-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX1100-GISEL-FAKE16: ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-GISEL-FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_from_fpext_bf16:
; R600: ; %bb.0:
generated by cgit v1.1 at 2025-07-24 01:18:10 +0000