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-rw-r--r--llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll305
1 files changed, 305 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
new file mode 100644
index 0000000..3a55070
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
@@ -0,0 +1,305 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=SDAG-REAL16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=GISEL-REAL16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=GISEL-FAKE16 %s
+
+declare i16 @llvm.amdgcn.sat.pk4.i4.i8(i32) #0
+declare i16 @llvm.amdgcn.sat.pk4.u4.u8(i32) #0
+
+define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
+; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
+; SDAG-REAL16: ; %bb.0:
+; SDAG-REAL16-NEXT: s_clause 0x1
+; SDAG-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT: s_endpgm
+;
+; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
+; SDAG-FAKE16: ; %bb.0:
+; SDAG-FAKE16-NEXT: s_clause 0x1
+; SDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s2
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
+; SDAG-FAKE16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
+; GISEL-REAL16: ; %bb.0:
+; GISEL-REAL16-NEXT: s_clause 0x1
+; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-REAL16-NEXT: s_endpgm
+;
+; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
+; GISEL-FAKE16: ; %bb.0:
+; GISEL-FAKE16-NEXT: s_clause 0x1
+; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-FAKE16-NEXT: s_endpgm
+ %cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
+ store i16 %cvt, ptr %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
+; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
+; SDAG-REAL16: ; %bb.1:
+; SDAG-REAL16-NEXT: s_load_b32 s8, s[4:5], 0x0
+; SDAG-REAL16-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-REAL16-NEXT: s_branch .LBB1_0
+; SDAG-REAL16-NEXT: .p2align 8
+; SDAG-REAL16-NEXT: ; %bb.2:
+; SDAG-REAL16-NEXT: .LBB1_0:
+; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s8
+; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT: s_endpgm
+;
+; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
+; SDAG-FAKE16: ; %bb.1:
+; SDAG-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x0
+; SDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-FAKE16-NEXT: s_branch .LBB1_0
+; SDAG-FAKE16-NEXT: .p2align 8
+; SDAG-FAKE16-NEXT: ; %bb.2:
+; SDAG-FAKE16-NEXT: .LBB1_0:
+; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s8
+; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
+; SDAG-FAKE16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
+; GISEL-REAL16: ; %bb.0:
+; GISEL-REAL16-NEXT: s_clause 0x1
+; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-REAL16-NEXT: s_endpgm
+;
+; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
+; GISEL-FAKE16: ; %bb.0:
+; GISEL-FAKE16-NEXT: s_clause 0x1
+; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-FAKE16-NEXT: s_endpgm
+ %cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
+ store i16 %cvt, ptr %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
+; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
+; SDAG-REAL16: ; %bb.0:
+; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
+; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT: s_endpgm
+;
+; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
+; SDAG-FAKE16: ; %bb.0:
+; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, 0x64
+; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
+; SDAG-FAKE16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
+; GISEL-REAL16: ; %bb.0:
+; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
+; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-REAL16-NEXT: s_endpgm
+;
+; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
+; GISEL-FAKE16: ; %bb.0:
+; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, 0x64
+; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-FAKE16-NEXT: s_endpgm
+ %cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 100) #0
+ store i16 %cvt, ptr %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
+; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
+; SDAG-REAL16: ; %bb.0:
+; SDAG-REAL16-NEXT: s_clause 0x1
+; SDAG-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT: s_endpgm
+;
+; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
+; SDAG-FAKE16: ; %bb.0:
+; SDAG-FAKE16-NEXT: s_clause 0x1
+; SDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s2
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
+; SDAG-FAKE16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
+; GISEL-REAL16: ; %bb.0:
+; GISEL-REAL16-NEXT: s_clause 0x1
+; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-REAL16-NEXT: s_endpgm
+;
+; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
+; GISEL-FAKE16: ; %bb.0:
+; GISEL-FAKE16-NEXT: s_clause 0x1
+; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-FAKE16-NEXT: s_endpgm
+ %cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
+ store i16 %cvt, ptr %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
+; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
+; SDAG-REAL16: ; %bb.1:
+; SDAG-REAL16-NEXT: s_load_b32 s8, s[4:5], 0x0
+; SDAG-REAL16-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-REAL16-NEXT: s_branch .LBB4_0
+; SDAG-REAL16-NEXT: .p2align 8
+; SDAG-REAL16-NEXT: ; %bb.2:
+; SDAG-REAL16-NEXT: .LBB4_0:
+; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s8
+; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT: s_endpgm
+;
+; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
+; SDAG-FAKE16: ; %bb.1:
+; SDAG-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x0
+; SDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-FAKE16-NEXT: s_branch .LBB4_0
+; SDAG-FAKE16-NEXT: .p2align 8
+; SDAG-FAKE16-NEXT: ; %bb.2:
+; SDAG-FAKE16-NEXT: .LBB4_0:
+; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s8
+; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
+; SDAG-FAKE16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
+; GISEL-REAL16: ; %bb.0:
+; GISEL-REAL16-NEXT: s_clause 0x1
+; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-REAL16-NEXT: s_endpgm
+;
+; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
+; GISEL-FAKE16: ; %bb.0:
+; GISEL-FAKE16-NEXT: s_clause 0x1
+; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
+; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
+; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-FAKE16-NEXT: s_endpgm
+ %cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
+ store i16 %cvt, ptr %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
+; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
+; SDAG-REAL16: ; %bb.0:
+; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
+; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT: s_endpgm
+;
+; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
+; SDAG-FAKE16: ; %bb.0:
+; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, 0x64
+; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
+; SDAG-FAKE16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
+; GISEL-REAL16: ; %bb.0:
+; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
+; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-REAL16-NEXT: s_endpgm
+;
+; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
+; GISEL-FAKE16: ; %bb.0:
+; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, 0x64
+; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
+; GISEL-FAKE16-NEXT: s_endpgm
+ %cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 100) #0
+ store i16 %cvt, ptr %out, align 2
+ ret void
+}
+
+attributes #0 = { nounwind memory(none) }
+attributes #1 = { nounwind }
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