diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/literal64.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/literal64.ll | 52 |
1 files changed, 13 insertions, 39 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/literal64.ll b/llvm/test/CodeGen/AMDGPU/literal64.ll index df4ff2c..768c972 100644 --- a/llvm/test/CodeGen/AMDGPU/literal64.ll +++ b/llvm/test/CodeGen/AMDGPU/literal64.ll @@ -12,21 +12,11 @@ define amdgpu_ps i64 @s_add_u64(i64 inreg %a) { } define amdgpu_ps void @v_add_u64(i64 %a, ptr addrspace(1) %out) { -; GCN-SDAG-LABEL: v_add_u64: -; GCN-SDAG: ; %bb.0: -; GCN-SDAG-NEXT: s_mov_b64 s[0:1], lit64(0xf12345678) -; GCN-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GCN-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] -; GCN-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off -; GCN-SDAG-NEXT: s_endpgm -; -; GCN-GISEL-LABEL: v_add_u64: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: v_mov_b64_e32 v[4:5], lit64(0xf12345678) -; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GCN-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[4:5] -; GCN-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off -; GCN-GISEL-NEXT: s_endpgm +; GCN-LABEL: v_add_u64: +; GCN: ; %bb.0: +; GCN-NEXT: v_add_nc_u64_e32 v[0:1], lit64(0xf12345678), v[0:1] +; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off +; GCN-NEXT: s_endpgm %result = add i64 %a, 64729929336 store i64 %result, ptr addrspace(1) %out, align 8 ret void @@ -42,21 +32,11 @@ define amdgpu_ps i64 @s_add_neg_u64(i64 inreg %a) { } define amdgpu_ps void @v_add_neg_u64(i64 %a, ptr addrspace(1) %out) { -; GCN-SDAG-LABEL: v_add_neg_u64: -; GCN-SDAG: ; %bb.0: -; GCN-SDAG-NEXT: s_mov_b64 s[0:1], lit64(0xfffffff0edcba988) -; GCN-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GCN-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] -; GCN-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off -; GCN-SDAG-NEXT: s_endpgm -; -; GCN-GISEL-LABEL: v_add_neg_u64: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: v_mov_b64_e32 v[4:5], lit64(0xfffffff0edcba988) -; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GCN-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[4:5] -; GCN-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off -; GCN-GISEL-NEXT: s_endpgm +; GCN-LABEL: v_add_neg_u64: +; GCN: ; %bb.0: +; GCN-NEXT: v_add_nc_u64_e32 v[0:1], lit64(0xfffffff0edcba988), v[0:1] +; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off +; GCN-NEXT: s_endpgm %result = sub i64 %a, 64729929336 store i64 %result, ptr addrspace(1) %out, align 8 ret void @@ -74,9 +54,7 @@ define amdgpu_ps i64 @s_sub_u64(i64 inreg %a) { define amdgpu_ps void @v_sub_u64(i64 %a, ptr addrspace(1) %out) { ; GCN-LABEL: v_sub_u64: ; GCN: ; %bb.0: -; GCN-NEXT: v_sub_co_u32 v0, vcc_lo, 0x12345678, v0 -; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GCN-NEXT: v_sub_co_ci_u32_e64 v1, null, 15, v1, vcc_lo +; GCN-NEXT: v_sub_nc_u64_e32 v[0:1], lit64(0xf12345678), v[0:1] ; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off ; GCN-NEXT: s_endpgm %result = sub i64 64729929336, %a @@ -94,15 +72,15 @@ define void @v_mov_b64_double(ptr addrspace(1) %ptr) { ; GCN-NEXT: .LBB6_1: ; %atomicrmw.start ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: s_wait_loadcnt 0x0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GCN-NEXT: v_add_f64_e32 v[2:3], lit64(0x4063233333333333), v[4:5] ; GCN-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GCN-NEXT: s_wait_loadcnt 0x0 ; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] ; GCN-NEXT: s_wait_xcnt 0x0 ; GCN-NEXT: v_mov_b64_e32 v[4:5], v[2:3] -; GCN-NEXT: s_wait_alu 0xfffe ; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 -; GCN-NEXT: s_wait_alu 0xfffe +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GCN-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 ; GCN-NEXT: s_cbranch_execnz .LBB6_1 ; GCN-NEXT: ; %bb.2: ; %atomicrmw.end @@ -143,9 +121,7 @@ define i1 @class_f64() noinline optnone { ; GCN-SDAG-NEXT: s_wait_kmcnt 0x0 ; GCN-SDAG-NEXT: s_mov_b32 s2, 1 ; GCN-SDAG-NEXT: s_mov_b64 s[0:1], lit64(0x4063233333333333) -; GCN-SDAG-NEXT: s_wait_alu 0xfffe ; GCN-SDAG-NEXT: v_cmp_class_f64_e64 s0, s[0:1], s2 -; GCN-SDAG-NEXT: s_wait_alu 0xf1ff ; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GCN-SDAG-NEXT: s_set_pc_i64 s[30:31] ; @@ -155,13 +131,11 @@ define i1 @class_f64() noinline optnone { ; GCN-GISEL-NEXT: s_wait_kmcnt 0x0 ; GCN-GISEL-NEXT: s_mov_b32 s2, 1 ; GCN-GISEL-NEXT: s_mov_b64 s[0:1], lit64(0x4063233333333333) -; GCN-GISEL-NEXT: s_wait_alu 0xfffe ; GCN-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GCN-GISEL-NEXT: v_cmp_class_f64_e64 s0, v[0:1], v2 ; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 1 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GCN-GISEL-NEXT: s_wait_alu 0xf1ff ; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, v0, s0 ; GCN-GISEL-NEXT: s_set_pc_i64 s[30:31] %result = call i1 @llvm.amdgcn.class.f64(double 153.1, i32 1) nounwind readnone |