diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/bitop3.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/bitop3.ll | 313 |
1 files changed, 271 insertions, 42 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/bitop3.ll b/llvm/test/CodeGen/AMDGPU/bitop3.ll index eb149a93..ba818f6 100644 --- a/llvm/test/CodeGen/AMDGPU/bitop3.ll +++ b/llvm/test/CodeGen/AMDGPU/bitop3.ll @@ -1,6 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-SDAG %s ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-SDAG-FAKE16,GFX1250-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-SDAG-TRUE16,GFX1250-TRUE16 %s +; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-FAKE16,GFX1250-FAKE16 %s +; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-TRUE16,GFX1250-TRUE16 %s ; ========= Single bit functions ========= @@ -55,6 +59,18 @@ define amdgpu_ps float @not_and_and_and(i32 %a, i32 %b, i32 %c) { ; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc ; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: not_and_and_and: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:8 +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: not_and_and_and: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %nota = xor i32 %a, -1 %and1 = and i32 %nota, %c %and2 = and i32 %and1, %b @@ -87,6 +103,19 @@ define amdgpu_ps float @and_not_and_and(i32 %a, i32 %b, i32 %c) { ; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v2 ; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: and_not_and_and: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x20 +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: and_not_and_and: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_not_b32_e32 v1, v1 +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v2 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %notb = xor i32 %b, -1 %and1 = and i32 %a, %c %and2 = and i32 %and1, %notb @@ -105,6 +134,18 @@ define amdgpu_ps float @and_and_not_and(i32 %a, i32 %b, i32 %c) { ; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0x30 ; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: and_and_not_and: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x40 +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: and_and_not_and: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0x30 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %notc = xor i32 %c, -1 %and1 = and i32 %a, %notc %and2 = and i32 %and1, %b @@ -113,15 +154,10 @@ define amdgpu_ps float @and_and_not_and(i32 %a, i32 %b, i32 %c) { } define amdgpu_ps float @and_and_and(i32 %a, i32 %b, i32 %c) { -; GFX950-SDAG-LABEL: and_and_and: -; GFX950-SDAG: ; %bb.0: -; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80 -; GFX950-SDAG-NEXT: ; return to shader part epilog -; -; GFX950-GISEL-LABEL: and_and_and: -; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80 -; GFX950-GISEL-NEXT: ; return to shader part epilog +; GCN-LABEL: and_and_and: +; GCN: ; %bb.0: +; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80 +; GCN-NEXT: ; return to shader part epilog %and1 = and i32 %a, %c %and2 = and i32 %and1, %b %ret_cast = bitcast i32 %and2 to float @@ -131,15 +167,10 @@ define amdgpu_ps float @and_and_and(i32 %a, i32 %b, i32 %c) { ; ========= Multi bit functions ========= define amdgpu_ps float @test_12(i32 %a, i32 %b) { -; GFX950-SDAG-LABEL: test_12: -; GFX950-SDAG: ; %bb.0: -; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc -; GFX950-SDAG-NEXT: ; return to shader part epilog -; -; GFX950-GISEL-LABEL: test_12: -; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc -; GFX950-GISEL-NEXT: ; return to shader part epilog +; GCN-LABEL: test_12: +; GCN: ; %bb.0: +; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc +; GCN-NEXT: ; return to shader part epilog %nota = xor i32 %a, -1 %and1 = and i32 %nota, %b %ret_cast = bitcast i32 %and1 to float @@ -158,6 +189,19 @@ define amdgpu_ps float @test_63(i32 %a, i32 %b) { ; GFX950-GISEL-NEXT: v_not_b32_e32 v1, v1 ; GFX950-GISEL-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: test_63: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0x3f +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_63: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_not_b32_e32 v0, v0 +; GFX1250-GISEL-NEXT: v_not_b32_e32 v1, v1 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %nota = xor i32 %a, -1 %notb = xor i32 %b, -1 %or = or i32 %nota, %notb @@ -190,6 +234,19 @@ define amdgpu_ps float @test_126(i32 %a, i32 %b, i32 %c) { ; GFX950-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2 ; GFX950-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: test_126: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v2, v1 bitop3:0x7e +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_126: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_xor_b32_e32 v1, v0, v1 +; GFX1250-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %xor1 = xor i32 %a, %b %xor2 = xor i32 %a, %c %or = or i32 %xor1, %xor2 @@ -216,6 +273,21 @@ define amdgpu_ps float @test_12_src_overflow(i32 %a, i32 %b, i32 %c) { ; GFX950-GISEL-NEXT: v_and_b32_e32 v2, v3, v4 ; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xc8 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: test_12_src_overflow: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_12_src_overflow: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_not_b32_e32 v3, v0 +; GFX1250-GISEL-NEXT: v_not_b32_e32 v4, v2 +; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_and_b32_e32 v2, v3, v4 +; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xc8 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %nota = xor i32 %a, -1 %notc = xor i32 %c, -1 %and1 = and i32 %nota, %c @@ -249,6 +321,29 @@ define amdgpu_ps float @test_100_src_overflow(i32 %a, i32 %b, i32 %c) { ; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v1 ; GFX950-GISEL-NEXT: v_or3_b32 v0, v3, v4, v0 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: test_100_src_overflow: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_bitop3_b32 v3, v1, v2, v0 bitop3:0x10 +; GFX1250-SDAG-NEXT: v_bitop3_b32 v4, v0, v2, v1 bitop3:0x40 +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v1, v2, v0 bitop3:0x20 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_or3_b32 v0, v3, v4, v0 +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_100_src_overflow: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_bitop3_b32 v3, v2, v0, v2 bitop3:3 +; GFX1250-GISEL-NEXT: v_bitop3_b32 v4, v0, v1, v0 bitop3:0x30 +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v1, v0 +; GFX1250-GISEL-NEXT: v_not_b32_e32 v5, v2 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, v1, v3 +; GFX1250-GISEL-NEXT: v_and_b32_e32 v2, v4, v2 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v5 +; GFX1250-GISEL-NEXT: v_or3_b32 v0, v1, v2, v0 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %or1 = or i32 %c, %a %not1 = xor i32 %or1, -1 %and1 = and i32 %b, %not1 @@ -267,11 +362,16 @@ define amdgpu_ps float @test_100_src_overflow(i32 %a, i32 %b, i32 %c) { ; ========= Ternary logical operations take precedence ========= define amdgpu_ps float @test_xor3(i32 %a, i32 %b, i32 %c) { -; GCN-LABEL: test_xor3: -; GCN: ; %bb.0: -; GCN-NEXT: v_xor_b32_e32 v0, v0, v1 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 -; GCN-NEXT: ; return to shader part epilog +; GFX950-LABEL: test_xor3: +; GFX950: ; %bb.0: +; GFX950-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX950-NEXT: v_xor_b32_e32 v0, v0, v2 +; GFX950-NEXT: ; return to shader part epilog +; +; GFX1250-LABEL: test_xor3: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_xor3_b32 v0, v0, v1, v2 +; GFX1250-NEXT: ; return to shader part epilog %xor1 = xor i32 %a, %b %xor2 = xor i32 %xor1, %c %ret_cast = bitcast i32 %xor2 to float @@ -303,12 +403,20 @@ define amdgpu_ps float @test_and_or(i32 %a, i32 %b, i32 %c) { ; ========= Uniform cases ========= define amdgpu_ps float @uniform_3_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) { -; GCN-LABEL: uniform_3_op: -; GCN: ; %bb.0: -; GCN-NEXT: s_andn2_b32 s0, s2, s0 -; GCN-NEXT: s_and_b32 s0, s0, s1 -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: ; return to shader part epilog +; GFX950-LABEL: uniform_3_op: +; GFX950: ; %bb.0: +; GFX950-NEXT: s_andn2_b32 s0, s2, s0 +; GFX950-NEXT: s_and_b32 s0, s0, s1 +; GFX950-NEXT: v_mov_b32_e32 v0, s0 +; GFX950-NEXT: ; return to shader part epilog +; +; GFX1250-LABEL: uniform_3_op: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_and_not1_b32 s0, s2, s0 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-NEXT: s_and_b32 s0, s0, s1 +; GFX1250-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-NEXT: ; return to shader part epilog %nota = xor i32 %a, -1 %and1 = and i32 %nota, %c %and2 = and i32 %and1, %b @@ -330,6 +438,21 @@ define amdgpu_ps float @uniform_4_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) { ; GFX950-GISEL-NEXT: s_andn2_b32 s0, s0, s1 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-LABEL: uniform_4_op: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:2 +; GFX1250-SDAG-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: uniform_4_op: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: s_and_not1_b32 s0, s2, s0 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-NEXT: s_and_not1_b32 s0, s0, s1 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %nota = xor i32 %a, -1 %notb = xor i32 %b, -1 %and1 = and i32 %nota, %c @@ -341,10 +464,30 @@ define amdgpu_ps float @uniform_4_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) { ; ========= 16 bit tests ========= define amdgpu_ps half @not_and_not_and_not_and_b16(i16 %a, i16 %b, i16 %c) { -; GCN-LABEL: not_and_not_and_not_and_b16: -; GCN: ; %bb.0: -; GCN-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1 -; GCN-NEXT: ; return to shader part epilog +; GFX950-LABEL: not_and_not_and_not_and_b16: +; GFX950: ; %bb.0: +; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1 +; GFX950-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-FAKE16-LABEL: not_and_not_and_not_and_b16: +; GFX1250-SDAG-FAKE16: ; %bb.0: +; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1 +; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-TRUE16-LABEL: not_and_not_and_not_and_b16: +; GFX1250-SDAG-TRUE16: ; %bb.0: +; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1 +; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-FAKE16-LABEL: not_and_not_and_not_and_b16: +; GFX1250-GISEL-FAKE16: ; %bb.0: +; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1 +; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-TRUE16-LABEL: not_and_not_and_not_and_b16: +; GFX1250-GISEL-TRUE16: ; %bb.0: +; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1 +; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog %nota = xor i16 %a, -1 %notb = xor i16 %b, -1 %notc = xor i16 %c, -1 @@ -355,10 +498,30 @@ define amdgpu_ps half @not_and_not_and_not_and_b16(i16 %a, i16 %b, i16 %c) { } define amdgpu_ps half @not_and_not_and_and_b16(i16 %a, i16 %b, i16 %c) { -; GCN-LABEL: not_and_not_and_and_b16: -; GCN: ; %bb.0: -; GCN-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2 -; GCN-NEXT: ; return to shader part epilog +; GFX950-LABEL: not_and_not_and_and_b16: +; GFX950: ; %bb.0: +; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2 +; GFX950-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-FAKE16-LABEL: not_and_not_and_and_b16: +; GFX1250-SDAG-FAKE16: ; %bb.0: +; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2 +; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-TRUE16-LABEL: not_and_not_and_and_b16: +; GFX1250-SDAG-TRUE16: ; %bb.0: +; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2 +; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-FAKE16-LABEL: not_and_not_and_and_b16: +; GFX1250-GISEL-FAKE16: ; %bb.0: +; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2 +; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-TRUE16-LABEL: not_and_not_and_and_b16: +; GFX1250-GISEL-TRUE16: ; %bb.0: +; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2 +; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog %nota = xor i16 %a, -1 %notb = xor i16 %b, -1 %and1 = and i16 %nota, %c @@ -368,10 +531,30 @@ define amdgpu_ps half @not_and_not_and_and_b16(i16 %a, i16 %b, i16 %c) { } define amdgpu_ps half @not_and_and_not_and_b16(i16 %a, i16 %b, i16 %c) { -; GCN-LABEL: not_and_and_not_and_b16: -; GCN: ; %bb.0: -; GCN-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4 -; GCN-NEXT: ; return to shader part epilog +; GFX950-LABEL: not_and_and_not_and_b16: +; GFX950: ; %bb.0: +; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4 +; GFX950-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-FAKE16-LABEL: not_and_and_not_and_b16: +; GFX1250-SDAG-FAKE16: ; %bb.0: +; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4 +; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-TRUE16-LABEL: not_and_and_not_and_b16: +; GFX1250-SDAG-TRUE16: ; %bb.0: +; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4 +; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-FAKE16-LABEL: not_and_and_not_and_b16: +; GFX1250-GISEL-FAKE16: ; %bb.0: +; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4 +; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-TRUE16-LABEL: not_and_and_not_and_b16: +; GFX1250-GISEL-TRUE16: ; %bb.0: +; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4 +; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog %nota = xor i16 %a, -1 %notc = xor i16 %c, -1 %and1 = and i16 %nota, %notc @@ -391,6 +574,21 @@ define amdgpu_ps half @test_xor3_b16(i16 %a, i16 %b, i16 %c) { ; GFX950-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1 ; GFX950-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-FAKE16-LABEL: test_xor3_b16: +; GFX1250-SDAG-FAKE16: ; %bb.0: +; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0x96 +; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-TRUE16-LABEL: test_xor3_b16: +; GFX1250-SDAG-TRUE16: ; %bb.0: +; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0x96 +; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_xor3_b16: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_xor3_b32 v0, v0, v1, v2 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %xor1 = xor i16 %a, %b %xor2 = xor i16 %xor1, %c %ret_cast = bitcast i16 %xor2 to half @@ -407,6 +605,21 @@ define amdgpu_ps half @test_or3_b16(i16 %a, i16 %b, i16 %c) { ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-FAKE16-LABEL: test_or3_b16: +; GFX1250-SDAG-FAKE16: ; %bb.0: +; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xfe +; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-TRUE16-LABEL: test_or3_b16: +; GFX1250-SDAG-TRUE16: ; %bb.0: +; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xfe +; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_or3_b16: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %or1 = or i16 %a, %b %or2 = or i16 %or1, %c %ret_cast = bitcast i16 %or2 to half @@ -423,10 +636,26 @@ define amdgpu_ps half @test_and_or_b16(i16 %a, i16 %b, i16 %c) { ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_and_or_b32 v0, v0, v1, v2 ; GFX950-GISEL-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-FAKE16-LABEL: test_and_or_b16: +; GFX1250-SDAG-FAKE16: ; %bb.0: +; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xec +; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX1250-SDAG-TRUE16-LABEL: test_and_or_b16: +; GFX1250-SDAG-TRUE16: ; %bb.0: +; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xec +; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250-GISEL-LABEL: test_and_or_b16: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_and_or_b32 v0, v0, v1, v2 +; GFX1250-GISEL-NEXT: ; return to shader part epilog %and1 = and i16 %a, %b %or1 = or i16 %and1, %c %ret_cast = bitcast i16 %or1 to half ret half %ret_cast } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX950: {{.*}} +; GFX1250-FAKE16: {{.*}} +; GFX1250-TRUE16: {{.*}} |