diff options
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
3 files changed, 45 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index bf2e04c..09b8864 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -46,6 +46,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( : TargetLowering(TM), Subtarget(&STI) { auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; + // Set the load count for memcmp expand optimization + MaxLoadsPerMemcmp = 8; + MaxLoadsPerMemcmpOptSize = 4; + // Booleans always contain 0 or 1. setBooleanContents(ZeroOrOneBooleanContent); // Except in SIMD vectors @@ -2935,6 +2939,25 @@ performVectorExtendToFPCombine(SDNode *N, } static SDValue +performVectorNonNegToFPCombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI) { + auto &DAG = DCI.DAG; + + SDNodeFlags Flags = N->getFlags(); + SDValue Op0 = N->getOperand(0); + EVT VT = N->getValueType(0); + + // Optimize uitofp to sitofp when the sign bit is known to be zero. + // Depending on the target (runtime) backend, this might be performance + // neutral (e.g. AArch64) or a significant improvement (e.g. x86_64). + if (VT.isVector() && (Flags.hasNonNeg() || DAG.SignBitIsZero(Op0))) { + return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, Op0); + } + + return SDValue(); +} + +static SDValue performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { auto &DAG = DCI.DAG; assert(N->getOpcode() == ISD::SIGN_EXTEND || @@ -3515,6 +3538,9 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N, case ISD::ZERO_EXTEND: return performVectorExtendCombine(N, DCI); case ISD::UINT_TO_FP: + if (auto ExtCombine = performVectorExtendToFPCombine(N, DCI)) + return ExtCombine; + return performVectorNonNegToFPCombine(N, DCI); case ISD::SINT_TO_FP: return performVectorExtendToFPCombine(N, DCI); case ISD::FP_TO_SINT_SAT: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp index 4f15999..52e7065 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp @@ -141,6 +141,21 @@ InstructionCost WebAssemblyTTIImpl::getCastInstrCost( return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); } +WebAssemblyTTIImpl::TTI::MemCmpExpansionOptions +WebAssemblyTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { + TTI::MemCmpExpansionOptions Options; + + Options.AllowOverlappingLoads = true; + + // TODO: Teach WebAssembly backend about load v128. + + Options.LoadSizes.append({8, 4, 2, 1}); + Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); + Options.NumLoadsPerBlock = Options.MaxNumLoads; + + return Options; +} + InstructionCost WebAssemblyTTIImpl::getMemoryOpCost( unsigned Opcode, Type *Ty, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index d83b8d1..c915eeb0 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -73,6 +73,10 @@ public: getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I = nullptr) const override; + + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override; + InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, |