diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrFormats.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td | 414 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td | 642 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td | 179 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonMask.cpp | 2 |
9 files changed, 2 insertions, 1265 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index c86fa2b..54c3cea 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -457,7 +457,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { TII = ST->getInstrInfo(); const Function &F = MF.getFunction(); - bool OptForSize = F.hasFnAttribute(Attribute::OptimizeForSize); + bool OptForSize = F.hasOptSize(); // Combine aggressively (for code size) ShouldCombineAggressively = diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td index f0ca908..6050649 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td @@ -336,5 +336,4 @@ class InstDuplex<bits<4> iClass, string cstr = ""> : Instruction, // Instruction Classes Definitions - //===----------------------------------------------------------------------===// -include "HexagonInstrFormatsV60.td" include "HexagonInstrFormatsV65.td" diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td deleted file mode 100644 index 86a8218..0000000 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ /dev/null @@ -1,21 +0,0 @@ -//==- HexagonInstrFormatsV60.td - Hexagon Instruction Formats -*- tablegen -==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V60 instruction classes in TableGen format. -// -//===----------------------------------------------------------------------===// - -//----------------------------------------------------------------------------// -// Instruction Classes Definitions + -//----------------------------------------------------------------------------// - -class CVI_VA_Resource<dag outs, dag ins, string asmstr, - list<dag> pattern = [], string cstr = "", - InstrItinClass itin = CVI_VA> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>, - OpcodeHexagon, Requires<[HasV60, UseHVX]>; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td index 246a1d3..85b826f 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td @@ -20,11 +20,6 @@ // Instruction Classes Definitions + //----------------------------------------------------------------------------// -class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr, - list<dag> pattern = [], string cstr = "", - InstrItinClass itin = CVI_VA> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>; - class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = CVI_GATHER_PSEUDO> diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td deleted file mode 100644 index 44f39a3..0000000 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ /dev/null @@ -1,414 +0,0 @@ -//===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>; -def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>; -def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>; - -// Vector reduce add unsigned halfwords -def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>; - -def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; -def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; -def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; -def: T_PP_pat<A2_minup, int_hexagon_A2_minup>; -def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>; -def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>; - -// Vector reduce multiply word by signed half (32x16) -//Rdd=vrmpyweh(Rss,Rtt)[:<<1] -def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>; -def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>; -def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>; - -//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] -def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>; -def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>; -def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>; - -// Vector multiply halfwords, signed by unsigned -// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat -def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>; -def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>; - -// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat -def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>; -def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>; - -// Vector polynomial multiply halfwords -// Rdd=vpmpyh(Rs,Rt) -def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>; -// Rxx[^]=vpmpyh(Rs,Rt) -def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>; - -// Polynomial multiply words -// Rdd=pmpyw(Rs,Rt) -def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>; -// Rxx^=pmpyw(Rs,Rt) -def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>; - -//Rxx^=asr(Rss,Rt) -def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>; -//Rxx^=asl(Rss,Rt) -def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>; -//Rxx^=lsr(Rss,Rt) -def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>; -//Rxx^=lsl(Rss,Rt) -def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>; - -// Multiply and use upper result -def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>; -def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>; -def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>; -def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>; -def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>; - -def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>; -def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>; - -// Vector reduce add unsigned halfwords -def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>; - -def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>; -def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>; -def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>; - -def: T_Q_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>; -def: T_Q_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>; -def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>; - -def : T_Q_PI_pat<A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi>; -def : T_Q_PI_pat<A4_vcmpbgti, int_hexagon_A4_vcmpbgti>; -def : T_Q_PI_pat<A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui>; -def : T_Q_PI_pat<A4_vcmpheqi, int_hexagon_A4_vcmpheqi>; -def : T_Q_PI_pat<A4_vcmphgti, int_hexagon_A4_vcmphgti>; -def : T_Q_PI_pat<A4_vcmphgtui, int_hexagon_A4_vcmphgtui>; -def : T_Q_PI_pat<A4_vcmpweqi, int_hexagon_A4_vcmpweqi>; -def : T_Q_PI_pat<A4_vcmpwgti, int_hexagon_A4_vcmpwgti>; -def : T_Q_PI_pat<A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui>; -def : T_Q_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>; - -def : T_Q_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>; -def : T_Q_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>; -def : T_Q_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>; -def : T_Q_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>; -def : T_Q_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>; -def : T_Q_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>; - -def : T_Q_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>; -def : T_Q_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>; -def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>; - -def : T_Q_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>; -def : T_Q_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>; -def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>; - -def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>; -def : T_Q_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>; - -def : T_RRR_pat <M4_mpyrr_addr, int_hexagon_M4_mpyrr_addr>; -def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>; -def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>; -def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>; -def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>; -def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>; -def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>; - -// Complex multiply 32x16 -def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>; -def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>; - -def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>; -def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>; - -def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>; -def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>; - -// Complex add/sub halfwords/words -def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>; -def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>; -def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>; -def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>; - -def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>; -def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>; - -// Extract bitfield -def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>; -def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>; -def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>; -def : T_RII_pat <S4_extract, int_hexagon_S4_extract>; - -// Vector conditional negate -// Rdd=vcnegh(Rss,Rt) -def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>; - -// Shift an immediate left by register amount -def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>; - -// Vector reduce maximum halfwords -def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>; -def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>; - -// Vector reduce maximum words -def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>; -def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>; - -// Vector reduce minimum halfwords -def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>; -def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>; - -// Vector reduce minimum words -def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>; -def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>; - -// Rotate and reduce bytes -def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, - u2_0ImmPred:$src3), - (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>; - -// Rotate and reduce bytes with accumulation -// Rxx+=vrcrotate(Rss,Rt,#u2) -def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, - IntRegs:$src3, u2_0ImmPred:$src4), - (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, - IntRegs:$src3, u2_0ImmPred:$src4)>; - -// Vector conditional negate -def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>; - -// Logical xor with xor accumulation -def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>; - -// ALU64 - Vector min/max byte -def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>; -def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>; - -// Shift and add/sub/and/or -def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>; -def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>; -def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>; -def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>; -def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>; -def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>; -def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>; -def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>; - -// Split bitfield -def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>; -def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>; - -def: T_RR_pat<S4_parity, int_hexagon_S4_parity>; - -def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>; -def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>; - -def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>; -def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>; -def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>; - -//******************************************************************* -// ALU32/ALU -//******************************************************************* - -// ALU32 / ALU / Logical Operations. -def: T_RR_pat<A4_andn, int_hexagon_A4_andn>; -def: T_RR_pat<A4_orn, int_hexagon_A4_orn>; - -//******************************************************************* -// ALU32/PERM -//******************************************************************* - -// Combine Words Into Doublewords. -def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>; -def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>; - -//******************************************************************* -// ALU32/PRED -//******************************************************************* - -// Compare -def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>; -def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>; -def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>; - -// Compare To General Register. -def: T_Q_RR_pat<C4_cmpneq, int_hexagon_C4_cmpneq>; -def: T_Q_RR_pat<C4_cmplte, int_hexagon_C4_cmplte>; -def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>; - -def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>; -def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>; - -def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>; -def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>; - -//******************************************************************* -// CR -//******************************************************************* - -// CR / Logical Operations On Predicates. -def: T_Q_QQQ_pat<C4_and_and, int_hexagon_C4_and_and>; -def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>; -def: T_Q_QQQ_pat<C4_and_or, int_hexagon_C4_and_or>; -def: T_Q_QQQ_pat<C4_and_orn, int_hexagon_C4_and_orn>; -def: T_Q_QQQ_pat<C4_or_and, int_hexagon_C4_or_and>; -def: T_Q_QQQ_pat<C4_or_andn, int_hexagon_C4_or_andn>; -def: T_Q_QQQ_pat<C4_or_or, int_hexagon_C4_or_or>; -def: T_Q_QQQ_pat<C4_or_orn, int_hexagon_C4_or_orn>; - -//******************************************************************* -// XTYPE/ALU -//******************************************************************* - -// Add And Accumulate. - -def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>; -def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>; - - -// XTYPE / ALU / Logical-logical Words. -def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>; -def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>; -def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>; -def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>; -def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>; -def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>; -def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>; -def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>; -def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>; -def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>; -def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>; - -def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>; -def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>; -def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>; - -// Modulo wrap. -def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>; - -// Arithmetic/Convergent round -// Rd=[cround|round](Rs,Rt)[:sat] -// Rd=[cround|round](Rs,#u5)[:sat] -def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>; -def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>; - -def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>; -def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>; - -def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>; -def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>; - -def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>; - -//Rdd[+]=vrmpybsu(Rss,Rtt) -//Rdd[+]=vrmpybuu(Rss,Rtt) -def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>; -def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>; - -def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>; - -def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>; -def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>; -//Rxx+=vdmpybsu(Rss,Rtt):sat -def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>; - -// Vector multiply bytes -// Rdd=vmpyb[s]u(Rs,Rt) -def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>; -def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>; - -// Rxx+=vmpyb[s]u(Rs,Rt) -def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>; -def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>; - -// Rd=vaddhub(Rss,Rtt):sat -def : T_PP_pat <A5_vaddhubs, int_hexagon_A5_vaddhubs>; - -def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>; -def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>; -def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>; -def : T_FF_pat<F2_sfmax, int_hexagon_F2_sfmax>; -def : T_FF_pat<F2_sfmin, int_hexagon_F2_sfmin>; - -def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>; -def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>; -def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>; - -def : T_Q_QQ_pat<C4_fastcorner9, int_hexagon_C4_fastcorner9>; -def : T_Q_QQ_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>; - -def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>; -def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>; - -def : T_PI_pat <S2_asr_i_p_rnd, int_hexagon_S2_asr_i_p_rnd>; -def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax, - int_hexagon_S2_asr_i_p_rnd_goodsyntax>; - -def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax, - int_hexagon_S5_asrhub_rnd_sat_goodsyntax>; - -def : T_PI_pat <S5_vasrhrnd_goodsyntax, int_hexagon_S5_vasrhrnd_goodsyntax>; - -def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>; -def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>; -def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>; -def : T_FFF_pat <F2_sffms_lib, int_hexagon_F2_sffms_lib>; -def : T_FFFQ_pat <F2_sffma_sc, int_hexagon_F2_sffma_sc>; - -// Compare floating-point value -def : T_Q_FF_pat <F2_sfcmpge, int_hexagon_F2_sfcmpge>; -def : T_Q_FF_pat <F2_sfcmpuo, int_hexagon_F2_sfcmpuo>; -def : T_Q_FF_pat <F2_sfcmpeq, int_hexagon_F2_sfcmpeq>; -def : T_Q_FF_pat <F2_sfcmpgt, int_hexagon_F2_sfcmpgt>; - -def : T_Q_DD_pat <F2_dfcmpeq, int_hexagon_F2_dfcmpeq>; -def : T_Q_DD_pat <F2_dfcmpgt, int_hexagon_F2_dfcmpgt>; -def : T_Q_DD_pat <F2_dfcmpge, int_hexagon_F2_dfcmpge>; -def : T_Q_DD_pat <F2_dfcmpuo, int_hexagon_F2_dfcmpuo>; - -// Create floating-point value -def : T_I_pat <F2_sfimm_p, int_hexagon_F2_sfimm_p>; -def : T_I_pat <F2_sfimm_n, int_hexagon_F2_sfimm_n>; -def : T_I_pat <F2_dfimm_p, int_hexagon_F2_dfimm_p>; -def : T_I_pat <F2_dfimm_n, int_hexagon_F2_dfimm_n>; - -def : T_Q_DI_pat <F2_dfclass, int_hexagon_F2_dfclass>; -def : T_Q_FI_pat <F2_sfclass, int_hexagon_F2_sfclass>; -def : T_F_pat <F2_conv_sf2df, int_hexagon_F2_conv_sf2df>; -def : T_D_pat <F2_conv_df2sf, int_hexagon_F2_conv_df2sf>; -def : T_R_pat <F2_conv_uw2sf, int_hexagon_F2_conv_uw2sf>; -def : T_R_pat <F2_conv_uw2df, int_hexagon_F2_conv_uw2df>; -def : T_R_pat <F2_conv_w2sf, int_hexagon_F2_conv_w2sf>; -def : T_R_pat <F2_conv_w2df, int_hexagon_F2_conv_w2df>; -def : T_P_pat <F2_conv_ud2sf, int_hexagon_F2_conv_ud2sf>; -def : T_P_pat <F2_conv_ud2df, int_hexagon_F2_conv_ud2df>; -def : T_P_pat <F2_conv_d2sf, int_hexagon_F2_conv_d2sf>; -def : T_P_pat <F2_conv_d2df, int_hexagon_F2_conv_d2df>; -def : T_F_pat <F2_conv_sf2uw, int_hexagon_F2_conv_sf2uw>; -def : T_F_pat <F2_conv_sf2w, int_hexagon_F2_conv_sf2w>; -def : T_F_pat <F2_conv_sf2ud, int_hexagon_F2_conv_sf2ud>; -def : T_F_pat <F2_conv_sf2d, int_hexagon_F2_conv_sf2d>; -def : T_D_pat <F2_conv_df2uw, int_hexagon_F2_conv_df2uw>; -def : T_D_pat <F2_conv_df2w, int_hexagon_F2_conv_df2w>; -def : T_D_pat <F2_conv_df2ud, int_hexagon_F2_conv_df2ud>; -def : T_D_pat <F2_conv_df2d, int_hexagon_F2_conv_df2d>; -def : T_F_pat <F2_conv_sf2uw_chop, int_hexagon_F2_conv_sf2uw_chop>; -def : T_F_pat <F2_conv_sf2w_chop, int_hexagon_F2_conv_sf2w_chop>; -def : T_F_pat <F2_conv_sf2ud_chop, int_hexagon_F2_conv_sf2ud_chop>; -def : T_F_pat <F2_conv_sf2d_chop, int_hexagon_F2_conv_sf2d_chop>; -def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>; -def : T_D_pat <F2_conv_df2w_chop, int_hexagon_F2_conv_df2w_chop>; -def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>; -def : T_D_pat <F2_conv_df2d_chop, int_hexagon_F2_conv_df2d_chop>; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td deleted file mode 100644 index 796979e..0000000 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ /dev/null @@ -1,642 +0,0 @@ -//===- HexagonIntrinsicsV60.td - V60 instruction intrinsics -*- tablegen *-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V60 Compiler Intrinsics in TableGen format. -// -//===----------------------------------------------------------------------===// - - -let AddedComplexity = 100 in { -def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))), - (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >; - -def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))), - (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >; - -def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))), - (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >; - -def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))), - (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >; -} - -def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))), - (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))), - (v64i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))), - (v64i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))), - (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))), - (v32i16 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v64i8 (bitconvert (v64i1 HvxQR:$src1))), - (v64i8 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))), - (v128i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v128i1 (bitconvert (v64i16 HvxVR:$src1))), - (v128i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v128i1 (bitconvert (v128i8 HvxVR:$src1))), - (v128i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v32i32 (bitconvert (v128i1 HvxQR:$src1))), - (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v64i16 (bitconvert (v128i1 HvxQR:$src1))), - (v64i16 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; - -def : Pat <(v128i8 (bitconvert (v128i1 HvxQR:$src1))), - (v128i8 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; - -let AddedComplexity = 140 in { -def : Pat <(store (v64i1 HvxQR:$src1), (i32 IntRegs:$addr)), - (V6_vS32b_ai IntRegs:$addr, 0, - (v16i32 (V6_vandqrt (v64i1 HvxQR:$src1), - (A2_tfrsi 0x01010101))))>; - -def : Pat <(v64i1 (load (i32 IntRegs:$addr))), - (v64i1 (V6_vandvrt - (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; - -def : Pat <(store (v128i1 HvxQR:$src1), (i32 IntRegs:$addr)), - (V6_vS32b_ai IntRegs:$addr, 0, - (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), - (A2_tfrsi 0x01010101))))>; - -def : Pat <(v128i1 (load (i32 IntRegs:$addr))), - (v128i1 (V6_vandvrt - (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; -} - -multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1), - (MI IntRegs:$src1)>; -} - -multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1), - (MI HvxVR:$src1)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1), - (MI HvxVR:$src1)>; -} - -multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1), - (MI HvxWR:$src1)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1), - (MI HvxWR:$src1)>; -} - -multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1), - (MI HvxQR:$src1)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1), - (MI HvxQR:$src1)>; -} - -multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, IntRegs:$src2), - (MI HvxWR:$src1, IntRegs:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2), - (MI HvxWR:$src1, IntRegs:$src2)>; -} - -multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), - (MI HvxVR:$src1, IntRegs:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2), - (MI HvxVR:$src1, IntRegs:$src2)>; -} - -multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxVR:$src2), - (MI HvxWR:$src1, HvxVR:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2), - (MI HvxWR:$src1, HvxVR:$src2)>; -} - -multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxWR:$src2), - (MI HvxWR:$src1, HvxWR:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2), - (MI HvxWR:$src1, HvxWR:$src2)>; -} - -multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), - (MI HvxVR:$src1, HvxVR:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), - (MI HvxVR:$src1, HvxVR:$src2)>; -} - -multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), - (MI HvxQR:$src1, IntRegs:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), - (MI HvxQR:$src1, IntRegs:$src2)>; -} - -multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), - (MI HvxQR:$src1, HvxQR:$src2)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), - (MI HvxQR:$src1, HvxQR:$src2)>; -} - -multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, - IntRegs:$src3), - (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; -} - -multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - IntRegs:$src3), - (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; -} - -multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, - IntRegs:$src3), - (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>; -} - -multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), - (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2, - IntRegs:$src3), - (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>; -} - -multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - HvxVR:$src3), - (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; -} - -multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, - HvxVR:$src3), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; -} - -multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, - HvxVR:$src3), - (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; -} - -multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, - IntRegs:$src3), - (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; -} - - -multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, - IntRegs:$src3), - (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; -} - -multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), - (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, - HvxVR:$src2, imm:$src3), - (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; -} - -multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3), - (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, - IntRegs:$src2, imm:$src3), - (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>; -} - -multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4), - (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, - IntRegs:$src3, imm:$src4), - (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; -} - -multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), - (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - HvxVR:$src3, IntRegs:$src4), - (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; -} - -multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; - - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, - HvxVR:$src3, IntRegs:$src4), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; -} - -defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>; -defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>; -defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>; -defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>; -defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>; -defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>; -defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>; -defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>; -defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>; -defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>; -defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>; -defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>; -defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>; -defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>; -defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>; -defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>; -defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>; -defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>; -defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>; -defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>; -defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>; -defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>; -defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>; -defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>; -defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>; -defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>; -defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>; -defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>; -defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>; -defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>; -defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>; -defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>; - -defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>; -defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>; -defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>; -defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>; -defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>; -defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>; -defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>; -defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>; -defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>; -defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>; -defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>; -defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>; -defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>; -defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>; -defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>; -defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>; -defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>; -defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>; -defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>; -defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>; -defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>; -defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>; -defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>; -defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>; -defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>; -defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>; -defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>; -defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>; -defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>; -defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>; -defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>; -defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>; -defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>; -defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>; -defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>; -defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>; -defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>; -defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>; -defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>; -defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>; -defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>; -defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>; -defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>; -defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>; -defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>; -defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>; -defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>; -defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>; -defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>; -defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>; -defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>; -defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>; -defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>; -defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>; -defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>; -defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>; -defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>; -defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>; -defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>; -defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>; -defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>; -defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>; -defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>; -defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>; - -defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>; -defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>; -defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>; -defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>; -defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>; -defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>; -defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>; -defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>; -defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>; -defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>; -defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>; - -defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>; -defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>; - -defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>; -defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>; -defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>; -defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>; - -defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>; -defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>; -defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>; -defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>; -defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>; -defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>; -defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>; -defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>; - -defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>; -defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>; -defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>; -defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>; -defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>; -defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>; -defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>; -defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>; -defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>; -defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>; -defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>; -defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>; -defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>; -defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>; -defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>; - -// Compare instructions -defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>; -defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>; -defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>; -defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>; -defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>; -defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>; -defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>; -defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>; -defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>; -defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>; -defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>; -defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>; -defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>; -defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>; -defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>; -defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>; -defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>; -defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>; -defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>; -defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>; -defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>; -defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>; -defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>; -defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>; -defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>; -defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>; -defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>; - -defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>; -defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>; -defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>; -defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>; -defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>; -defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>; -defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>; -defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>; -defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>; -defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>; -defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>; -defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>; -defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>; -defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>; -defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>; -defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>; -defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>; -defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>; -defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>; -defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>; -defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>; -defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>; -defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>; -defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>; -defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>; -defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>; -defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>; -defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>; -defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>; -defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>; -defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>; -defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>; -defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>; -defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>; -defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>; -defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>; -defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>; -defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>; -defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>; -defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>; -defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>; -defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>; -defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>; -defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>; -defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>; -defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>; - -defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>; -defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>; -defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>; -defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>; -defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>; -defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>; -defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>; -defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>; -defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>; -defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>; -defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>; -defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>; - -defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>; -defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>; -defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>; -defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>; -defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>; -defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>; -defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>; -defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>; -defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>; -defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>; -defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>; -defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>; -defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>; -defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>; -defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>; -defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>; -defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>; -defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>; -defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>; -defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>; -defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>; -defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>; -defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>; - -defm : T_W_pat <V6_lo, int_hexagon_V6_lo>; -defm : T_W_pat <V6_hi, int_hexagon_V6_hi>; -defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>; - -defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>; -defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>; -defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>; - -defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>; -defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>; -defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>; - -// assembler mapped. -//defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>; -// not present earlier.. need to add intrinsic -defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>; -defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>; -defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>; -defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>; -defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>; -defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>; -defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>; -defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>; -defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>; - -defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>; -defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>; - -defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>; -defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>; -defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>; -defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>; - -defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>; -defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>; -defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>; -defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>; -defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>; -defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>; -defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>; -defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>; -defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>; -defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>; -defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>; -defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>; -defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>; -defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>; -defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>; -defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>; -defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>; - -defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>; -defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; -defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>; -defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>; -defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>; -defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>; - -defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>; -defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>; -defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>; -defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>; - -defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; -def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>; -def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>; -def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>; -def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>; -def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>; -def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>; -def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>; -def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>; -def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>; -def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>; -def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>; -def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>; - -defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>; -defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>; - -//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; - -def: Pat<(v64i16 (trunc v64i32:$Vdd)), - (v64i16 (V6_vpackwh_sat - (v32i32 (V6_hi HvxWR:$Vdd)), - (v32i32 (V6_lo HvxWR:$Vdd))))>; - -def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>; -def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>; - diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index c2eb24b..c34eecd 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -38,7 +38,6 @@ #include "llvm/IR/InstrTypes.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" -#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/IntrinsicsHexagon.h" #include "llvm/IR/Module.h" diff --git a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td deleted file mode 100644 index 2fcefe6..0000000 --- a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td +++ /dev/null @@ -1,179 +0,0 @@ -//===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), - (MI HvxVR:$src1, IntRegs:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2), - (MI HvxVR:$src1, IntRegs:$src2)>; -} - -multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - IntRegsLow8:$src3), - (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>; -} - -multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), - (MI HvxVR:$src1, HvxVR:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), - (MI HvxVR:$src1, HvxVR:$src2)>; -} - -multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxWR:$src2), - (MI HvxWR:$src1, HvxWR:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2), - (MI HvxWR:$src1, HvxWR:$src2)>; -} - -multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, - HvxVR:$src3), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; -} - -multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, IntRegs:$src2), - (MI HvxWR:$src1, IntRegs:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2), - (MI HvxWR:$src1, IntRegs:$src2)>; -} - -multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, - IntRegs:$src3), - (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; -} - -multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - IntRegs:$src3), - (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; -} - -multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), - (MI HvxQR:$src1, IntRegs:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), - (MI HvxQR:$src1, IntRegs:$src2)>; -} - -multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, - IntRegs:$src3), - (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; -} - -multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, HvxVR:$src2), - (MI HvxQR:$src1, HvxVR:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2), - (MI HvxQR:$src1, HvxVR:$src2)>; -} - -multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID IntRegs:$src1), - (MI IntRegs:$src1)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1), - (MI IntRegs:$src1)>; -} - -multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), - (MI HvxQR:$src1, HvxQR:$src2)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), - (MI HvxQR:$src1, HvxQR:$src2)>; -} - -multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), - (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - imm:$src3), - (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; -} - -multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), - (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, - HvxVR:$src3, imm:$src4), - (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; -} - -multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { - def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; - def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, - HvxVR:$src3, imm:$src4), - (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; -} - -def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>; -def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>; -def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>; -def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>; -def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>; - -defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>; -defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>; -defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>; -defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>; -defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>; -defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>; -defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>; -defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>; -defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>; -defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>; -defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>; -defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>; -defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>; -defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>; -defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>; -defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>; -defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>; -defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>; -defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>; -defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>; -defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>; -defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>; -defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>; -defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>; -defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>; -defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>; -defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>; -defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>; -defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>; -defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>; -defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>; -defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>; -defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>; -defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>; -defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>; -defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>; -defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>; -defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>; -defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>; -defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>; -defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>; -defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>; -defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>; -defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>; -defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>; diff --git a/llvm/lib/Target/Hexagon/HexagonMask.cpp b/llvm/lib/Target/Hexagon/HexagonMask.cpp index 6eccf80..9d7776d 100644 --- a/llvm/lib/Target/Hexagon/HexagonMask.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMask.cpp @@ -76,7 +76,7 @@ bool HexagonMask::runOnMachineFunction(MachineFunction &MF) { HII = HST.getInstrInfo(); const Function &F = MF.getFunction(); - if (!F.hasFnAttribute(Attribute::OptimizeForSize)) + if (!F.hasOptSize()) return false; // Mask instruction is available only from v66 if (!HST.hasV66Ops()) |