1 files changed, 6 insertions, 16 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 980e585..d35a022 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3117,30 +3117,20 @@ static bool isCttzOpc(unsigned Opc) {
 SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
                                                SelectionDAG &DAG) const {
   auto SL = SDLoc(Op);
-  auto Opc = Op.getOpcode();
   auto Arg = Op.getOperand(0u);
   auto ResultVT = Op.getValueType();
 
   if (ResultVT != MVT::i8 && ResultVT != MVT::i16)
     return {};
 
-  assert(isCtlzOpc(Opc));
+  assert(isCtlzOpc(Op.getOpcode()));
   assert(ResultVT == Arg.getValueType());
 
-  const uint64_t NumBits = ResultVT.getFixedSizeInBits();
-  SDValue NumExtBits = DAG.getConstant(32u - NumBits, SL, MVT::i32);
-  SDValue NewOp;
-
-  if (Opc == ISD::CTLZ_ZERO_UNDEF) {
-    NewOp = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Arg);
-    NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, NumExtBits);
-    NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp);
-  } else {
-    NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg);
-    NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp);
-    NewOp = DAG.getNode(ISD::SUB, SL, MVT::i32, NewOp, NumExtBits);
-  }
-
+  auto const LeadingZeroes = 32u - ResultVT.getFixedSizeInBits();
+  auto SubVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32);
+  auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg);
+  NewOp = DAG.getNode(Op.getOpcode(), SL, MVT::i32, NewOp);
+  NewOp = DAG.getNode(ISD::SUB, SL, MVT::i32, NewOp, SubVal);
   return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp);
 }