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-rw-r--r--llvm/lib/CodeGen/CodeGen.cpp2
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp211
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.h36
3 files changed, 187 insertions, 62 deletions
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 046a3ee..6311ec2 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -112,7 +112,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6b494a2..6dba1bd 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -43,8 +43,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -55,6 +57,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
@@ -146,11 +149,160 @@ static cl::opt<unsigned> SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::ID;
+namespace {
+class RAGreedyLegacy : public MachineFunctionPass {
+ RegAllocFilterFunc F;
-INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
- "Greedy Register Allocator", false, false)
+public:
+ RAGreedyLegacy(const RegAllocFilterFunc F = nullptr);
+
+ static char ID;
+ /// Return the pass name.
+ StringRef getPassName() const override { return "Greedy Register Allocator"; }
+
+ /// RAGreedy analysis usage.
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ /// Perform register allocation.
+ bool runOnMachineFunction(MachineFunction &mf) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // end anonymous namespace
+
+RAGreedyLegacy::RAGreedyLegacy(const RegAllocFilterFunc F)
+ : MachineFunctionPass(ID), F(F) {
+ initializeRAGreedyLegacyPass(*PassRegistry::getPassRegistry());
+}
+
+struct RAGreedy::RequiredAnalyses {
+ VirtRegMap *VRM = nullptr;
+ LiveIntervals *LIS = nullptr;
+ LiveRegMatrix *LRM = nullptr;
+ SlotIndexes *Indexes = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+ MachineDominatorTree *DomTree = nullptr;
+ MachineLoopInfo *Loops = nullptr;
+ MachineOptimizationRemarkEmitter *ORE = nullptr;
+ EdgeBundles *Bundles = nullptr;
+ SpillPlacement *SpillPlacer = nullptr;
+ LiveDebugVariables *DebugVars = nullptr;
+
+ // Used by InlineSpiller
+ LiveStacks *LSS;
+ // Proxies for eviction and priority advisors
+ RegAllocEvictionAdvisorProvider *EvictProvider;
+ RegAllocPriorityAdvisorProvider *PriorityProvider;
+
+ RequiredAnalyses() = delete;
+ RequiredAnalyses(Pass &P);
+ RequiredAnalyses(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+RAGreedy::RAGreedy(RequiredAnalyses &Analyses, const RegAllocFilterFunc F)
+ : RegAllocBase(F) {
+ VRM = Analyses.VRM;
+ LIS = Analyses.LIS;
+ Matrix = Analyses.LRM;
+ Indexes = Analyses.Indexes;
+ MBFI = Analyses.MBFI;
+ DomTree = Analyses.DomTree;
+ Loops = Analyses.Loops;
+ ORE = Analyses.ORE;
+ Bundles = Analyses.Bundles;
+ SpillPlacer = Analyses.SpillPlacer;
+ DebugVars = Analyses.DebugVars;
+ LSS = Analyses.LSS;
+ EvictProvider = Analyses.EvictProvider;
+ PriorityProvider = Analyses.PriorityProvider;
+}
+
+void RAGreedyPass::printPipeline(
+ raw_ostream &OS,
+ function_ref<StringRef(StringRef)> MapClassName2PassName) const {
+ StringRef FilterName = Opts.FilterName.empty() ? "all" : Opts.FilterName;
+ OS << "greedy<" << FilterName << '>';
+}
+
+RAGreedy::RequiredAnalyses::RequiredAnalyses(
+ MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) {
+ LIS = &MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ LRM = &MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ LSS = &MFAM.getResult<LiveStacksAnalysis>(MF);
+ Indexes = &MFAM.getResult<SlotIndexesAnalysis>(MF);
+ MBFI = &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF);
+ DomTree = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ ORE = &MFAM.getResult<MachineOptimizationRemarkEmitterAnalysis>(MF);
+ Loops = &MFAM.getResult<MachineLoopAnalysis>(MF);
+ Bundles = &MFAM.getResult<EdgeBundlesAnalysis>(MF);
+ SpillPlacer = &MFAM.getResult<SpillPlacementAnalysis>(MF);
+ DebugVars = &MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+ EvictProvider = MFAM.getResult<RegAllocEvictionAdvisorAnalysis>(MF).Provider;
+ PriorityProvider =
+ MFAM.getResult<RegAllocPriorityAdvisorAnalysis>(MF).Provider;
+ VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
+}
+
+PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ RAGreedy::RequiredAnalyses Analyses(MF, MFAM);
+ RAGreedy Impl(Analyses, Opts.Filter);
+
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<MachineBlockFrequencyAnalysis>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveDebugVariablesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ PA.preserve<VirtRegMapAnalysis>();
+ PA.preserve<LiveRegMatrixAnalysis>();
+ return PA;
+}
+
+RAGreedy::RequiredAnalyses::RequiredAnalyses(Pass &P) {
+ VRM = &P.getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ LIS = &P.getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ LSS = &P.getAnalysis<LiveStacksWrapperLegacy>().getLS();
+ LRM = &P.getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ Indexes = &P.getAnalysis<SlotIndexesWrapperPass>().getSI();
+ MBFI = &P.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
+ DomTree = &P.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ ORE = &P.getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
+ Loops = &P.getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ Bundles = &P.getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
+ SpillPlacer = &P.getAnalysis<SpillPlacementWrapperLegacy>().getResult();
+ DebugVars = &P.getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+ EvictProvider =
+ &P.getAnalysis<RegAllocEvictionAdvisorAnalysisLegacy>().getProvider();
+ PriorityProvider =
+ &P.getAnalysis<RegAllocPriorityAdvisorAnalysisLegacy>().getProvider();
+}
+
+bool RAGreedyLegacy::runOnMachineFunction(MachineFunction &MF) {
+ RAGreedy::RequiredAnalyses Analyses(*this);
+ RAGreedy Impl(Analyses, F);
+ return Impl.run(MF);
+}
+
+char RAGreedyLegacy::ID = 0;
+char &llvm::RAGreedyLegacyID = RAGreedyLegacy::ID;
+
+INITIALIZE_PASS_BEGIN(RAGreedyLegacy, "greedy", "Greedy Register Allocator",
+ false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -166,8 +318,8 @@ INITIALIZE_PASS_DEPENDENCY(SpillPlacementWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
INITIALIZE_PASS_DEPENDENCY(RegAllocEvictionAdvisorAnalysisLegacy)
INITIALIZE_PASS_DEPENDENCY(RegAllocPriorityAdvisorAnalysisLegacy)
-INITIALIZE_PASS_END(RAGreedy, "greedy",
- "Greedy Register Allocator", false, false)
+INITIALIZE_PASS_END(RAGreedyLegacy, "greedy", "Greedy Register Allocator",
+ false, false)
#ifndef NDEBUG
const char *const RAGreedy::StageName[] = {
@@ -186,17 +338,14 @@ const char *const RAGreedy::StageName[] = {
const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
FunctionPass* llvm::createGreedyRegisterAllocator() {
- return new RAGreedy();
+ return new RAGreedyLegacy();
}
FunctionPass *llvm::createGreedyRegisterAllocator(RegAllocFilterFunc Ftor) {
- return new RAGreedy(Ftor);
+ return new RAGreedyLegacy(Ftor);
}
-RAGreedy::RAGreedy(RegAllocFilterFunc F)
- : MachineFunctionPass(ID), RegAllocBase(F) {}
-
-void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
+void RAGreedyLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
@@ -1057,7 +1206,8 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around region", &errs());
+ MF->verify(LIS, Indexes, "After splitting live range around region",
+ &errs());
}
MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg,
@@ -1326,7 +1476,8 @@ MCRegister RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around basic blocks", &errs());
+ MF->verify(LIS, Indexes, "After splitting live range around basic blocks",
+ &errs());
return MCRegister();
}
@@ -2524,7 +2675,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
DebugVars->splitRegister(r, LRE.regs(), *LIS);
if (VerifyEnabled)
- MF->verify(this, "After spilling", &errs());
+ MF->verify(LIS, Indexes, "After spilling", &errs());
}
// The live virtual register requesting allocation was spilled, so tell
@@ -2717,7 +2868,7 @@ bool RAGreedy::hasVirtRegAlloc() {
return false;
}
-bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
+bool RAGreedy::run(MachineFunction &mf) {
LLVM_DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
<< "********** Function: " << mf.getName() << '\n');
@@ -2725,29 +2876,18 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
TII = MF->getSubtarget().getInstrInfo();
if (VerifyEnabled)
- MF->verify(this, "Before greedy register allocator", &errs());
+ MF->verify(LIS, Indexes, "Before greedy register allocator", &errs());
- RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
- getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
- getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM());
+ RegAllocBase::init(*this->VRM, *this->LIS, *this->Matrix);
// Early return if there is no virtual register to be allocated to a
// physical register.
if (!hasVirtRegAlloc())
return false;
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
// Renumber to get accurate and consistent results from
// SlotIndexes::getApproxInstrDistance.
Indexes->packIndexes();
- MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
- Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
- SpillPlacer = &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
- auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
initializeCSRCost();
@@ -2763,17 +2903,12 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
ExtraInfo.emplace();
- auto &EvictAdvisorProvider =
- getAnalysis<RegAllocEvictionAdvisorAnalysisLegacy>().getProvider();
- EvictAdvisor = EvictAdvisorProvider.getAdvisor(*MF, *this, MBFI, Loops);
-
- PriorityAdvisor = getAnalysis<RegAllocPriorityAdvisorAnalysisLegacy>()
- .getProvider()
- .getAdvisor(*MF, *this, *Indexes);
+ EvictAdvisor = EvictProvider->getAdvisor(*MF, *this, MBFI, Loops);
+ PriorityAdvisor = PriorityProvider->getAdvisor(*MF, *this, *Indexes);
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
SpillerInstance.reset(
- createInlineSpiller({*LIS, LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
+ createInlineSpiller({*LIS, *LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
VRAI->calculateSpillWeightsAndHints();
@@ -2790,7 +2925,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
tryHintsRecoloring();
if (VerifyEnabled)
- MF->verify(this, "Before post optimization", &errs());
+ MF->verify(LIS, Indexes, "Before post optimization", &errs());
postOptimization();
reportStats();
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index d89b93e..7f013d1 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -25,8 +25,9 @@
#include "llvm/CodeGen/LiveDebugVariables.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
+#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SpillPlacement.h"
@@ -56,11 +57,12 @@ class SlotIndexes;
class TargetInstrInfo;
class VirtRegMap;
-class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
- public RegAllocBase,
+class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
private LiveRangeEdit::Delegate {
- // Interface to eviction advisers
public:
+ struct RequiredAnalyses;
+
+ // Interface to eviction advisers
/// Track allocation stage and eviction loop prevention during allocation.
class ExtraRegInfo final {
// RegInfo - Keep additional information about each live range.
@@ -178,6 +180,10 @@ private:
EdgeBundles *Bundles = nullptr;
SpillPlacement *SpillPlacer = nullptr;
LiveDebugVariables *DebugVars = nullptr;
+ LiveStacks *LSS = nullptr; // Used by InlineSpiller
+ // Proxy for the advisors
+ RegAllocEvictionAdvisorProvider *EvictProvider = nullptr;
+ RegAllocPriorityAdvisorProvider *PriorityProvider = nullptr;
// state
std::unique_ptr<Spiller> SpillerInstance;
@@ -281,14 +287,8 @@ private:
bool ReverseLocalAssignment = false;
public:
- RAGreedy(const RegAllocFilterFunc F = nullptr);
-
- /// Return the pass name.
- StringRef getPassName() const override { return "Greedy Register Allocator"; }
+ RAGreedy(RequiredAnalyses &Analyses, const RegAllocFilterFunc F = nullptr);
- /// RAGreedy analysis usage.
- void getAnalysisUsage(AnalysisUsage &AU) const override;
- void releaseMemory() override;
Spiller &spiller() override { return *SpillerInstance; }
void enqueueImpl(const LiveInterval *LI) override;
const LiveInterval *dequeue() override;
@@ -297,19 +297,9 @@ public:
void aboutToRemoveInterval(const LiveInterval &) override;
/// Perform register allocation.
- bool runOnMachineFunction(MachineFunction &mf) override;
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoPHIs);
- }
-
- MachineFunctionProperties getClearedProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
- }
+ bool run(MachineFunction &mf);
- static char ID;
+ void releaseMemory();
private:
MCRegister selectOrSplitImpl(const LiveInterval &,
generated by cgit v1.1 at 2025-08-03 10:45:28 +0000