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-rw-r--r--llvm/lib/CodeGen/CodeGen.cpp2
-rw-r--r--llvm/lib/CodeGen/InlineSpiller.cpp4
-rw-r--r--llvm/lib/CodeGen/LiveDebugVariables.cpp6
-rw-r--r--llvm/lib/CodeGen/LiveIntervals.cpp61
-rw-r--r--llvm/lib/CodeGen/LiveRegMatrix.cpp6
-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp3
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp14
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp8
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp5
-rw-r--r--llvm/lib/CodeGen/ModuloSchedule.cpp6
-rw-r--r--llvm/lib/CodeGen/PHIElimination.cpp5
-rw-r--r--llvm/lib/CodeGen/RegAllocBasic.cpp8
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp8
-rw-r--r--llvm/lib/CodeGen/RegAllocPBQP.cpp8
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.cpp10
-rw-r--r--llvm/lib/CodeGen/RenameIndependentSubregs.cpp8
-rw-r--r--llvm/lib/CodeGen/StackSlotColoring.cpp2
-rw-r--r--llvm/lib/CodeGen/TwoAddressInstructionPass.cpp5
-rw-r--r--llvm/lib/CodeGen/VirtRegMap.cpp8
19 files changed, 104 insertions, 73 deletions
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 98eebd0..a30eaae 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -60,7 +60,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeJMCInstrumenterPass(Registry);
initializeLiveDebugValuesPass(Registry);
initializeLiveDebugVariablesPass(Registry);
- initializeLiveIntervalsPass(Registry);
+ initializeLiveIntervalsWrapperPassPass(Registry);
initializeLiveRangeShrinkPass(Registry);
initializeLiveStacksPass(Registry);
initializeLiveVariablesWrapperPassPass(Registry);
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index dc03f59..6abbf8b 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -131,7 +131,7 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
public:
HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
VirtRegMap &vrm)
- : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
+ : MF(mf), LIS(pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()),
LSS(pass.getAnalysis<LiveStacks>()),
MDT(pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()),
VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
@@ -188,7 +188,7 @@ class InlineSpiller : public Spiller {
public:
InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap &VRM,
VirtRegAuxInfo &VRAI)
- : MF(MF), LIS(Pass.getAnalysis<LiveIntervals>()),
+ : MF(MF), LIS(Pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()),
LSS(Pass.getAnalysis<LiveStacks>()),
MDT(Pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()),
VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 3224bed..d1341f1 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -79,13 +79,13 @@ char LiveDebugVariables::ID = 0;
INITIALIZE_PASS_BEGIN(LiveDebugVariables, DEBUG_TYPE,
"Debug Variable Analysis", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_END(LiveDebugVariables, DEBUG_TYPE,
"Debug Variable Analysis", false, false)
void LiveDebugVariables::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequiredTransitive<LiveIntervals>();
+ AU.addRequiredTransitive<LiveIntervalsWrapperPass>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -1263,7 +1263,7 @@ void LDVImpl::computeIntervals() {
bool LDVImpl::runOnMachineFunction(MachineFunction &mf, bool InstrRef) {
clear();
MF = &mf;
- LIS = &pass.getAnalysis<LiveIntervals>();
+ LIS = &pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS();
TRI = mf.getSubtarget().getRegisterInfo();
LLVM_DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
<< mf.getName() << " **********\n");
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 009aea4..3327080 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -57,14 +57,39 @@ using namespace llvm;
#define DEBUG_TYPE "regalloc"
-char LiveIntervals::ID = 0;
-char &llvm::LiveIntervalsID = LiveIntervals::ID;
-INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals", "Live Interval Analysis",
- false, false)
+AnalysisKey LiveIntervalsAnalysis::Key;
+
+LiveIntervalsAnalysis::Result
+LiveIntervalsAnalysis::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ return Result(MF, MFAM.getResult<SlotIndexesAnalysis>(MF),
+ MFAM.getResult<MachineDominatorTreeAnalysis>(MF));
+}
+
+PreservedAnalyses
+LiveIntervalsPrinterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ OS << "Live intervals for machine function: " << MF.getName() << ":\n";
+ MFAM.getResult<LiveIntervalsAnalysis>(MF).print(OS);
+ return PreservedAnalyses::all();
+}
+
+char LiveIntervalsWrapperPass::ID = 0;
+char &llvm::LiveIntervalsID = LiveIntervalsWrapperPass::ID;
+INITIALIZE_PASS_BEGIN(LiveIntervalsWrapperPass, "liveintervals",
+ "Live Interval Analysis", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
-INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
- "Live Interval Analysis", false, false)
+INITIALIZE_PASS_END(LiveIntervalsWrapperPass, "liveintervals",
+ "Live Interval Analysis", false, false)
+
+bool LiveIntervalsWrapperPass::runOnMachineFunction(MachineFunction &MF) {
+ LIS.Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
+ LIS.DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ LIS.analyze(MF);
+ LLVM_DEBUG(dump());
+ return false;
+}
#ifndef NDEBUG
static cl::opt<bool> EnablePrecomputePhysRegs(
@@ -83,7 +108,7 @@ cl::opt<bool> UseSegmentSetForPhysRegs(
} // end namespace llvm
-void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
+void LiveIntervalsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addPreserved<LiveVariablesWrapperPass>();
AU.addPreservedID(MachineLoopInfoID);
@@ -94,13 +119,13 @@ void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-LiveIntervals::LiveIntervals() : MachineFunctionPass(ID) {
- initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
+LiveIntervalsWrapperPass::LiveIntervalsWrapperPass() : MachineFunctionPass(ID) {
+ initializeLiveIntervalsWrapperPassPass(*PassRegistry::getPassRegistry());
}
-LiveIntervals::~LiveIntervals() { delete LICalc; }
+LiveIntervals::~LiveIntervals() { clear(); }
-void LiveIntervals::releaseMemory() {
+void LiveIntervals::clear() {
// Free the live intervals themselves.
for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
delete VirtRegIntervals[Register::index2VirtReg(i)];
@@ -117,16 +142,14 @@ void LiveIntervals::releaseMemory() {
VNInfoAllocator.Reset();
}
-bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
+void LiveIntervals::analyze(MachineFunction &fn) {
MF = &fn;
MRI = &MF->getRegInfo();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
- DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
if (!LICalc)
- LICalc = new LiveIntervalCalc();
+ LICalc = std::make_unique<LiveIntervalCalc>();
// Allocate space for all virtual registers.
VirtRegIntervals.resize(MRI->getNumVirtRegs());
@@ -141,11 +164,9 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
getRegUnit(i);
}
- LLVM_DEBUG(dump());
- return false;
}
-void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
+void LiveIntervals::print(raw_ostream &OS) const {
OS << "********** INTERVALS **********\n";
// Dump the regunits.
@@ -179,6 +200,10 @@ LLVM_DUMP_METHOD void LiveIntervals::dumpInstrs() const {
}
#endif
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+LLVM_DUMP_METHOD void LiveIntervals::dump() const { print(dbgs()); }
+#endif
+
LiveInterval *LiveIntervals::createInterval(Register reg) {
float Weight = reg.isPhysical() ? huge_valf : 0.0F;
return new LiveInterval(reg, Weight);
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index 6df7e5c..c8c7223 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -38,7 +38,7 @@ STATISTIC(NumUnassigned , "Number of registers unassigned");
char LiveRegMatrix::ID = 0;
INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix",
"Live Register Matrix", false, false)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix",
"Live Register Matrix", false, false)
@@ -47,14 +47,14 @@ LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID) {}
void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
- AU.addRequiredTransitive<LiveIntervals>();
+ AU.addRequiredTransitive<LiveIntervalsWrapperPass>();
AU.addRequiredTransitive<VirtRegMap>();
MachineFunctionPass::getAnalysisUsage(AU);
}
bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
TRI = MF.getSubtarget().getRegisterInfo();
- LIS = &getAnalysis<LiveIntervals>();
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
VRM = &getAnalysis<VirtRegMap>();
unsigned NumRegUnits = TRI->getNumRegUnits();
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 292bfa6..5fe7a9d 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1161,7 +1161,8 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
<< " -- " << printMBBReference(*NMBB) << " -- "
<< printMBBReference(*Succ) << '\n');
- LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
+ auto *LISWrapper = P.getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ LiveIntervals *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
auto *SIWrapper = P.getAnalysisIfAvailable<SlotIndexesWrapperPass>();
SlotIndexes *Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
if (LIS)
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 4460f1f..2488f81f 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -236,7 +236,7 @@ INITIALIZE_PASS_BEGIN(MachinePipeliner, DEBUG_TYPE,
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE,
"Modulo Software Pipelining", false, false)
@@ -437,7 +437,8 @@ bool MachinePipeliner::canPipelineLoop(MachineLoop &L) {
void MachinePipeliner::preprocessPhiNodes(MachineBasicBlock &B) {
MachineRegisterInfo &MRI = MF->getRegInfo();
- SlotIndexes &Slots = *getAnalysis<LiveIntervals>().getSlotIndexes();
+ SlotIndexes &Slots =
+ *getAnalysis<LiveIntervalsWrapperPass>().getLIS().getSlotIndexes();
for (MachineInstr &PI : B.phis()) {
MachineOperand &DefOp = PI.getOperand(0);
@@ -472,8 +473,9 @@ void MachinePipeliner::preprocessPhiNodes(MachineBasicBlock &B) {
bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) {
assert(L.getBlocks().size() == 1 && "SMS works on single blocks only.");
- SwingSchedulerDAG SMS(*this, L, getAnalysis<LiveIntervals>(), RegClassInfo,
- II_setByPragma, LI.LoopPipelinerInfo.get());
+ SwingSchedulerDAG SMS(
+ *this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), RegClassInfo,
+ II_setByPragma, LI.LoopPipelinerInfo.get());
MachineBasicBlock *MBB = L.getHeader();
// The kernel should not include any terminator instructions. These
@@ -501,7 +503,7 @@ void MachinePipeliner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<AAResultsWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
AU.addRequired<MachineOptimizationRemarkEmitterPass>();
AU.addRequired<TargetPassConfig>();
MachineFunctionPass::getAnalysisUsage(AU);
@@ -514,7 +516,7 @@ bool MachinePipeliner::runWindowScheduler(MachineLoop &L) {
Context.MDT = MDT;
Context.PassConfig = &getAnalysis<TargetPassConfig>();
Context.AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
- Context.LIS = &getAnalysis<LiveIntervals>();
+ Context.LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
Context.RegClassInfo->runOnMachineFunction(*MF);
WindowScheduler WS(&Context, L);
return WS.run();
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 50eac1a..a8a1710 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -269,7 +269,7 @@ INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
@@ -285,8 +285,8 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
AU.addRequired<SlotIndexesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
- AU.addRequired<LiveIntervals>();
- AU.addPreserved<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -449,7 +449,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
PassConfig = &getAnalysis<TargetPassConfig>();
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
- LIS = &getAnalysis<LiveIntervals>();
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
if (VerifyScheduling) {
LLVM_DEBUG(LIS->dump());
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 395f5de..d0d3af0 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -316,7 +316,7 @@ namespace {
AU.addUsedIfAvailable<LiveStacks>();
AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
AU.addUsedIfAvailable<SlotIndexesWrapperPass>();
- AU.addUsedIfAvailable<LiveIntervals>();
+ AU.addUsedIfAvailable<LiveIntervalsWrapperPass>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -428,7 +428,8 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
MachineFunctionProperties::Property::TracksDebugUserValues);
if (PASS) {
- LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
+ auto *LISWrapper = PASS->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ LiveInts = LISWrapper ? &LISWrapper->getLIS() : nullptr;
// We don't want to verify LiveVariables if LiveIntervals is available.
auto *LVWrapper = PASS->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
if (!LiveInts)
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
index 8b4a6fe..0f29ebe 100644
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -2764,7 +2764,7 @@ public:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineLoopInfoWrapperPass>();
- AU.addRequired<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
@@ -2775,7 +2775,7 @@ char ModuloScheduleTest::ID = 0;
INITIALIZE_PASS_BEGIN(ModuloScheduleTest, "modulo-schedule-test",
"Modulo Schedule test pass", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_END(ModuloScheduleTest, "modulo-schedule-test",
"Modulo Schedule test pass", false, false)
@@ -2810,7 +2810,7 @@ static void parseSymbolString(StringRef S, int &Cycle, int &Stage) {
}
void ModuloScheduleTest::runOnLoop(MachineFunction &MF, MachineLoop &L) {
- LiveIntervals &LIS = getAnalysis<LiveIntervals>();
+ LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
MachineBasicBlock *BB = L.getTopBlock();
dbgs() << "--- ModuloScheduleTest running on BB#" << BB->getNumber() << "\n";
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index bfd1f74..e392bb8 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -141,7 +141,7 @@ void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
AU.addPreserved<LiveVariablesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
- AU.addPreserved<LiveIntervals>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
@@ -151,7 +151,8 @@ bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
auto *LVWrapper = getAnalysisIfAvailable<LiveVariablesWrapperPass>();
LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
- LIS = getAnalysisIfAvailable<LiveIntervals>();
+ auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
bool Changed = false;
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index 133904c..544bc98 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -131,7 +131,7 @@ INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
INITIALIZE_PASS_DEPENDENCY(LiveStacks)
@@ -177,8 +177,8 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<AAResultsWrapperPass>();
AU.addPreserved<AAResultsWrapperPass>();
- AU.addRequired<LiveIntervals>();
- AU.addPreserved<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
@@ -310,7 +310,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
RegAllocBase::init(getAnalysis<VirtRegMap>(),
- getAnalysis<LiveIntervals>(),
+ getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
getAnalysis<LiveRegMatrix>());
VirtRegAuxInfo VRAI(*MF, *LIS, *VRM,
getAnalysis<MachineLoopInfoWrapperPass>().getLI(),
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 2fdf63e..2006cda 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -156,7 +156,7 @@ INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
"Greedy Register Allocator", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
INITIALIZE_PASS_DEPENDENCY(LiveStacks)
@@ -205,8 +205,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineBlockFrequencyInfo>();
AU.addPreserved<MachineBlockFrequencyInfo>();
- AU.addRequired<LiveIntervals>();
- AU.addPreserved<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addRequired<SlotIndexesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveDebugVariables>();
@@ -2716,7 +2716,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
MF->verify(this, "Before greedy register allocator");
RegAllocBase::init(getAnalysis<VirtRegMap>(),
- getAnalysis<LiveIntervals>(),
+ getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
getAnalysis<LiveRegMatrix>());
// Early return if there is no virtual register to be allocated to a
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index dd7bd380..88e9139 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -121,7 +121,7 @@ public:
RegAllocPBQP(char *cPassID = nullptr)
: MachineFunctionPass(ID), customPassID(cPassID) {
initializeSlotIndexesWrapperPassPass(*PassRegistry::getPassRegistry());
- initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
+ initializeLiveIntervalsWrapperPassPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
}
@@ -546,8 +546,8 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
au.addPreserved<AAResultsWrapperPass>();
au.addRequired<SlotIndexesWrapperPass>();
au.addPreserved<SlotIndexesWrapperPass>();
- au.addRequired<LiveIntervals>();
- au.addPreserved<LiveIntervals>();
+ au.addRequired<LiveIntervalsWrapperPass>();
+ au.addPreserved<LiveIntervalsWrapperPass>();
//au.addRequiredID(SplitCriticalEdgesID);
if (customPassID)
au.addRequiredID(*customPassID);
@@ -791,7 +791,7 @@ void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
}
bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
- LiveIntervals &LIS = getAnalysis<LiveIntervals>();
+ LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
MachineBlockFrequencyInfo &MBFI =
getAnalysis<MachineBlockFrequencyInfo>();
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index c84650b..1c35a88 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -406,7 +406,7 @@ char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
INITIALIZE_PASS_BEGIN(RegisterCoalescer, "register-coalescer",
"Register Coalescer", false, false)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
@@ -588,8 +588,8 @@ bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<AAResultsWrapperPass>();
- AU.addRequired<LiveIntervals>();
- AU.addPreserved<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
@@ -4206,7 +4206,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
const TargetSubtargetInfo &STI = fn.getSubtarget();
TRI = STI.getRegisterInfo();
TII = STI.getInstrInfo();
- LIS = &getAnalysis<LiveIntervals>();
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
if (EnableGlobalCopies == cl::BOU_UNSET)
@@ -4298,5 +4298,5 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
}
void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {
- LIS->print(O, m);
+ LIS->print(O);
}
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 2c4a027..0128f87 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -54,8 +54,8 @@ public:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
- AU.addRequired<LiveIntervals>();
- AU.addPreserved<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addRequired<SlotIndexesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
@@ -115,7 +115,7 @@ char &llvm::RenameIndependentSubregsID = RenameIndependentSubregs::ID;
INITIALIZE_PASS_BEGIN(RenameIndependentSubregs, DEBUG_TYPE,
"Rename Independent Subregisters", false, false)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_END(RenameIndependentSubregs, DEBUG_TYPE,
"Rename Independent Subregisters", false, false)
@@ -390,7 +390,7 @@ bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "Renaming independent subregister live ranges in "
<< MF.getName() << '\n');
- LIS = &getAnalysis<LiveIntervals>();
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
TII = MF.getSubtarget().getInstrInfo();
// Iterate over all vregs. Note that we query getNumVirtRegs() the newly
diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp
index 928ec39..1118287 100644
--- a/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -159,7 +159,7 @@ namespace {
// split into multiple phases based on register class. So, this pass
// may be invoked multiple times requiring it to save these analyses to be
// used by RA later.
- AU.addPreserved<LiveIntervals>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveDebugVariables>();
MachineFunctionPass::getAnalysisUsage(AU);
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index eb6f368..73385fe 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -198,7 +198,7 @@ public:
AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
AU.addPreserved<LiveVariablesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
- AU.addPreserved<LiveIntervals>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
@@ -1764,7 +1764,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
InstrItins = MF->getSubtarget().getInstrItineraryData();
auto *LVWrapper = getAnalysisIfAvailable<LiveVariablesWrapperPass>();
LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
- LIS = getAnalysisIfAvailable<LiveIntervals>();
+ auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
if (auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
AA = &AAPass->getAAResults();
else
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index c2c13ea..4acc4f8 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -229,7 +229,7 @@ char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
"Virtual Register Rewriter", false, false)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
INITIALIZE_PASS_DEPENDENCY(LiveStacks)
INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
@@ -238,8 +238,8 @@ INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
- AU.addRequired<LiveIntervals>();
- AU.addPreserved<LiveIntervals>();
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addRequired<SlotIndexesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveDebugVariables>();
@@ -259,7 +259,7 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
- LIS = &getAnalysis<LiveIntervals>();
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
VRM = &getAnalysis<VirtRegMap>();
DebugVars = &getAnalysis<LiveDebugVariables>();
LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
generated by cgit v1.1 at 2025-08-02 06:05:18 +0000