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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp6
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp41
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h11
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp2
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp144
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp14
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp2
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp21
-rw-r--r--llvm/lib/CodeGen/TargetLoweringBase.cpp3
9 files changed, 244 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 2c7148d..dfc24f0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1153,6 +1153,8 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
case ISD::USUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
+ case ISD::SCMP:
+ case ISD::UCMP:
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -3885,6 +3887,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::USUBSAT:
Results.push_back(TLI.expandAddSubSat(Node, DAG));
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Results.push_back(TLI.expandCMP(Node, DAG));
+ break;
case ISD::SSHLSAT:
case ISD::USHLSAT:
Results.push_back(TLI.expandShlSat(Node, DAG));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index f435a36..a058b50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -236,6 +236,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = PromoteIntRes_CMP(N);
+ break;
+
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -1261,6 +1266,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
return Res;
}
+SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
+ EVT PromotedResultTy =
+ TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ return DAG.getNode(N->getOpcode(), SDLoc(N), PromotedResultTy,
+ N->getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
SDValue Mask = N->getOperand(0);
@@ -1923,6 +1935,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::ROTL:
case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
+
case ISD::FSHL:
case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
@@ -2233,6 +2248,17 @@ SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
ZExtPromotedInteger(N->getOperand(1))), 0);
}
+SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
+ SDValue LHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(0))
+ : SExtPromotedInteger(N->getOperand(0));
+ SDValue RHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(1))
+ : SExtPromotedInteger(N->getOperand(1));
+
+ return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS), 0);
+}
+
SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
ZExtPromotedInteger(N->getOperand(2))), 0);
@@ -2788,6 +2814,9 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::UMIN:
case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
+ case ISD::SCMP:
+ case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
+
case ISD::ADD:
case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
@@ -3285,6 +3314,11 @@ void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
SplitInteger(Result, Lo, Hi);
}
+void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue ExpandedCMP = TLI.expandCMP(N, DAG);
+ SplitInteger(ExpandedCMP, Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue &Lo, SDValue &Hi) {
SDLoc dl(N);
@@ -5194,6 +5228,9 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::RETURNADDR:
case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
+
case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
case ISD::STACKMAP:
Res = ExpandIntOp_STACKMAP(N, OpNo);
@@ -5455,6 +5492,10 @@ SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
}
+SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
+ return TLI.expandCMP(N, DAG);
+}
+
SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
// The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
// surely makes pretty nice problems on 8/16 bit targets. Just truncate this
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 82c39f4..85f947e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -343,6 +343,7 @@ private:
SDValue PromoteIntRes_Overflow(SDNode *N);
SDValue PromoteIntRes_FFREXP(SDNode *N);
SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
+ SDValue PromoteIntRes_CMP(SDNode *N);
SDValue PromoteIntRes_Select(SDNode *N);
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
SDValue PromoteIntRes_SETCC(SDNode *N);
@@ -394,6 +395,7 @@ private:
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_Shift(SDNode *N);
+ SDValue PromoteIntOp_CMP(SDNode *N);
SDValue PromoteIntOp_FunnelShift(SDNode *N);
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
SDValue PromoteIntOp_VP_SIGN_EXTEND(SDNode *N);
@@ -476,6 +478,8 @@ private:
void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CMP (SDNode *N, SDValue &Lo, SDValue &Hi);
+
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -505,6 +509,7 @@ private:
SDValue ExpandIntOp_SETCC(SDNode *N);
SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
SDValue ExpandIntOp_Shift(SDNode *N);
+ SDValue ExpandIntOp_CMP(SDNode *N);
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
SDValue ExpandIntOp_XINT_TO_FP(SDNode *N);
@@ -805,6 +810,7 @@ private:
void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_BinOp(SDNode *N);
+ SDValue ScalarizeVecRes_CMP(SDNode *N);
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
@@ -849,6 +855,7 @@ private:
SDValue ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N);
SDValue ScalarizeVecOp_VECREDUCE(SDNode *N);
SDValue ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N);
+ SDValue ScalarizeVecOp_CMP(SDNode *N);
//===--------------------------------------------------------------------===//
// Vector Splitting Support: LegalizeVectorTypes.cpp
@@ -879,6 +886,7 @@ private:
void SplitVectorResult(SDNode *N, unsigned ResNo);
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_ADDRSPACECAST(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_FFREXP(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi);
@@ -943,6 +951,7 @@ private:
SDValue SplitVecOp_VSETCC(SDNode *N);
SDValue SplitVecOp_FP_ROUND(SDNode *N);
SDValue SplitVecOp_FPOpDifferentTypes(SDNode *N);
+ SDValue SplitVecOp_CMP(SDNode *N);
SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SplitVecOp_VP_CttzElements(SDNode *N);
@@ -1011,6 +1020,7 @@ private:
SDValue WidenVecRes_Ternary(SDNode *N);
SDValue WidenVecRes_Binary(SDNode *N);
+ SDValue WidenVecRes_CMP(SDNode *N);
SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
SDValue WidenVecRes_StrictFP(SDNode *N);
@@ -1030,6 +1040,7 @@ private:
SDValue WidenVecOp_BITCAST(SDNode *N);
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTEND(SDNode *N);
+ SDValue WidenVecOp_CMP(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 340d50d..14b147c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -449,6 +449,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
case ISD::MGATHER:
+ case ISD::SCMP:
+ case ISD::UCMP:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
case ISD::SMULFIX:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 52ef620..532c630 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -173,6 +173,12 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ROTR:
R = ScalarizeVecRes_BinOp(N);
break;
+
+ case ISD::SCMP:
+ case ISD::UCMP:
+ R = ScalarizeVecRes_CMP(N);
+ break;
+
case ISD::FMA:
case ISD::FSHL:
case ISD::FSHR:
@@ -222,6 +228,27 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
LHS.getValueType(), LHS, RHS, N->getFlags());
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_CMP(SDNode *N) {
+ SDLoc DL(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ if (getTypeAction(LHS.getValueType()) ==
+ TargetLowering::TypeScalarizeVector) {
+ LHS = GetScalarizedVector(LHS);
+ RHS = GetScalarizedVector(RHS);
+ } else {
+ EVT VT = LHS.getValueType().getVectorElementType();
+ LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
+ DAG.getVectorIdxConstant(0, DL));
+ RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
+ DAG.getVectorIdxConstant(0, DL));
+ }
+
+ return DAG.getNode(N->getOpcode(), SDLoc(N),
+ N->getValueType(0).getVectorElementType(), LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
SDValue Op1 = GetScalarizedVector(N->getOperand(1));
@@ -775,6 +802,10 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::VECREDUCE_SEQ_FMUL:
Res = ScalarizeVecOp_VECREDUCE_SEQ(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = ScalarizeVecOp_CMP(N);
+ break;
}
// If the result is null, the sub-method took care of registering results etc.
@@ -995,6 +1026,12 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N) {
AccOp, Op, N->getFlags());
}
+SDValue DAGTypeLegalizer::ScalarizeVecOp_CMP(SDNode *N) {
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));
+ SDValue RHS = GetScalarizedVector(N->getOperand(1));
+ return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), LHS, RHS);
+}
+
//===----------------------------------------------------------------------===//
// Result Vector Splitting
//===----------------------------------------------------------------------===//
@@ -1230,6 +1267,10 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
SplitVecRes_TernaryOp(N, Lo, Hi);
break;
+ case ISD::SCMP: case ISD::UCMP:
+ SplitVecRes_CMP(N, Lo, Hi);
+ break;
+
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
case ISD::STRICT_##DAGN:
#include "llvm/IR/ConstrainedOps.def"
@@ -1373,6 +1414,27 @@ void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
{Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags);
}
+void DAGTypeLegalizer::SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
+ if (getTypeAction(LHS.getValueType()) == TargetLowering::TypeSplitVector) {
+ GetSplitVector(LHS, LHSLo, LHSHi);
+ GetSplitVector(RHS, RHSLo, RHSHi);
+ } else {
+ std::tie(LHSLo, LHSHi) = DAG.SplitVector(LHS, dl);
+ std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, dl);
+ }
+
+ EVT SplitResVT = N->getValueType(0).getHalfNumVectorElementsVT(Ctxt);
+ Lo = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSLo, RHSLo);
+ Hi = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSHi, RHSHi);
+}
+
void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
@@ -3103,6 +3165,11 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
Res = SplitVecOp_FPOpDifferentTypes(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = SplitVecOp_CMP(N);
+ break;
+
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
@@ -4104,6 +4171,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_FPOpDifferentTypes(SDNode *N) {
return DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Lo, Hi);
}
+SDValue DAGTypeLegalizer::SplitVecOp_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
+ GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
+ GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
+
+ EVT ResVT = N->getValueType(0);
+ ElementCount SplitOpEC = LHSLo.getValueType().getVectorElementCount();
+ EVT NewResVT =
+ EVT::getVectorVT(Ctxt, ResVT.getVectorElementType(), SplitOpEC);
+
+ SDValue Lo = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSLo, RHSLo);
+ SDValue Hi = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSHi, RHSHi);
+
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
+}
+
SDValue DAGTypeLegalizer::SplitVecOp_FP_TO_XINT_SAT(SDNode *N) {
EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
@@ -4288,6 +4374,11 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
Res = WidenVecRes_Binary(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecRes_CMP(N);
+ break;
+
case ISD::FPOW:
case ISD::FREM:
if (unrollExpandedOp())
@@ -4495,6 +4586,28 @@ SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
{InOp1, InOp2, Mask, N->getOperand(3)}, N->getFlags());
}
+SDValue DAGTypeLegalizer::WidenVecRes_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT OpVT = LHS.getValueType();
+ if (getTypeAction(OpVT) == TargetLowering::TypeWidenVector) {
+ LHS = GetWidenedVector(LHS);
+ RHS = GetWidenedVector(RHS);
+ OpVT = LHS.getValueType();
+ }
+
+ EVT WidenResVT = TLI.getTypeToTransformTo(Ctxt, N->getValueType(0));
+ ElementCount WidenResEC = WidenResVT.getVectorElementCount();
+ if (WidenResEC == OpVT.getVectorElementCount()) {
+ return DAG.getNode(N->getOpcode(), dl, WidenResVT, LHS, RHS);
+ }
+
+ return DAG.UnrollVectorOp(N, WidenResVT.getVectorNumElements());
+}
+
SDValue DAGTypeLegalizer::WidenVecRes_BinaryWithExtraScalarOp(SDNode *N) {
// Binary op widening, but with an extra operand that shouldn't be widened.
SDLoc dl(N);
@@ -6208,6 +6321,11 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
Res = WidenVecOp_EXTEND(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecOp_CMP(N);
+ break;
+
case ISD::FP_EXTEND:
case ISD::STRICT_FP_EXTEND:
case ISD::FP_ROUND:
@@ -6354,6 +6472,32 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
}
}
+SDValue DAGTypeLegalizer::WidenVecOp_CMP(SDNode *N) {
+ SDLoc dl(N);
+
+ EVT OpVT = N->getOperand(0).getValueType();
+ EVT ResVT = N->getValueType(0);
+ SDValue LHS = GetWidenedVector(N->getOperand(0));
+ SDValue RHS = GetWidenedVector(N->getOperand(1));
+
+ // 1. EXTRACT_SUBVECTOR
+ // 2. SIGN_EXTEND/ZERO_EXTEND
+ // 3. CMP
+ LHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, LHS,
+ DAG.getVectorIdxConstant(0, dl));
+ RHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, RHS,
+ DAG.getVectorIdxConstant(0, dl));
+
+ // At this point the result type is guaranteed to be valid, so we can use it
+ // as the operand type by extending it appropriately
+ ISD::NodeType ExtendOpcode =
+ N->getOpcode() == ISD::SCMP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ LHS = DAG.getNode(ExtendOpcode, dl, ResVT, LHS);
+ RHS = DAG.getNode(ExtendOpcode, dl, ResVT, RHS);
+
+ return DAG.getNode(N->getOpcode(), dl, ResVT, LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::WidenVecOp_UnrollVectorOp(SDNode *N) {
// The result (and first input) is legal, but the second input is illegal.
// We can't do much to fix that, so just unroll and let the extracts off of
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 8838cce..453bc71 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7220,6 +7220,20 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1));
return;
}
+ case Intrinsic::scmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
+ setValue(&I, DAG.getNode(ISD::SCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
+ case Intrinsic::ucmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
+ setValue(&I, DAG.getNode(ISD::UCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
case Intrinsic::stacksave: {
SDValue Op = getRoot();
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 12a7b7f..a7555d6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -293,6 +293,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SMAX: return "smax";
case ISD::UMIN: return "umin";
case ISD::UMAX: return "umax";
+ case ISD::SCMP: return "scmp";
+ case ISD::UCMP: return "ucmp";
case ISD::FLDEXP: return "fldexp";
case ISD::STRICT_FLDEXP: return "strict_fldexp";
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 623d2e0..ad957aa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10358,6 +10358,27 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
return DAG.getSelect(dl, VT, Overflow, Result, SumDiff);
}
+SDValue TargetLowering::expandCMP(SDNode *Node, SelectionDAG &DAG) const {
+ unsigned Opcode = Node->getOpcode();
+ SDValue LHS = Node->getOperand(0);
+ SDValue RHS = Node->getOperand(1);
+ EVT VT = LHS.getValueType();
+ EVT ResVT = Node->getValueType(0);
+ EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ SDLoc dl(Node);
+
+ auto LTPredicate = (Opcode == ISD::UCMP ? ISD::SETULT : ISD::SETLT);
+ auto GTPredicate = (Opcode == ISD::UCMP ? ISD::SETUGT : ISD::SETGT);
+
+ SDValue IsLT = DAG.getSetCC(dl, BoolVT, LHS, RHS, LTPredicate);
+ SDValue IsGT = DAG.getSetCC(dl, BoolVT, LHS, RHS, GTPredicate);
+ SDValue SelectZeroOrOne =
+ DAG.getSelect(dl, ResVT, IsGT, DAG.getConstant(1, dl, ResVT),
+ DAG.getConstant(0, dl, ResVT));
+ return DAG.getSelect(dl, ResVT, IsLT, DAG.getConstant(-1, dl, ResVT),
+ SelectZeroOrOne);
+}
+
SDValue TargetLowering::expandShlSat(SDNode *Node, SelectionDAG &DAG) const {
unsigned Opcode = Node->getOpcode();
bool IsSigned = Opcode == ISD::SSHLSAT;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index de53499..ff684c7c 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -938,6 +938,9 @@ void TargetLoweringBase::initActions() {
setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
Expand);
+ // [US]CMP default to expand
+ setOperationAction({ISD::UCMP, ISD::SCMP}, VT, Expand);
+
// Halving adds
setOperationAction(
{ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
generated by cgit v1.1 at 2024-11-13 16:53:42 +0000