diff options
Diffstat (limited to 'llvm/lib/CodeGen')
45 files changed, 95 insertions, 167 deletions
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 41e66bb..e0f7466 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -106,8 +106,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } }; diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp index 618e418..05eed96 100644 --- a/llvm/lib/CodeGen/BreakFalseDeps.cpp +++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp @@ -64,8 +64,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/CodeGen/FuncletLayout.cpp b/llvm/lib/CodeGen/FuncletLayout.cpp index f1222a8..f2dd393 100644 --- a/llvm/lib/CodeGen/FuncletLayout.cpp +++ b/llvm/lib/CodeGen/FuncletLayout.cpp @@ -29,8 +29,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; } diff --git a/llvm/lib/CodeGen/GlobalISel/Combiner.cpp b/llvm/lib/CodeGen/GlobalISel/Combiner.cpp index 733ac41..2cba6f0 100644 --- a/llvm/lib/CodeGen/GlobalISel/Combiner.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Combiner.cpp @@ -255,8 +255,7 @@ bool Combiner::tryDCE(MachineInstr &MI, MachineRegisterInfo &MRI) { bool Combiner::combineMachineInstrs() { // If the ISel pipeline failed, do not bother running this pass. // FIXME: Should this be here or in individual combiner passes. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; // We can't call this in the constructor because the derived class is diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 051d220..fe5dcd1 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -115,7 +115,7 @@ static void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R) { - MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); + MF.getProperties().setFailedISel(); // Print the function name explicitly if we don't have a debug location (which // makes the diagnostic less useful) or if we're going to emit a raw error. diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index 194cbc5..2dd22c8a 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -133,8 +133,7 @@ void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const { bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { // If the ISel pipeline failed, do not bother running that pass. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; ISel = MF.getSubtarget().getInstructionSelector(); @@ -307,7 +306,7 @@ bool InstructionSelect::selectMachineFunction(MachineFunction &MF) { if (!DebugCounter::shouldExecute(GlobalISelCounter)) { dbgs() << "Falling back for function " << MF.getName() << "\n"; - MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); + MF.getProperties().setFailedISel(); return false; } diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp index 1bb3f4b..aef16b5 100644 --- a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp @@ -308,8 +308,7 @@ Legalizer::legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI, bool Legalizer::runOnMachineFunction(MachineFunction &MF) { // If the ISel pipeline failed, do not bother running that pass. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; LLVM_DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n'); init(MF); diff --git a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp index b507c42..78cd9bc 100644 --- a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp @@ -67,8 +67,7 @@ void LoadStoreOpt::init(MachineFunction &MF) { TLI = MF.getSubtarget().getTargetLowering(); LI = MF.getSubtarget().getLegalizerInfo(); Builder.setMF(MF); - IsPreLegalizer = !MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Legalized); + IsPreLegalizer = !MF.getProperties().hasLegalized(); InstsToErase.clear(); } @@ -973,8 +972,7 @@ void LoadStoreOpt::initializeStoreMergeTargetInfo(unsigned AddrSpace) { bool LoadStoreOpt::runOnMachineFunction(MachineFunction &MF) { // If the ISel pipeline failed, do not bother running that pass. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; LLVM_DEBUG(dbgs() << "Begin memory optimizations for: " << MF.getName() diff --git a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp index 5164875..77ca27b 100644 --- a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp @@ -203,8 +203,7 @@ bool Localizer::localizeIntraBlock(LocalizedSetVecT &LocalizedInstrs) { bool Localizer::runOnMachineFunction(MachineFunction &MF) { // If the ISel pipeline failed, do not bother running that pass. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; // Don't run the pass if the target asked so. diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index f1fec54..bcb4f1c 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -733,8 +733,7 @@ bool RegBankSelect::checkFunctionIsLegal(MachineFunction &MF) const { bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) { // If the ISel pipeline failed, do not bother running that pass. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n'); diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index 445a716..64af7a5 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -259,7 +259,7 @@ void llvm::reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R) { - MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); + MF.getProperties().setFailedISel(); reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R); } diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index 400418e..5265bd7 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -217,8 +217,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index 0e0ffa5..b585ce4 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -226,8 +226,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 6e63f1c..a57bda5 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -434,7 +434,7 @@ bool MIRParserImpl::computeFunctionProperties( MF.setHasInlineAsm(HasInlineAsm); if (HasTiedOps && AllTiedOpsRewritten) - Properties.set(MachineFunctionProperties::Property::TiedOpsRewritten); + Properties.setTiedOpsRewritten(); if (ComputedPropertyHelper(YamlMF.IsSSA, isSSA(MF), MachineFunctionProperties::Property::IsSSA)) { @@ -556,21 +556,19 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF, MF.setHasEHFunclets(YamlMF.HasEHFunclets); MF.setIsOutlined(YamlMF.IsOutlined); + MachineFunctionProperties &Props = MF.getProperties(); if (YamlMF.Legalized) - MF.getProperties().set(MachineFunctionProperties::Property::Legalized); + Props.setLegalized(); if (YamlMF.RegBankSelected) - MF.getProperties().set( - MachineFunctionProperties::Property::RegBankSelected); + Props.setRegBankSelected(); if (YamlMF.Selected) - MF.getProperties().set(MachineFunctionProperties::Property::Selected); + Props.setSelected(); if (YamlMF.FailedISel) - MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); + Props.setFailedISel(); if (YamlMF.FailsVerification) - MF.getProperties().set( - MachineFunctionProperties::Property::FailsVerification); + Props.setFailsVerification(); if (YamlMF.TracksDebugUserValues) - MF.getProperties().set( - MachineFunctionProperties::Property::TracksDebugUserValues); + Props.setTracksDebugUserValues(); PerFunctionMIParsingState PFS(MF, SM, IRSlots, *Target); if (parseRegisterInfo(PFS, YamlMF)) diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 368b9eb..b7b8f66 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -188,25 +188,16 @@ static void printMF(raw_ostream &OS, const MachineModuleInfo &MMI, YamlMF.IsOutlined = MF.isOutlined(); YamlMF.UseDebugInstrRef = MF.useDebugInstrRef(); - YamlMF.Legalized = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Legalized); - YamlMF.RegBankSelected = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::RegBankSelected); - YamlMF.Selected = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected); - YamlMF.FailedISel = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel); - YamlMF.FailsVerification = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailsVerification); - YamlMF.TracksDebugUserValues = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::TracksDebugUserValues); - - YamlMF.NoPHIs = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoPHIs); - YamlMF.IsSSA = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::IsSSA); - YamlMF.NoVRegs = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs); + const MachineFunctionProperties &Props = MF.getProperties(); + YamlMF.Legalized = Props.hasLegalized(); + YamlMF.RegBankSelected = Props.hasRegBankSelected(); + YamlMF.Selected = Props.hasSelected(); + YamlMF.FailedISel = Props.hasFailedISel(); + YamlMF.FailsVerification = Props.hasFailsVerification(); + YamlMF.TracksDebugUserValues = Props.hasTracksDebugUserValues(); + YamlMF.NoPHIs = Props.hasNoPHIs(); + YamlMF.IsSSA = Props.hasIsSSA(); + YamlMF.NoVRegs = Props.hasNoVRegs(); convertMRI(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); MachineModuleSlotTracker &MST = State.MST; diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 37fe37f..76227b7 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -1776,17 +1776,15 @@ void MachineBasicBlock::clearLiveIns( } MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const { - assert(getParent()->getProperties().hasProperty( - MachineFunctionProperties::Property::TracksLiveness) && - "Liveness information is accurate"); + assert(getParent()->getProperties().hasTracksLiveness() && + "Liveness information is accurate"); return LiveIns.begin(); } MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const { const MachineFunction &MF = *getParent(); - assert(MF.getProperties().hasProperty( - MachineFunctionProperties::Property::TracksLiveness) && - "Liveness information is accurate"); + assert(MF.getProperties().hasTracksLiveness() && + "Liveness information is accurate"); const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering(); MCRegister ExceptionPointer, ExceptionSelector; diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index bebdead..780ed92 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -153,8 +153,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; } // end anonymous namespace diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 6af3154..49d62e9 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -514,8 +514,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 833b765..607e87a 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -187,8 +187,8 @@ void MachineFunction::handleChangeDesc(MachineInstr &MI, void MachineFunction::init() { // Assume the function starts in SSA form with correct liveness. - Properties.set(MachineFunctionProperties::Property::IsSSA); - Properties.set(MachineFunctionProperties::Property::TracksLiveness); + Properties.setIsSSA(); + Properties.setTracksLiveness(); RegInfo = new (Allocator) MachineRegisterInfo(this); MFInfo = nullptr; diff --git a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp index c8c8ed9..26b6f5a 100644 --- a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp +++ b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp @@ -81,8 +81,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp index ba125d9..e486123 100644 --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -962,10 +962,10 @@ MachineFunction *MachineOutliner::createOutlinedFunction( computeAndPublishHashSequence(MF, OF.Candidates.size()); // Set normal properties for a late MachineFunction. - MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); - MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs); - MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); - MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness); + MF.getProperties().resetIsSSA(); + MF.getProperties().setNoPHIs(); + MF.getProperties().setNoVRegs(); + MF.getProperties().setTracksLiveness(); MF.getRegInfo().freezeReservedRegs(); // Compute live-in set for outlined fn @@ -1111,8 +1111,7 @@ bool MachineOutliner::outline( // anything we outline doesn't break liveness assumptions. The outlined // functions themselves currently don't track liveness, but we should // make sure that the ranges we yank things out of aren't wrong. - if (MBB.getParent()->getProperties().hasProperty( - MachineFunctionProperties::Property::TracksLiveness)) { + if (MBB.getParent()->getProperties().hasTracksLiveness()) { // The following code is to add implicit def operands to the call // instruction. It also updates call site information for moved // code. diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index aa2987b..e3f6eda8f 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -2082,8 +2082,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index a7dbceb..1099882 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -383,8 +383,7 @@ struct MachineVerifierLegacyPass : public MachineFunctionPass { // Skip functions that have known verification problems. // FIXME: Remove this mechanism when all problematic passes have been // fixed. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailsVerification)) + if (MF.getProperties().hasFailsVerification()) return false; MachineVerifier(this, Banner.c_str(), &errs()).verify(MF); @@ -400,8 +399,7 @@ MachineVerifierPass::run(MachineFunction &MF, // Skip functions that have known verification problems. // FIXME: Remove this mechanism when all problematic passes have been // fixed. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailsVerification)) + if (MF.getProperties().hasFailsVerification()) return PreservedAnalyses::all(); MachineVerifier(MFAM, Banner.c_str(), &errs()).verify(MF); return PreservedAnalyses::all(); @@ -462,9 +460,7 @@ void MachineVerifier::verifyProperties(const MachineFunction &MF) { // If a pass has introduced virtual registers without clearing the // NoVRegs property (or set it without allocating the vregs) // then report an error. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs) && - MRI->getNumVirtRegs()) + if (MF.getProperties().hasNoVRegs() && MRI->getNumVirtRegs()) report("Function has NoVRegs property but there are VReg operands", &MF); } @@ -476,8 +472,8 @@ bool MachineVerifier::verify(const MachineFunction &MF) { RBI = MF.getSubtarget().getRegBankInfo(); MRI = &MF.getRegInfo(); - const bool isFunctionFailedISel = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel); + const MachineFunctionProperties &Props = MF.getProperties(); + const bool isFunctionFailedISel = Props.hasFailedISel(); // If we're mid-GlobalISel and we already triggered the fallback path then // it's expected that the MIR is somewhat broken but that's ok since we'll @@ -485,12 +481,9 @@ bool MachineVerifier::verify(const MachineFunction &MF) { if (isFunctionFailedISel) return true; - isFunctionRegBankSelected = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::RegBankSelected); - isFunctionSelected = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected); - isFunctionTracksDebugUserValues = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::TracksDebugUserValues); + isFunctionRegBankSelected = Props.hasRegBankSelected(); + isFunctionSelected = Props.hasSelected(); + isFunctionTracksDebugUserValues = Props.hasTracksDebugUserValues(); if (PASS) { auto *LISWrapper = PASS->getAnalysisIfAvailable<LiveIntervalsWrapperPass>(); @@ -731,8 +724,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { FirstTerminator = nullptr; FirstNonPHI = nullptr; - if (!MF->getProperties().hasProperty( - MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) { + if (!MF->getProperties().hasNoPHIs() && MRI->tracksLiveness()) { // If this block has allocatable physical registers live-in, check that // it is an entry block or landing pad. for (const auto &LI : MBB->liveins()) { @@ -2285,8 +2277,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { report("NoConvergent flag expected only on convergent instructions.", MI); if (MI->isPHI()) { - if (MF->getProperties().hasProperty( - MachineFunctionProperties::Property::NoPHIs)) + if (MF->getProperties().hasNoPHIs()) report("Found PHI instruction with NoPHIs property set", MI); if (FirstNonPHI) @@ -2303,9 +2294,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef()) report("Unspillable Terminator does not define a reg", MI); Register Def = MI->getOperand(0).getReg(); - if (Def.isVirtual() && - !MF->getProperties().hasProperty( - MachineFunctionProperties::Property::NoPHIs) && + if (Def.isVirtual() && !MF->getProperties().hasNoPHIs() && std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1) report("Unspillable Terminator expected to have at most one use!", MI); } @@ -2626,9 +2615,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { // TiedOpsRewritten property to verify two-address constraints, this // property will be set in twoaddressinstruction pass. unsigned DefIdx; - if (MF->getProperties().hasProperty( - MachineFunctionProperties::Property::TiedOpsRewritten) && - MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) && + if (MF->getProperties().hasTiedOpsRewritten() && MO->isUse() && + MI->isRegTiedToDefOperand(MONum, &DefIdx) && Reg != MI->getOperand(DefIdx).getReg()) report("Two-address instruction operands must be identical", MO, MONum); @@ -3729,9 +3717,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, // early-clobber slot if it is being redefined by an early-clobber def. // TODO: Before tied operands are rewritten, a live segment can only end at // an early-clobber slot if the last use is tied to an early-clobber def. - if (MF->getProperties().hasProperty( - MachineFunctionProperties::Property::TiedOpsRewritten) && - S.end.isEarlyClobber()) { + if (MF->getProperties().hasTiedOpsRewritten() && S.end.isEarlyClobber()) { if (I + 1 == LR.end() || (I + 1)->start != S.end) { report("Live segment ending at early clobber slot must be " "redefined by an EC def in the same instruction", diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index 14f91a8..a93a89e 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -152,8 +152,7 @@ public: } MachineFunctionProperties getSetProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } void getAnalysisUsage(AnalysisUsage &AU) const override; @@ -285,7 +284,7 @@ bool PHIEliminationImpl::run(MachineFunction &MF) { ImpDefs.clear(); VRegPHIUseCount.clear(); - MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs); + MF.getProperties().setNoPHIs(); return Changed; } diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp index 07e6c1d..405b9fd 100644 --- a/llvm/lib/CodeGen/PatchableFunction.cpp +++ b/llvm/lib/CodeGen/PatchableFunction.cpp @@ -38,8 +38,7 @@ struct PatchableFunctionLegacy : public MachineFunctionPass { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index 27b22e6..81f14a4 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -577,8 +577,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 039a473..06e5b18 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -106,8 +106,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } bool runOnMachineFunction(MachineFunction &Fn) override; diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp index be81eca..6c84cc2 100644 --- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp @@ -48,8 +48,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; } // end anonymous namespace diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 961b2f0..7b149cf 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -659,8 +659,7 @@ void PEIImpl::spillCalleeSavedRegs(MachineFunction &MF) { // pipeline is set up without giving the passes a chance to look at the // TargetMachine. // FIXME: Find a way to express this in getRequiredProperties. - assert(MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs)); + assert(MF.getProperties().hasNoVRegs()); const Function &F = MF.getFunction(); const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp index b9599e7..69b9291 100644 --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -216,10 +216,9 @@ MCPhysReg RegAllocBase::getErrorAssignment(const TargetRegisterClass &RC, // Avoid printing the error for every single instance of the register. It // would be better if this were per register class. - bool EmitError = !MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedRegAlloc); + bool EmitError = !MF.getProperties().hasFailedRegAlloc(); if (EmitError) - MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc); + MF.getProperties().setFailedRegAlloc(); const Function &Fn = MF.getFunction(); LLVMContext &Context = Fn.getContext(); diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index 51e047b..381249e 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -105,13 +105,11 @@ public: bool runOnMachineFunction(MachineFunction &mf) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } // Helper for spilling all live virtual registers currently unified under preg diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index bb118dd..66a206c 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -417,22 +417,19 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } MachineFunctionProperties getSetProperties() const override { if (Impl.ClearVirtRegs) { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } return MachineFunctionProperties(); } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; @@ -1196,10 +1193,9 @@ MCPhysReg RegAllocFastImpl::getErrorAssignment(const LiveReg &LR, MachineFunction &MF = *MI.getMF(); // Avoid repeating the error every time a register is used. - bool EmitError = !MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedRegAlloc); + bool EmitError = !MF.getProperties().hasFailedRegAlloc(); if (EmitError) - MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc); + MF.getProperties().setFailedRegAlloc(); // If the allocation order was empty, all registers in the class were // probably reserved. Fall back to taking the first register in the class, diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index c938480..fa384b2 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -158,13 +158,11 @@ public: bool runOnMachineFunction(MachineFunction &mf) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index e230a1b..048cd21 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -135,13 +135,11 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } private: diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index c27435a..2d25f09 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -398,8 +398,7 @@ public: void getAnalysisUsage(AnalysisUsage &AU) const override; MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } /// This is the pass entry point. diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index f5bc902..7e26c2e 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -467,7 +467,7 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) { MachineRegisterInfo &MRI = MF.getRegInfo(); // Shortcut. if (MRI.getNumVirtRegs() == 0) { - MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); + MF.getProperties().setNoVRegs(); return; } @@ -489,7 +489,7 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) { } MRI.clearVirtRegs(); - MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); + MF.getProperties().setNoVRegs(); } namespace { diff --git a/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp b/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp index 0c05473c..ea0ea02 100644 --- a/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp +++ b/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp @@ -58,8 +58,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp index 0cebad4..4a0ceed 100644 --- a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp +++ b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp @@ -60,8 +60,7 @@ namespace { auto ClearVRegTypesOnReturn = make_scope_exit([&MF]() { MF.getRegInfo().clearVirtRegTypes(); }); - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) { + if (MF.getProperties().hasFailedISel()) { if (AbortOnFailedISel) report_fatal_error("Instruction selection failed"); LLVM_DEBUG(dbgs() << "Resetting: " << MF.getName() << '\n'); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 586728a..4bdb8e6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -345,8 +345,7 @@ SelectionDAGISelLegacy::SelectionDAGISelLegacy( bool SelectionDAGISelLegacy::runOnMachineFunction(MachineFunction &MF) { // If we already selected that function, we do not need to run SDISel. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected)) + if (MF.getProperties().hasSelected()) return false; // Do some sanity-checking on the command-line options. @@ -421,8 +420,7 @@ PreservedAnalyses SelectionDAGISelPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { // If we already selected that function, we do not need to run SDISel. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected)) + if (MF.getProperties().hasSelected()) return PreservedAnalyses::all(); // Do some sanity-checking on the command-line options. diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp index 1781e62..41e956c 100644 --- a/llvm/lib/CodeGen/ShrinkWrap.cpp +++ b/llvm/lib/CodeGen/ShrinkWrap.cpp @@ -275,8 +275,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "Shrink Wrapping analysis"; } diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp index 8437422..462d9e0 100644 --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -62,8 +62,7 @@ public: void getAnalysisUsage(AnalysisUsage &AU) const override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } /// Calculate the liveness information for the given machine function. diff --git a/llvm/lib/CodeGen/TailDuplication.cpp b/llvm/lib/CodeGen/TailDuplication.cpp index a50cdcf..bcec318 100644 --- a/llvm/lib/CodeGen/TailDuplication.cpp +++ b/llvm/lib/CodeGen/TailDuplication.cpp @@ -66,8 +66,7 @@ public: } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties() - .set(MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } }; diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 3e29f62..8b82deb 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1846,8 +1846,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI, // To simplify the sub-register handling, verify that we only need to // consider physical registers. - assert(MF->getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs)); + assert(MF->getProperties().hasNoVRegs()); if (auto DestSrc = isCopyInstr(MI)) { Register DestReg = DestSrc->Destination->getReg(); diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 36e2156..8d94b40 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1837,8 +1837,7 @@ bool TwoAddressInstructionImpl::run() { MRI->leaveSSA(); // This pass will rewrite the tied-def to meet the RegConstraint. - MF->getProperties() - .set(MachineFunctionProperties::Property::TiedOpsRewritten); + MF->getProperties().setTiedOpsRewritten(); TiedOperandMap TiedOperands; for (MachineBasicBlock &MBBI : *MF) { diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 49e819e..3d6ccba 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -244,8 +244,7 @@ public: MachineFunctionProperties getSetProperties() const override { if (ClearVirtRegs) { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } return MachineFunctionProperties(); |