diff options
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/ModuloSchedule.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp index 8e8cdb2..3245d96 100644 --- a/llvm/lib/CodeGen/ModuloSchedule.cpp +++ b/llvm/lib/CodeGen/ModuloSchedule.cpp @@ -1447,7 +1447,7 @@ Register KernelRewriter::remapUse(Register Reg, MachineInstr &MI) { Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, const TargetRegisterClass *RC) { // If the init register is not undef, try and find an existing phi. - if (InitReg.hasValue()) { + if (InitReg) { auto I = Phis.find({LoopReg, InitReg.getValue()}); if (I != Phis.end()) return I->second; @@ -1483,18 +1483,18 @@ Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, if (!RC) RC = MRI.getRegClass(LoopReg); Register R = MRI.createVirtualRegister(RC); - if (InitReg.hasValue()) { + if (InitReg) { const TargetRegisterClass *ConstrainRegClass = MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); assert(ConstrainRegClass && "Expected a valid constrained register class!"); (void)ConstrainRegClass; } BuildMI(*BB, BB->getFirstNonPHI(), DebugLoc(), TII->get(TargetOpcode::PHI), R) - .addReg(InitReg.hasValue() ? *InitReg : undef(RC)) + .addReg(InitReg ? *InitReg : undef(RC)) .addMBB(PreheaderBB) .addReg(LoopReg) .addMBB(BB); - if (!InitReg.hasValue()) + if (!InitReg) UndefPhis[LoopReg] = R; else Phis[{LoopReg, *InitReg}] = R; |