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-rw-r--r--llvm/include/llvm/ADT/EquivalenceClasses.h8
-rw-r--r--llvm/include/llvm/Analysis/VectorUtils.h5
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h23
-rw-r--r--llvm/include/llvm/CodeGen/TargetLowering.h15
-rw-r--r--llvm/include/llvm/IR/IntrinsicsSPIRV.td7
-rw-r--r--llvm/include/llvm/IR/OptBisect.h35
-rw-r--r--llvm/include/llvm/IR/RuntimeLibcalls.td2
-rw-r--r--llvm/include/llvm/MC/MCAssembler.h8
-rw-r--r--llvm/include/llvm/MC/MCELFStreamer.h3
-rw-r--r--llvm/include/llvm/MC/MCObjectStreamer.h14
-rw-r--r--llvm/include/llvm/MC/MCStreamer.h10
-rw-r--r--llvm/include/llvm/Object/ELFObjectFile.h8
-rw-r--r--llvm/include/llvm/Pass.h4
-rw-r--r--llvm/include/llvm/Target/GlobalISel/Combine.td20
-rw-r--r--llvm/include/llvm/TargetParser/Host.h2
-rw-r--r--llvm/include/llvm/TargetParser/Triple.h122
-rw-r--r--llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h1
17 files changed, 172 insertions, 115 deletions
diff --git a/llvm/include/llvm/ADT/EquivalenceClasses.h b/llvm/include/llvm/ADT/EquivalenceClasses.h
index b1009f8..1a2331c 100644
--- a/llvm/include/llvm/ADT/EquivalenceClasses.h
+++ b/llvm/include/llvm/ADT/EquivalenceClasses.h
@@ -218,12 +218,12 @@ public:
/// insert - Insert a new value into the union/find set, ignoring the request
/// if the value already exists.
const ECValue &insert(const ElemTy &Data) {
- auto I = TheMapping.insert({Data, nullptr});
- if (!I.second)
- return *I.first->second;
+ auto [I, Inserted] = TheMapping.try_emplace(Data);
+ if (!Inserted)
+ return *I->second;
auto *ECV = new (ECValueAllocator) ECValue(Data);
- I.first->second = ECV;
+ I->second = ECV;
Members.push_back(ECV);
return *ECV;
}
diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h
index af1e0d7..9a2773c 100644
--- a/llvm/include/llvm/Analysis/VectorUtils.h
+++ b/llvm/include/llvm/Analysis/VectorUtils.h
@@ -24,6 +24,7 @@
namespace llvm {
class TargetLibraryInfo;
+class IntrinsicInst;
/// The Vector Function Database.
///
@@ -188,6 +189,10 @@ LLVM_ABI unsigned getInterleaveIntrinsicFactor(Intrinsic::ID ID);
/// Returns the corresponding factor of llvm.vector.deinterleaveN intrinsics.
LLVM_ABI unsigned getDeinterleaveIntrinsicFactor(Intrinsic::ID ID);
+/// Given a deinterleaveN intrinsic, return the (narrow) vector type of each
+/// factor.
+LLVM_ABI VectorType *getDeinterleavedVectorType(IntrinsicInst *DI);
+
/// Given a vector and an element number, see if the scalar value is
/// already around as a register, for example if it were inserted then extracted
/// from the vector.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 31f1197b..da82904 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -700,18 +700,19 @@ public:
/// Given an G_UDIV \p MI or G_UREM \p MI expressing a divide by constant,
/// return an expression that implements it by multiplying by a magic number.
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
- MachineInstr *buildUDivorURemUsingMul(MachineInstr &MI) const;
+ MachineInstr *buildUDivOrURemUsingMul(MachineInstr &MI) const;
/// Combine G_UDIV or G_UREM by constant into a multiply by magic constant.
- bool matchUDivorURemByConst(MachineInstr &MI) const;
- void applyUDivorURemByConst(MachineInstr &MI) const;
-
- /// Given an G_SDIV \p MI expressing a signed divide by constant, return an
- /// expression that implements it by multiplying by a magic number.
- /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
- MachineInstr *buildSDivUsingMul(MachineInstr &MI) const;
- /// Combine G_SDIV by constant into a multiply by magic constant.
- bool matchSDivByConst(MachineInstr &MI) const;
- void applySDivByConst(MachineInstr &MI) const;
+ bool matchUDivOrURemByConst(MachineInstr &MI) const;
+ void applyUDivOrURemByConst(MachineInstr &MI) const;
+
+ /// Given an G_SDIV \p MI or G_SREM \p MI expressing a signed divide by
+ /// constant, return an expression that implements it by multiplying by a
+ /// magic number. Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's
+ /// Guide".
+ MachineInstr *buildSDivOrSRemUsingMul(MachineInstr &MI) const;
+ /// Combine G_SDIV or G_SREM by constant into a multiply by magic constant.
+ bool matchSDivOrSRemByConst(MachineInstr &MI) const;
+ void applySDivOrSRemByConst(MachineInstr &MI) const;
/// Given an G_SDIV \p MI expressing a signed divided by a pow2 constant,
/// return expressions that implements it by shifting.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 72594c7..084b788 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3251,10 +3251,9 @@ public:
///
/// \p Load is the accompanying load instruction. Can be either a plain load
/// instruction or a vp.load intrinsic.
- /// \p DeinterleaveValues contains the deinterleaved values.
- virtual bool
- lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask,
- ArrayRef<Value *> DeinterleaveValues) const {
+ /// \p DI represents the deinterleaveN intrinsic.
+ virtual bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask,
+ IntrinsicInst *DI) const {
return false;
}
@@ -3262,10 +3261,14 @@ public:
/// Return true on success. Currently only supports
/// llvm.vector.interleave{2,3,5,7}
///
- /// \p SI is the accompanying store instruction
+ /// \p Store is the accompanying store instruction. Can be either a plain
+ /// store or a vp.store intrinsic.
+ /// \p Mask is a per-segment (i.e. number of lanes equal to that of one
+ /// component being interwoven) mask. Can be nullptr, in which case the
+ /// result is uncondiitional.
/// \p InterleaveValues contains the interleaved values.
virtual bool
- lowerInterleaveIntrinsicToStore(StoreInst *SI,
+ lowerInterleaveIntrinsicToStore(Instruction *Store, Value *Mask,
ArrayRef<Value *> InterleaveValues) const {
return false;
}
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 35c9cd6..b5f0cdf 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -90,7 +90,12 @@ let TargetPrefix = "spv" in {
def int_spv_length : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_spv_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_spv_reflect : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;
- def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
+ def int_spv_refract
+ : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
+ [llvm_anyfloat_ty, LLVMMatchType<0>,
+ llvm_anyfloat_ty],
+ [IntrNoMem]>;
+def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_spv_saturate : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_spv_smoothstep : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
def int_spv_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [LLVMMatchType<0>, llvm_anyfloat_ty], [IntrNoMem]>;
diff --git a/llvm/include/llvm/IR/OptBisect.h b/llvm/include/llvm/IR/OptBisect.h
index ea3c1de..d813ae9 100644
--- a/llvm/include/llvm/IR/OptBisect.h
+++ b/llvm/include/llvm/IR/OptBisect.h
@@ -15,6 +15,7 @@
#define LLVM_IR_OPTBISECT_H
#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSet.h"
#include "llvm/Support/Compiler.h"
#include <limits>
@@ -82,8 +83,38 @@ private:
mutable int LastBisectNum = 0;
};
-/// Singleton instance of the OptBisect class, so multiple pass managers don't
-/// need to coordinate their uses of OptBisect.
+/// This class implements a mechanism to disable passes and individual
+/// optimizations at compile time based on a command line option
+/// (-opt-disable) in order to study how single transformations, or
+/// combinations thereof, affect the IR.
+class LLVM_ABI OptDisable : public OptPassGate {
+public:
+ /// Checks the pass name to determine if the specified pass should run.
+ ///
+ /// It returns true if the pass should run, i.e. if its name is was
+ /// not provided via command line.
+ /// If -opt-disable-enable-verbosity is given, the method prints the
+ /// name of the pass, and whether or not the pass will be executed.
+ ///
+ /// Most passes should not call this routine directly. Instead, it is called
+ /// through helper routines provided by the base classes of the pass. For
+ /// instance, function passes should call FunctionPass::skipFunction().
+ bool shouldRunPass(StringRef PassName,
+ StringRef IRDescription) const override;
+
+ /// Parses the command line argument to extract the names of the passes
+ /// to be disabled. Multiple pass names can be provided with comma separation.
+ void setDisabled(StringRef Pass);
+
+ /// isEnabled() should return true before calling shouldRunPass().
+ bool isEnabled() const override { return !DisabledPasses.empty(); }
+
+private:
+ StringSet<> DisabledPasses = {};
+};
+
+/// Singleton instance of the OptPassGate class, so multiple pass managers don't
+/// need to coordinate their uses of OptBisect and OptDisable.
LLVM_ABI OptPassGate &getGlobalPassGate();
} // end namespace llvm
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td
index 11926d4..f0297cd 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -2129,7 +2129,7 @@ defvar X86CommonLibcalls =
);
defvar Windows32DivRemMulCalls =
- LibcallImpls<(add WindowsDivRemMulLibcalls),
+ LibcallsWithCC<(add WindowsDivRemMulLibcalls), X86_STDCALL,
RuntimeLibcallPredicate<"TT.isWindowsMSVCEnvironment() || TT.isWindowsItaniumEnvironment()">>;
def X86_32SystemLibrary
diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h
index aa396ef..ade9ee6f 100644
--- a/llvm/include/llvm/MC/MCAssembler.h
+++ b/llvm/include/llvm/MC/MCAssembler.h
@@ -69,6 +69,13 @@ private:
SmallVector<const MCSymbol *, 0> Symbols;
+ struct RelocDirective {
+ const MCExpr &Offset;
+ const MCExpr *Expr;
+ uint32_t Kind;
+ };
+ SmallVector<RelocDirective, 0> relocDirectives;
+
mutable SmallVector<std::pair<SMLoc, std::string>, 0> PendingErrors;
MCDwarfLineTableParams LTParams;
@@ -205,6 +212,7 @@ public:
LLVM_ABI bool registerSection(MCSection &Section);
LLVM_ABI bool registerSymbol(const MCSymbol &Symbol);
+ void addRelocDirective(RelocDirective RD);
LLVM_ABI void reportError(SMLoc L, const Twine &Msg) const;
// Record pending errors during layout iteration, as they may go away once the
diff --git a/llvm/include/llvm/MC/MCELFStreamer.h b/llvm/include/llvm/MC/MCELFStreamer.h
index ad0961c..144f6bc 100644
--- a/llvm/include/llvm/MC/MCELFStreamer.h
+++ b/llvm/include/llvm/MC/MCELFStreamer.h
@@ -141,7 +141,8 @@ public:
}
private:
- void finalizeCGProfileEntry(const MCSymbolRefExpr *&S, uint64_t Offset);
+ void finalizeCGProfileEntry(const MCSymbolRefExpr *Sym, uint64_t Offset,
+ const MCSymbolRefExpr *&S);
void finalizeCGProfile();
bool SeenIdent = false;
diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h
index e2a77b8..a55fd4a 100644
--- a/llvm/include/llvm/MC/MCObjectStreamer.h
+++ b/llvm/include/llvm/MC/MCObjectStreamer.h
@@ -40,14 +40,6 @@ class MCObjectStreamer : public MCStreamer {
std::unique_ptr<MCAssembler> Assembler;
bool EmitEHFrame;
bool EmitDebugFrame;
- struct PendingMCFixup {
- const MCSymbol *Sym;
- MCFixup Fixup;
- MCFragment *DF;
- PendingMCFixup(const MCSymbol *McSym, MCFragment *F, MCFixup McFixup)
- : Sym(McSym), Fixup(McFixup), DF(F) {}
- };
- SmallVector<PendingMCFixup, 2> PendingFixups;
struct PendingAssignment {
MCSymbol *Symbol;
@@ -63,7 +55,6 @@ class MCObjectStreamer : public MCStreamer {
void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;
void emitInstructionImpl(const MCInst &Inst, const MCSubtargetInfo &STI);
- void resolvePendingFixups();
protected:
MCObjectStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
@@ -162,9 +153,8 @@ public:
void emitCVStringTableDirective() override;
void emitCVFileChecksumsDirective() override;
void emitCVFileChecksumOffsetDirective(unsigned FileNo) override;
- std::optional<std::pair<bool, std::string>>
- emitRelocDirective(const MCExpr &Offset, StringRef Name, const MCExpr *Expr,
- SMLoc Loc, const MCSubtargetInfo &STI) override;
+ void emitRelocDirective(const MCExpr &Offset, StringRef Name,
+ const MCExpr *Expr, SMLoc Loc = {}) override;
using MCStreamer::emitFill;
void emitFill(const MCExpr &NumBytes, uint64_t FillValue,
SMLoc Loc = SMLoc()) override;
diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h
index 1f7c8b5..b3a9aab 100644
--- a/llvm/include/llvm/MC/MCStreamer.h
+++ b/llvm/include/llvm/MC/MCStreamer.h
@@ -1048,13 +1048,9 @@ public:
virtual void emitSyntaxDirective();
- /// Record a relocation described by the .reloc directive. Return std::nullopt
- /// if succeeded. Otherwise, return a pair (Name is invalid, error message).
- virtual std::optional<std::pair<bool, std::string>>
- emitRelocDirective(const MCExpr &Offset, StringRef Name, const MCExpr *Expr,
- SMLoc Loc, const MCSubtargetInfo &STI) {
- return std::nullopt;
- }
+ /// Record a relocation described by the .reloc directive.
+ virtual void emitRelocDirective(const MCExpr &Offset, StringRef Name,
+ const MCExpr *Expr, SMLoc Loc = {}) {}
virtual void emitAddrsig() {}
virtual void emitAddrsigSym(const MCSymbol *Sym) {}
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h
index 1036868..a3aa0d9 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -1312,7 +1312,7 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
case ELF::EM_PPC:
return (IsLittleEndian ? "elf32-powerpcle" : "elf32-powerpc");
case ELF::EM_RISCV:
- return "elf32-littleriscv";
+ return (IsLittleEndian ? "elf32-littleriscv" : "elf32-bigriscv");
case ELF::EM_CSKY:
return "elf32-csky";
case ELF::EM_SPARC:
@@ -1338,7 +1338,7 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
case ELF::EM_PPC64:
return (IsLittleEndian ? "elf64-powerpcle" : "elf64-powerpc");
case ELF::EM_RISCV:
- return "elf64-littleriscv";
+ return (IsLittleEndian ? "elf64-littleriscv" : "elf64-bigriscv");
case ELF::EM_S390:
return "elf64-s390";
case ELF::EM_SPARCV9:
@@ -1400,9 +1400,9 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
case ELF::EM_RISCV:
switch (EF.getHeader().e_ident[ELF::EI_CLASS]) {
case ELF::ELFCLASS32:
- return Triple::riscv32;
+ return IsLittleEndian ? Triple::riscv32 : Triple::riscv32be;
case ELF::ELFCLASS64:
- return Triple::riscv64;
+ return IsLittleEndian ? Triple::riscv64 : Triple::riscv64be;
default:
report_fatal_error("Invalid ELFCLASS!");
}
diff --git a/llvm/include/llvm/Pass.h b/llvm/include/llvm/Pass.h
index 2ecd47d..f3962c3 100644
--- a/llvm/include/llvm/Pass.h
+++ b/llvm/include/llvm/Pass.h
@@ -114,6 +114,10 @@ public:
/// Registration templates, but can be overloaded directly.
virtual StringRef getPassName() const;
+ /// Return a nice clean name for a pass
+ /// corresponding to that used to enable the pass in opt.
+ StringRef getPassArgument() const;
+
/// getPassID - Return the PassID number that corresponds to this pass.
AnalysisID getPassID() const {
return PassID;
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 66051d7..fc81ab7 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1132,14 +1132,14 @@ def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg,
def udiv_by_const : GICombineRule<
(defs root:$root),
(match (G_UDIV $dst, $x, $y):$root,
- [{ return Helper.matchUDivorURemByConst(*${root}); }]),
- (apply [{ Helper.applyUDivorURemByConst(*${root}); }])>;
+ [{ return Helper.matchUDivOrURemByConst(*${root}); }]),
+ (apply [{ Helper.applyUDivOrURemByConst(*${root}); }])>;
def sdiv_by_const : GICombineRule<
(defs root:$root),
(match (G_SDIV $dst, $x, $y):$root,
- [{ return Helper.matchSDivByConst(*${root}); }]),
- (apply [{ Helper.applySDivByConst(*${root}); }])>;
+ [{ return Helper.matchSDivOrSRemByConst(*${root}); }]),
+ (apply [{ Helper.applySDivOrSRemByConst(*${root}); }])>;
def sdiv_by_pow2 : GICombineRule<
(defs root:$root),
@@ -1159,10 +1159,16 @@ def intdiv_combines : GICombineGroup<[udiv_by_pow2, sdiv_by_pow2,
def urem_by_const : GICombineRule<
(defs root:$root),
(match (G_UREM $dst, $x, $y):$root,
- [{ return Helper.matchUDivorURemByConst(*${root}); }]),
- (apply [{ Helper.applyUDivorURemByConst(*${root}); }])>;
+ [{ return Helper.matchUDivOrURemByConst(*${root}); }]),
+ (apply [{ Helper.applyUDivOrURemByConst(*${root}); }])>;
-def intrem_combines : GICombineGroup<[urem_by_const]>;
+def srem_by_const : GICombineRule<
+ (defs root:$root),
+ (match (G_SREM $dst, $x, $y):$root,
+ [{ return Helper.matchSDivOrSRemByConst(*${root}); }]),
+ (apply [{ Helper.applySDivOrSRemByConst(*${root}); }])>;
+
+def intrem_combines : GICombineGroup<[urem_by_const, srem_by_const]>;
def reassoc_ptradd : GICombineRule<
(defs root:$root, build_fn_matchinfo:$matchinfo),
diff --git a/llvm/include/llvm/TargetParser/Host.h b/llvm/include/llvm/TargetParser/Host.h
index be3d41e..40a9b6c 100644
--- a/llvm/include/llvm/TargetParser/Host.h
+++ b/llvm/include/llvm/TargetParser/Host.h
@@ -53,7 +53,7 @@ LLVM_ABI StringRef getHostCPUName();
/// which features may appear in this map, except that they are all valid LLVM
/// feature names. The map can be empty, for example if feature detection
/// fails.
-LLVM_ABI const StringMap<bool, MallocAllocator> getHostCPUFeatures();
+LLVM_ABI StringMap<bool, MallocAllocator> getHostCPUFeatures();
/// This is a function compatible with cl::AddExtraVersionPrinter, which adds
/// info about the current target triple and detected CPU.
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 57d771b..670a632 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -49,62 +49,64 @@ public:
enum ArchType {
UnknownArch,
- arm, // ARM (little endian): arm, armv.*, xscale
- armeb, // ARM (big endian): armeb
- aarch64, // AArch64 (little endian): aarch64
- aarch64_be, // AArch64 (big endian): aarch64_be
- aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
- arc, // ARC: Synopsys ARC
- avr, // AVR: Atmel AVR microcontroller
- bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
- bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
- csky, // CSKY: csky
- dxil, // DXIL 32-bit DirectX bytecode
- hexagon, // Hexagon: hexagon
- loongarch32, // LoongArch (32-bit): loongarch32
- loongarch64, // LoongArch (64-bit): loongarch64
- m68k, // M68k: Motorola 680x0 family
- mips, // MIPS: mips, mipsallegrex, mipsr6
- mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
- mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
- mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
- msp430, // MSP430: msp430
- ppc, // PPC: powerpc
- ppcle, // PPCLE: powerpc (little endian)
- ppc64, // PPC64: powerpc64, ppu
- ppc64le, // PPC64LE: powerpc64le
- r600, // R600: AMD GPUs HD2XXX - HD6XXX
- amdgcn, // AMDGCN: AMD GCN GPUs
- riscv32, // RISC-V (32-bit): riscv32
- riscv64, // RISC-V (64-bit): riscv64
- sparc, // Sparc: sparc
- sparcv9, // Sparcv9: Sparcv9
- sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
- systemz, // SystemZ: s390x
- tce, // TCE (http://tce.cs.tut.fi/): tce
- tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
- thumb, // Thumb (little endian): thumb, thumbv.*
- thumbeb, // Thumb (big endian): thumbeb
- x86, // X86: i[3-9]86
- x86_64, // X86-64: amd64, x86_64
- xcore, // XCore: xcore
- xtensa, // Tensilica: Xtensa
- nvptx, // NVPTX: 32-bit
- nvptx64, // NVPTX: 64-bit
- amdil, // AMDIL
- amdil64, // AMDIL with 64-bit pointers
- hsail, // AMD HSAIL
- hsail64, // AMD HSAIL with 64-bit pointers
- spir, // SPIR: standard portable IR for OpenCL 32-bit version
- spir64, // SPIR: standard portable IR for OpenCL 64-bit version
- spirv, // SPIR-V with logical memory layout.
- spirv32, // SPIR-V with 32-bit pointers
- spirv64, // SPIR-V with 64-bit pointers
- kalimba, // Kalimba: generic kalimba
- shave, // SHAVE: Movidius vector VLIW processors
- lanai, // Lanai: Lanai 32-bit
- wasm32, // WebAssembly with 32-bit pointers
- wasm64, // WebAssembly with 64-bit pointers
+ arm, // ARM (little endian): arm, armv.*, xscale
+ armeb, // ARM (big endian): armeb
+ aarch64, // AArch64 (little endian): aarch64
+ aarch64_be, // AArch64 (big endian): aarch64_be
+ aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
+ arc, // ARC: Synopsys ARC
+ avr, // AVR: Atmel AVR microcontroller
+ bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
+ bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
+ csky, // CSKY: csky
+ dxil, // DXIL 32-bit DirectX bytecode
+ hexagon, // Hexagon: hexagon
+ loongarch32, // LoongArch (32-bit): loongarch32
+ loongarch64, // LoongArch (64-bit): loongarch64
+ m68k, // M68k: Motorola 680x0 family
+ mips, // MIPS: mips, mipsallegrex, mipsr6
+ mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
+ mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
+ mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
+ msp430, // MSP430: msp430
+ ppc, // PPC: powerpc
+ ppcle, // PPCLE: powerpc (little endian)
+ ppc64, // PPC64: powerpc64, ppu
+ ppc64le, // PPC64LE: powerpc64le
+ r600, // R600: AMD GPUs HD2XXX - HD6XXX
+ amdgcn, // AMDGCN: AMD GCN GPUs
+ riscv32, // RISC-V (32-bit, little endian): riscv32
+ riscv64, // RISC-V (64-bit, little endian): riscv64
+ riscv32be, // RISC-V (32-bit, big endian): riscv32be
+ riscv64be, // RISC-V (64-bit, big endian): riscv64be
+ sparc, // Sparc: sparc
+ sparcv9, // Sparcv9: Sparcv9
+ sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
+ systemz, // SystemZ: s390x
+ tce, // TCE (http://tce.cs.tut.fi/): tce
+ tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
+ thumb, // Thumb (little endian): thumb, thumbv.*
+ thumbeb, // Thumb (big endian): thumbeb
+ x86, // X86: i[3-9]86
+ x86_64, // X86-64: amd64, x86_64
+ xcore, // XCore: xcore
+ xtensa, // Tensilica: Xtensa
+ nvptx, // NVPTX: 32-bit
+ nvptx64, // NVPTX: 64-bit
+ amdil, // AMDIL
+ amdil64, // AMDIL with 64-bit pointers
+ hsail, // AMD HSAIL
+ hsail64, // AMD HSAIL with 64-bit pointers
+ spir, // SPIR: standard portable IR for OpenCL 32-bit version
+ spir64, // SPIR: standard portable IR for OpenCL 64-bit version
+ spirv, // SPIR-V with logical memory layout.
+ spirv32, // SPIR-V with 32-bit pointers
+ spirv64, // SPIR-V with 64-bit pointers
+ kalimba, // Kalimba: generic kalimba
+ shave, // SHAVE: Movidius vector VLIW processors
+ lanai, // Lanai: Lanai 32-bit
+ wasm32, // WebAssembly with 32-bit pointers
+ wasm64, // WebAssembly with 64-bit pointers
renderscript32, // 32-bit RenderScript
renderscript64, // 64-bit RenderScript
ve, // NEC SX-Aurora Vector Engine
@@ -1064,10 +1066,14 @@ public:
}
/// Tests whether the target is 32-bit RISC-V.
- bool isRISCV32() const { return getArch() == Triple::riscv32; }
+ bool isRISCV32() const {
+ return getArch() == Triple::riscv32 || getArch() == Triple::riscv32be;
+ }
/// Tests whether the target is 64-bit RISC-V.
- bool isRISCV64() const { return getArch() == Triple::riscv64; }
+ bool isRISCV64() const {
+ return getArch() == Triple::riscv64 || getArch() == Triple::riscv64be;
+ }
/// Tests whether the target is RISC-V (32- and 64-bit).
bool isRISCV() const { return isRISCV32() || isRISCV64(); }
diff --git a/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h b/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
index a101151..39fef92 100644
--- a/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
+++ b/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
@@ -530,6 +530,7 @@ private:
bool isExpandedAddRecExprPHI(PHINode *PN, Instruction *IncV, const Loop *L);
+ Value *tryToReuseLCSSAPhi(const SCEVAddRecExpr *S);
Value *expandAddRecExprLiterally(const SCEVAddRecExpr *);
PHINode *getAddRecExprPHILiterally(const SCEVAddRecExpr *Normalized,
const Loop *L, Type *&TruncTy,
generated by cgit v1.1 at 2025-07-18 02:39:24 +0000